MC16XSD200FK

NXP Semiconductors Data Sheet: Advance Information Document Number: MC16XSD200 Rev. 4.0, 5/2018 Dual 16 mOhm high-side switch 16XSD200 The 16XSD200 device is part of a 36 V dual high-side switch product family with integrated control, and a high number of protective and diagnostic functions. It has been designed for industrial applications. The low RDS(ON) channels ( VPWR /2 and “Off” when V(HS[x]) < VPWR /2. The channel’s switching state should not be confused with the device’s internal channel control state hson[x] (= High Side On). Signal hson[x] defines the targeted switching state of the channel (On/Off). It is either controlled by the value of the direct input signal or by that of the internal/external clock signals combined with the SPI register settings. The value of hson[x] is given by the following boolean expression: hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and PWM_en[x] = 0)]. In this expression Duty_cycle[x] represents the value of the duty cycle, set by bits D7…D0 of the PWMR register (Table 7). The channel’s actual switching state may differ from the control signal’s state in the following cases: • • • • • short-circuits to GND, before automatic turn-off (t < tFAULT) short-circuits to VPWR when the channel is set to Off VPWR < 13 V when Openload in OFF state detection is selected and the load is actually lost during the turn-on transition as long as V(HS[x])< VPWR/2 during the turn-off transition as long as V(HS[x]) > VPWR/2 6.1.3.3 Entering and maintaining Normal mode A 0-to-1 transition on RSTB, (when both VPWR and VDD are present) or on any of both direct inputs IN[x] (when only supplied by VPWR) puts the device in Normal mode. If desired, the device can be operated in Normal mode without VDD, but this requires that at least one of both direct inputs be regularly turned on (Operation and operating modes). To maintain the device in Normal mode (NM), communication must take place on a regular basis. For SPI communication, the state of the WDIN bit must be alternated at least every 310 ms (typ.) (tWDTO), unless the WD_disable bit is set to 1. For direct input control, the timing requirements are shown in Figure 11. A signal called IN_ON[x] is not directly accessible to the user but is used by the internal logic circuitry to determine the device state. When no activity is detected on a direct input pin (IN[x]) for a time longer than tIN = 250 ms (typ.), timeout is detected and IN_ON[x] goes low. When this occurs on both channels, Sleep mode is entered (Sleep mode), provided reset = RSTB = 0. . IN[x] tIN IN_ON[x] Figure 11. Relation between signals IN(x) and IN_ON[x] 6.1.3.4 Direct control mode When RSTB = 0 (and also in Fail-safe mode), the channels are merely controlled by the direct input pins IN[x]. All protective functions (OC, OT, SC, OV, and UV) are operational including auto-retry. To avoid entering Sleep mode at frequencies < 4.0 Hz, reset should be set to RSTB = 1. 16XSD200 NXP Semiconductors 28 6.1.3.5 Going from Normal to Fail-safe, Fault or Sleep mode The device changes from Normal to Fail-safe (Fail-safe mode), Sleep mode (Sleep mode), or Fault mode (Fault mode), according to the value of the following signals (see Table 6). • wake-up = RSTB or IN_ON[0] or IN_ON[1] • fail-safe = (VDD Failure and VDD_FAIL_en) or (SPI watchdog timeout (tWDTO) and WD_dis = 0) • fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis) Table 6. Device operating modes Wake-up Mode Fail-safe Fault Comments Sleep 0 x x All channels are OFF. Normal 1 0 0 The SPI Watchdog is active when: VDD = 5.0 V, WD_dis = 0, RSTB = 1 Fail-safe 1 1 0 The channels are controlled by the IN inputs. (see Fail-safe mode) Fault 1 X 1 The channels are OFF, see Fault mode. x = Don’t care. It enters Fail-safe mode in case of a timeout on SPI communication or when VDD is lost after having been initially present (if this function was previously enabled by setting: VDD_FAIL_EN bit = [1]). Setting watchdog disabled (WD_dis = 1, D4 of the GCR register) avoids entering Fail-safe mode after watchdog timeout. Device behavior upon fault occurrence is explained in the paragraph on Faults (Fault mode). Sleep (wake-up = 0) (wake-up = 1) and (fail-safe = 1) and (fault = 0) (wake-up = 1) and (fault = 1) (wake-up = 0) (fail-safe = 1) and (wake-up = 1) and (fault = 1) Fail-safe Fault (fail safe = 1) and (wake-up = 1) and (fault = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 0) (wake-up = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 1) Normal (fail-safe = 0) and (wakeup = 1) and (fault = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 0) (fail-safe = 1) and (wake-up = 1) and (fault = 0) Figure 12. Device operating modes 16XSD200 29 NXP Semiconductors 6.1.4 Sleep mode In Sleep mode, the channels and the SPI interface are turned off to minimize current consumption. The device enters Sleep mode (wake-up = 0) when both Direct Input pins IN(x) remain Off longer than tIN sec. (when reset is active; RSTB = 0). This is expressed as follows: • VPWR (and VDD) are within the normal range, and • wake-up = 0 (wake-up = RSTB or IN_ON[0] or IN_ON[1]) • and • fail-safe = X and • fault = X When employed, VDD must be kept in the normal range. Sleep mode is the default mode after the first application of the supply voltage (VPWR), prior to any I/O communication (RSTB and the internal states IN_ON[0:1] are still at logic [0]). All SPI register contents remain in their default state during sleep mode. 6.1.5 6.1.5.1 Fail-safe mode Entering Fail-safe mode Fail-safe mode is entered either upon loss of SPI communication or after loss of optional SPI supply voltage VDD (VDD out of range). The FSOB pin goes low and the channels are only controlled by the direct inputs (IN[0:1]). All protective functions remain fully operational. Previously latched faults are delatched and SPI register contents is reset (except bits POR & PARALLEL). The SPI registers can not be accessed. These conditions are also described by the following expressions: • VPWR is within the normal voltage range, and • wake-up = 1, fault = 0, and • fail-safe = 1 ((VDD Failure and VDD_FAIL_en=1 before) or (t(SPI)> tWDTO and WD_dis = 0). The last condition describes the loss of SPI communication which is detailed in the next section. 6.1.5.2 Watchdog on SPI communication and Fail-safe mode When VDD is present, the SPI watchdog timer is started upon a rising edge on the RSTB pin. Thereafter the device monitors the state of the first bit (WDIN) of all received SPI words. When the state of this bit is not alternated at least once within a data stream of duration tWDTO = 310 ms typ., the device considers that SPI communication has been lost and enters Fail-safe mode. This behavior can be disabled by setting the bit WD_DIS = 1. The value of watchdog timeout is derived from an internal oscillator. 6.1.5.3 Returning from Fail-safe to Normal mode To exit Fail-safe mode and return to normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device (regardless the register it is contained in and regardless the values of the other bits in this register). Next, a second data word must be received within the timeout period (tWDTO = 310 ms typ.) to be able to change any SPI register contents. Upon entering Normal mode, the FSOB pin returns to logic high and previously set faults and SPI registers are reset, except bits POR, PARALLEL and fault bits of latchable faults that had actually been latched. 6.1.6 Fault mode The device enters Fault mode when any of the following faults occurs in Normal or Fail-safe mode: • Overtemperature fault, (latchable fault) • Overcurrent fault, (latchable fault) • Severe short-circuit fault, (latchable fault) • Output shorted to VPWR in OFF state (default: disabled) • Openload fault in OFF state (default: disabled) • Openload fault in ON state (default: disabled) • External Clock Failure (default: enabled) • Overvoltage fault (enabled by default) • Undervoltage fault, (latchable fault) 16XSD200 NXP Semiconductors 30 The Fault Status pin (FSB) asserts a fault occurrence on any channel in real time (active low). Additionally, the assigned fault bit in the STATR_s or FAULTR_s register is set to one. Conversely to the FSB pin, a fault bit remains set until the corresponding register is read, even if the fault has disappeared. These bits can be read via the SO pin. Fault occurrence results in a turn-off of the incurred channel, except for the following faults: Openload (ON and OFF state), External Clock Failure and Output(s) shorted to VPWR. Under and overvoltage occurrences cause simultaneous turn-off of both channels. Details on the device’s behavior after the occurrence of one of the above faults can be found in Protection and Diagnostic Features. Fault mode (Operation and operating modes) is entered when: • VPWR (+VDD) were within the normal voltage range, and • wake-up = 1, and • fail-safe = X, and • fault = 1 (see Going from Normal to Fail-safe, Fault or Sleep mode) 6.1.6.1 Resetting FAULT bits Registers STATR_s and FAULTR_s contain global and channel-specific fault information. Reading the register the fault bit is contained in clears it, provided failure cause disappearance was detected and the fault wasn’t latched. 6.1.6.2 Entering Fault mode from Fail-safe mode When a Fault occurs in Fail-safe mode, the device is in Fault/Fail-safe mode and behaves according to the description of fault mode. However, SPI registers remain reset and can not be accessed. Only the Direct Inputs control the channels. 6.1.6.3 Returning from Fault mode to Fail-safe mode When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Fail-safe mode and behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset. 6.1.7 Latchable faults An auto-retry function (see Auto-retry) controls how the device responds to the so-called latchable faults. Latchable faults are: overcurrent (OC), severe short-circuit (SC), overtemperature (OT), and undervoltage (UV). If a latchable fault occurs, the channel is turned off, the FSB terminal goes low, and the assigned fault bit is set. These bits can not be reset before the next turn-on event is generated by auto-retry. Next, the channel automatically turns on at a programmable interval (provided auto-retry was enabled and the channel wasn’t latched). If the failure disappears prior to the expiration of the available amount of auto-retries, the FSB pin automatically returns to logic [1], but the fault bit remains set. It can then still be reset by reading the SPI register it is contained in. However, the fault actually gets latched if the failure cause hasn’t disappeared at the first turn-on event following expiration of the available amount of auto-retries (see Auto-retry). In that case, the channel gets latched and the FSB terminal remains low. The fault bit can not be reset by reading out the associated SPI register prior to performing a delatch sequence (Fault delatching). 6.1.7.1 Fault delatching To delatch a latched channel and be able to turn it on again, a delatch sequence must be executed after disappearance of the failure cause. Delatching resets the fault bit of latched faults (see Resetting FAULT bits). To reset the FSB pin, both channels must be delatched. Delatching is achieved either by alternating the state of the channels’ fault control signal fc[x] (generating a 1_0_1 sequence), or by resetting the auto-retry counter (provided retry is enabled). See Reset of the auto-retry counter. Delatching then actually occurs at the rising edge of the turn-on event. Signal fc[x] is an internal signal used by the device’s internal logic circuitry to control the diagnostic functions. The value of fc[x] depends on the state of the variables IN_ON[x], DIR_dis[x] and ON[x] and is expressed as follows: fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1) Alternating the fc[x] signal is achieved differently according to the way the user controls the device. • In direct-input controlled mode (DIR_dis_s = 0), the IN[x] pin must be set low, remain low for at least tIN seconds, and set high again (be switched On). This might happen automatically when operating at frequencies f fCLOCK(HIGH)), the external clock signal is ignored and a fault is detected (FSB =0), CLOCK_fail bit is set (OD2 in the DIAGR register). The state of the ON_s bit in the SPI register then determines the channel’s switching state. To return to external clock mode (and reset FSB), the clock-fail bit must be read and the external clock has to be within the authorized range again. 6.1.8.2 Internal clock and internal PWM (Clock_int_s bit = 1) By using a reference time slot (usually available from an external microcontroller), the period of each of the internal PWM clocks can be changed or calibrated (see Programmable PWM module). Calibration of the default period = 1/fPWM(0) reduces it maximum variation from about +/-30% to +/-10%. The programming procedure is initialized by sending a dedicated word to the SI-CALR register (see Table 7). Next, the device sets the new value of the switching period in 2 steps. First it measures the time elapsed between the first falling edge on the CSB pin and the next rising edge on the CSB pin (tCSB). Then it changes the value of the internal clock period accordingly. The actual value of the channel’s switching period is obtained by multiplying the internal clock period by 256. tCSB CSB SI SI command ignored tCSB CALR_s Internal clock period of channel s Figure 14. Internal clock calibration When the duration of the negative CSB pulse is outside a predefined time slot (from t CSB(MIN) to t CSB(MAX)), the calibration event is ignored and the internal clock frequency remains unchanged. If the value (fPWM(0)) has not been previously calibrated, it remains at its default level. 6.1.8.3 Synchronization of both channels When internal clock signals are used to drive the PWM modules, perfect synchronization over a long time can not be achieved since both clock signals are independent. However, when the channels are driven by an external clock, perfect synchronization can be achieved by simultaneously setting PWM_en_1=1 and PWM_en_0=1. The best way to optimize EMC is to use an external clock with a staggered switch on delay (see Table 8). 6.1.9 Parallel operation The channels can be paralleled to drive higher currents. Setting the PARALLEL bit in the GCR register to logic [1] is mandatory in this case. The improved synchronization of both transistors allows an equal current distribution between both channels. In parallel mode, both 16XSD200 33 NXP Semiconductors output pins (HS[x]) must be connected (as well as both IN[x] pins in case of external control). CONF0 and CONF1 must be set to equal values. 1- Device configuration in Parallel mode: There are two ways to configure the On/Off control: SPI-configured PWM control and Direct Input Control. • SPI configured Parallel mode: The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as PARALLEL=1, the contents of the corresponding registers in bank 1 are replaced by that of bank 0, except bits D6-D8 of the CONFR_1 register (configuration of the Openload/Output short-circuited diagnostics). After setting PARALLEL=1, contents of SO registers in bank 0 are copied to registers of bank 1 only when new information is written in them. Bits OD3, OD4 and OD5 of both FAULTR_s registers (OLON, OLOFF, OS) are always reported independently. • Direct Input controlled Parallel mode: The IN0 and IN1 pins must be connected externally. 2- Diagnostics in Parallel mode: The Diagnostics in Parallel mode operate as follows: • Openload in OFF state and - Openload in ON state: The OL_ON and OL_OFF bits of both FAULTR registers independently report failures of the channels according to the settings of bits D7 and D6 of the CONFR_s register. • Current sensing: Refer to the Table 23 for a description of the various current sensing modes. Only the Current sense ratio of bank 0 (D5 of the OCR_0 register) is considered. The corresponding bit in the OCR_1 register is copied from that of the OCR_0 register. • output shorted to supply: The OS-bit (OD3) of each of both FAULT registers independently report this fault, according to the settings of bit D8 of the CONFR_s reg. 3- Protections in Parallel mode: • Overcurrent: -Only the Configuration of overcurrent thresholds & blanking windows of channel 0 are considered. -In case overcurrent (OC) occurs on any channel, both channels are turned-off. Regardless the order of occurrence of OC, both OCbits (OD0) in the FAULT registers are simultaneously set to logic 1. • severe short-circuit: In case of SC detection on any channel, both channels are turned-off and the SC bits (OD1) in both FAULT registers are simultaneously set to logic 1. • overtemperature: In case of OT detection on any channel, both channels are turned-off and both OT bits in the FAULT registers (OD2) are simultaneously set to logic 1. • auto-retry: Only one 4-bit auto-retry counter specifies the number of successive turn-on events on paralleled channels (RETRYR_0). The counter value in register RETRYR_1 (OD4…OD7) is copied from that in RETRYR_0. To delatch the channels, only channel 0 needs to be delatched. 6.2 6.2.1 6.2.1.1 Protection and Diagnostic Features Protective Functions Overtemperature fault (Latchable fault) The channels have individual overtemperature detection. As soon as a channel’s junction temperature rises above TSD (175 °C typ.), it is turned OFF, the overtemperature bit (OT = OD2) is set, and FSB = 0. FSB can only be reset by turning ON the channel when the junction temperature of both channels has dropped below the threshold: TJ VPWR(OV)), the device turns OFF both channels simultaneously, the FSB pin is asserted low, and the OV fault bit is set to logic [1]. The channels remain OFF until the supply voltage drops below a threshold voltage VPWR < VPWR(OV) - VPWR(OVHYS). The OV bit can then be reset by reading out the STATR register. The overvoltage protection can be disabled by setting the OV_dis = 1 in the general configuration (GCR) register. In this case, the FSB pin neither asserts a fault occurrence, nor turns off the channels. However, the fault register (OV bit) still reports an overvoltage occurrence (when VPWR > VPWR(OV)) as a warning. When VPWR > VPWR(OV), the value of the on-resistance on both channels (RDS(ON)) still lays within the ranges specified in Table 4. 6.2.1.10 Undervoltage fault (Latchable fault) The channels are always turned off when the supply voltage (VPWR) drops below VPWR(UV). FSB drops to logic [0], and the fault register’s (common) UV bit is set to [1]. When the undervoltage condition then disappears, two different cases exist: • If the channel’s internal control signal hson[x] is off, FSB returns to logic [1], but the UV bit remains set until at least one output is turned on (warning). • If the channel’s control signal is on, the channel is turned on if a delatch or POR sequence is performed prior to the turn on request. The UV bit can then only be reset by reading out the STATR register. Auto-retry (if enabled) starts as soon as the UV condition disappears. 16XSD200 37 NXP Semiconductors 6.2.1.11 Extended mode protection In extended mode (6.0 V < VPWR < 8.0 V or 36 V < VPWR < 58 V), the channels are still fault protected, but compliance with the specified protection levels is not guaranteed. The register settings however (including previously detected faults) remain unaltered, provided VDD is within the authorized range. Below 6.0 V, the channels are only protected from overtemperature, and this fault is only reported in the SPI register the moment VPWR has again risen above VPWR(UV). To allow the outputs to remain ON between 36 V and 58 V, overvoltage detection should be disabled (by setting OV_dis = 1 in the GCR register). Faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if: • VDD < VDD(FAIL) with VPWR in the normal voltage range • VDD and VPWR are below the VSUPPLY(POR) voltage threshold • The corresponding SPI register is read after the disappearance of the failure cause (and delatching) 6.2.1.12 Drain/source overvoltage protection The device tries to limit the Drain-to-Source voltage by turning on the channel whenever VDS exceeds VDS(CLAMP). When a fault occurs (SC, OC, OT, UV), the device is rapidly switched Off (in t < tFAULT seconds), regardless the value of the selected slew rate. This may induce voltage surges on VPWR and/or the output pin (HS[x]) when connected to an inductive line/load. Turning on the device also dissipates the energy stored in the inductive supply line. This function monitors overvoltage for VPWR > 30 V. For supply voltages VPWR < 30 V, the device is protected from negative output voltages by automatically turning on the channel. The feature remains functional after device ground loss. 6.2.1.13 Supply overvoltage protection In order to protect the device from excessive voltages on the supply lines, the voltage between the device’s supply pins (VPWR and the GND) is monitored. When the VPWR-to-GND voltage exceeds the threshold VD_GND(CLAMP), the channel is automatically turned on. The feature is not operational in cases of ground loss. 6.2.1.14 Negative output voltage protection The device tries to limit the undervoltage on the output pins HS[x] when turning off inductive loads. When the output voltage drops below VCL, the channel is switched on automatically. This feature is not guaranteed after a device ground loss. The energy dissipation capabilities of the circuit are defined by the ECL [0:1] parameters. For inductive loads larger than 20 µH, it is recommended to employ a freewheeling diode. The three different overvoltage protection circuits are symbolically represented in Figure 17. The values of the clamping diodes are those specified in Table 4. Coupling factor k represents the current ratio between the current in the supply-voltage measurement-diode (zener) and the current injected into the MOSFET’s gate to turn it on. . VPWR K.Iz VDS(CLAMP)-Vth HS[x] DC Vth I2 VD_GND(Clamp) IMEG Load VCL-Vth GND Figure 17. Supply and output voltage protections 6.2.1.15 Reverse voltage protection on VPWR The device can withstand reverse supply voltages on VPWR down to -28 V. Under these conditions, the outputs are automatically turned On and the channel’s On-resistance (RDS(ON)) is similar to that during positive supply voltages. No additional components are 16XSD200 NXP Semiconductors 38 required to protect the VPWR circuit except series resistors (>8.0 k) between the direct inputs IN[0:1] and VPWR, in case they are connected to VPWR. The VDD pin needs reverse voltage protection from an externally connected diode (Figure 23). 6.2.1.16 Load and system ground loss In case of load ground loss, the channel’s state does not change, but the device detects an Openload fault. In case of a system GND loss, the channels are turned off. 6.2.1.17 Device ground loss In the (improbable) case the device loses all of its three ground connections (pins 14, 17, and 22), the channels’ state (ON/OFF), depends on several factors: the values of the series resistors connected to the device pins, the voltage of the direct input signals, the device’s momentary current consumption (influenced by the SPI settings) and the state of other high side switches on the board when there are pins in common like FSB, FSOB, and SYNC. In the following description, all voltages are referenced to the system (module) GND. When series resistors are used, the channel state can be controlled by entering Fail-safe mode. The channels are turned off automatically when the voltage applied to the IN[x] input(s) through the series resistor(s) is not higher than VDD and be turned on when the IN[x] input(s) are tied to VPWR. Fail-safe is entered under the following conditions: • all unused pins are tied to the overall system’s GND connection by resistors > 8.0 k • any device pin connected to external system components has a series resistors > 8.0 k (except pins Vpwr, VDD, HS[0], HS[1], and R(CSNS)>2.0 k) • the FSB, FSOB, and SYNC pins are in the logic high state when they are shared with other devices. This means that none of the other devices is in Fault or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, and CSNS. When the device GND voltage becomes logic low (V(GND)< VIL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high (V(GND)> VIH), SPI communication is lost and Fail-safe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH. 6.2.2 6.2.2.1 Supply voltages out of range VDD out of range If the external VDD supply voltage is lost (or falls outside the authorized range: VDD VPWR (POR), after a period VPWR < VPWR (POR) (and VDD < VDD (POR) before and after) • VDD > VDD (POR) after a period with VDD < VDD (POR) (VPWR < VPWR (POR) before and after) POR is also set at the transition to wake-up (by setting RSTB =1 or IN[x]=1) when VPWR > VPWR (POR) (before and after) or VDD >VDD(POR) (before and after). POR is not performed when VPWR > VPWR (POR) after a period VPWR < VPWR (POR) (and VDD > VDD (POR) permanently). (fc[x] = 0) (OpenLoadOFF = 1 or OS = 1 or OV = 1) OFF (fc[x] = 1 and (OV = 0)) (fc[x]= 0 or OV = 1) (fc[x] = 0) (OpenLoadOFF = 1 or OS = 1 or OV = 1) (OpenLoadON = 1) ON Latched OFF (Retry = 1) (count = 16) Auto-retry Loop (after Retry Period and OV = 0 and OT = 0 and UV = 0) OFF (OpenloadOFF = 1 or OS = 1 or OV = 1 or UV = 1 or OT = 1) (fc[x] = 0) (OV = 1) (OpenLoadON = 1) ON (Retry = 1) = > count = count+1 Figure 18. State machine: fault occurrence and auto-retry 6.2.3 Auto-retry The auto-retry circuitry automatically tries to turn on the channel on a cyclic basis. Only faults of the latchable type (overcurrent, severe short-circuit, overtemperature (OT), and undervoltage (UV)) may activate auto-retry. For UV and OT faults, auto-retry only starts after disappearance of the failure cause (when auto-retry is enabled). The retry condition is expressed by: Retry[x] = OC[x] or SC[x] or OT[x] or UV. If Auto-retry has been enabled, its mode of operation depends on the settings of the auto-retry related bits (bits D0...D3 of the SIRETRY_s register, see Table 12) and the available amount of auto-retries (bits OD7...OD4 of the SO-RETRY_s reg.). More details can be found in Amount of Auto-retries. If Auto-retry is disabled, latchable faults are immediately latched upon their occurrence (see Protection and Diagnostic Features). 6.2.3.1 Auto-retry configuration To enable the auto-retry function, bit retry_s (D0 of the SI RETRY_s register) has to be set to the appropriate value. Auto-retry is enabled for retry_s = 0 when the channel is configured for lighting applications (CONF=0). It is enabled for retry_s=1 for DC motor applications (CONF[x] =1). Table 10. Auto-retry activation for lamps (CONF=0) and DC motors (CONF=1) CONF[x] Retry_s bit auto-retry 0 0 enabled 0 1 disabled 16XSD200 NXP Semiconductors 40 Table 10. Auto-retry activation for lamps (CONF=0) and DC motors (CONF=1) CONF[x] Retry_s bit auto-retry 1 0 disabled 1 1 enabled If auto-retry is enabled, an auto-retry sequence starts when the channel’s fault control signal is set to 1 (fc[x] = 1, see Fault delatching) and the retry condition applies (Retry[x]=1, see Auto-retry). When a failure occurs (fault = 1), the channel automatically switches on again after the auto-retry period. The value of this period (tAUTO) is set through the SPI port (bits D2 and D3 of the RETRY_s register, see Table 22). When the failure cause disappears before expiration of the available amount of auto-retries, the device behaves normally (FSB = 1), but the retry counter keeps its current value and the fault bit remains set until it is cleared. This guarantees a maximum device availability without preventing fault detection. 6.2.3.2 Amount of Auto-retries In case the device is configured for an unlimited amount of auto-retries (Retry_unlimited_s = 1), auto-retry continues as long as the device remains powered. The channel never latches off. In case a limited amount of retries was selected (Retry-unlimited_s = 0), auto-retry continues as long as the value of the 4-bit auto-retry counter does not exceed 15 (bits OD4...OD7 of the RETRY_s register). After 15 retries, the Rfull bit of the STATR (OD4 for channel 0, OD5 for channel 1) register is set to a logic high. The amount of available auto-retries is then reduced to one. If the fault still hasn’t disappeared at the next retry, the corresponding channel is switched off definitively and the fault is latched (FSB = 0, see Protection and Diagnostic Features and Fault delatching). Any channel can be turned on at any moment during the auto-retry cycle by performing a delatch sequence. However, this does not reset the retry counter. The value of the auto-retry counter can be read back in Normal mode only (SO-RETRYR register bits OD7-OD4). 6.2.3.3 Reset of the auto-retry counter Any one of the below events reset the retry counter: Fail-safe is entered (Fail-safe mode) Sleep mode is left (Sleep mode) POR occurs (Supply voltages out of range) the retry function is set to unlimited (bit Retry-unlimited_s = 1 (D1 = 1)) the retry function is disabled (retry_s bit= D0 of the RETRY_s register under goes a 1-0 transition for CONF = 1 and a 0-1 transition for CONF = 0). If the channel is latched at the moment the auto-retry counter was reset (case 4), the channel is delatched, and turned on after one retry period (if retry was enabled). • • • • • Auto-retry and Overcurrent Duration During the on-period following an auto-retry, the load current profile is compared to the length and height of the selected overcurrent threshold profile, as described in the section on overcurrent protection (See Overcurrent fault (Latchable fault)). When the lighting profile is activated, the overcurrent duration counter is reset at each auto-retry (to allow sustaining new inrush currents). For DC motor mode however, it is only reset at the turn-off event of the first PWM period without any overcurrent (see Reset of the duration counter). Figure 18 gives a description of the retry state machine with the various transitions between operating modes. 6.2.4 Diagnostic features Diagnostic functions Openload-in-On state (OLON), Openload-in-Off-state (OLOFF) and output short-circuited to VPWR (OS) are operational over the frequency and duty cycle ranges specified in Table 5 for PWM mode, but the precise values also depend on the way the device is controlled (direct/internal PWM), on the current sense ratio and on the optional activation of the Openload-in-On-state detection. As an example, in direct input (DIR_dis_s = 0), Low-Current mode (CSR1), OLON, OLOFF and OS detection are performed for duty cycle values up to: RPWM_400_h = 85% (instead of 90%) when Openload in On state detection is enabled (OLON_dis=0). Occurrence of an OLON, OLOFF or OS fault sets the associated bit in the FAULTR_s register but does not trigger automatic turn-off. Any of these diagnostic functions can be disabled by setting OLON_dis_s=1, OLOFF_dis_s=1, or OS_dis_s=1 (bits D8...D6 of the CONFR reg.). 16XSD200 41 NXP Semiconductors The functions are guaranteed over the specified ranges for output capacitor values up to 22 nF (+/-20%). 6.2.4.1 Output shorted-to-VPWR fault The device detects short-circuits between the output and VPWR. The detection is performed during the OFF state. The output-shortedto-VPWR fault-bit (OS_s) is set whenever the output voltage rises above VOSD(THRES). The fault is reported in real time on the FSB pin and saved by the OS_s bit. Occurrence of this fault does not trigger automatic turn-off. Even if the short-circuit disappears, the OS_s bit is not cleared until the FAULTR register is read. The function may be disabled by setting OS_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic features. This type of event shall be limited to 1000 min. during its lifetime. In case of permanent output shorted to the power supply condition, it is needed to turn-on the corresponding channel. 6.2.4.2 Openload detection in OFF state Openload-in-OFF state detection (OL_OFF) is performed continuously during each OFF state (both for CSR0 and CSR1). This function is implemented by injecting a small current into the load (IOLD(OFF)). When the load is disconnected, the output voltage rises above VOLD(THRES). OL_OFF is then detected and the OL_OFF bit in the FAULTR register is set. If disappearance of the Openload fault is detected, the FSB output pin returns to a high immediately, but the OL_OFF bit in the fault register remains set until it is cleared by a read out of the FAULTR register. The function may be disabled by setting OLOFF_dis_s=1. The function operates over the duty cycle ranges specified in section Diagnostic features. 6.2.4.3 Openload detection in ON state (OL_ON) Openload in ON state detection (OLON) is performed continuously during the ON state for CSR0 over the ranges specified in section Diagnostic features. An Openload in ON state fault is detected when the load current is lower than the Openload current threshold IOLD(ON). This happens at IOLD(ON) = 150 mA (typ.) for high current sense mode (CSR0), and at 7.0 mA (typ.) for low current mode. FSB is asserted low and the OLON bit in the fault register is set to 1 but the channel remains On. FSB goes high as soon as disappearance of the failure cause is detected, but the OL_ON bit remains set. In high current mode (CSR0), Openload in ON state detection is done continuously during the ON state and the OLON-bit remains set even if the fault disappears. In high current mode, the OLON-bit is cleared when the FAULTR register is read during the OFF state, even if the fault has not disappeared. The OLON-bit is also cleared when the FAULTR register is read during the ON state, provided the failure cause (load disconnected) has disappeared. In low current mode (CSR1), OL_ON is done periodically instead of continuously and only operates when fast slew rate is selected. When the internal PWM module is used with an internal or external clock (case 1), the period is 150 ms (typ.). When the direct inputs are used (case 2), the period is that of the input signal. The detection instants in both cases are given by the following: 1. In internal PWM (int./ext. clock), low current mode (CSR1), Openload in ON state detection is not performed each switching period, but at a fixed frequency of about 7.0 Hz (each tOLLED =150 ms typ.). The function is available for a duty cycle of 100%. OLON detection is also performed at 7.0 Hz, at the first turn-off event occurring 150 ms after the previous OL_ON detection event (before OS and OL_OFF). 2. In direct input, low current mode (CSR1), OL_ON is performed each switching period (at the turn-off instant) but the duty cycle is restricted to the values. Consequently, when the signal on the IN[x] pin has a duty cycle of 100%, OL_ON is not performed. To solve this problem, either the internal PWM function must be activated with a duty cycle of 100%, or the channel’s direct input must be disabled by setting Dir_dis_s=1 (bit D5 of the CONFR-s register). The OLON-bit is only reset when the FAULTR register is read after occurrence of an OL_ON detection event without fault presence. 6.2.4.4 Openload detection in discontinuous conduction mode If small inductive loads (solenoids / DC motors) are driven at low frequencies, discontinuous conduction mode may occur. Undesired Openload in ON state errors may then be detected, as the inductor current needs some time to rise above the Openload detection threshold after turn-on. This problem can be solved by increasing the switching frequency or by disabling the function and activating Openload in OFF state detection instead. When small DC motors are driven in discontinuous conduction mode, undesired Openload in OFF state detection may also occur when the load current reaches 0.0 A during the OFF state. This problem can be solved by increasing the switching frequency or by enabling Openload in OFF state detection only during a limited time, preferably directly after turn-off (see Diagnostic features). The signal on the SYNC pin can be used to identify the turn-off instant. 16XSD200 NXP Semiconductors 42 6.2.5 Current and temperature sensing The scaled values of either of the output currents or the temperature of the device’s GND pin (#14) can be made available at the CSNS pin. To monitor the current of a particular channel or the general device temperature, the CSNS0_en and CSNS1_en bits (see Table 23) in the General Configuration Register (GCR) must be set to the appropriate values. When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high. 6.2.5.1 Instantaneous and sampled current sensing The device offers two possibilities for load current sensing: instantaneous (synchronous) sensing mode and track & hold mode (see Figure 9). In synchronous mode, the load current is mirrored through the current sense pin (Output current monitoring (CSNS)) and is therefore synchronous with it. After turn-off, the current sense pin does not output the channel current. In track & hold mode however, the current sense pin continues to mirror the load current as it was just before turn-off. Synchronous mode is activated by setting the T_H_en bit to 0, and Track & Hold mode by setting the T_H_en bit to 1. 6.2.5.2 Current sense ratio selection The load current is mirrored through the CSNS pin with a sense ratio (Figure 19) selected by the CSNS_ratio bit in the OCR register. To achieve optimal accuracy at low current levels, the lower current sensing ratio, called CSR1, must be selected. In that case, the overcurrent threshold levels are decreased. The best accuracy that can be obtained for either ratio is shown in Figure 20. The amount of current the CSNS pin can sink is limited to ICSNS,MAX..The CSNS pin must be connected to a pull-down resistor (470 Ω < R(CSNS)