MC33290DR2

Freescale Semiconductor Technical Data Document Number: MC33290 Rev 8.0, 8/2008 33290 The 33290 is a serial link bus interface device designed to provide bi-directional half-duplex communication interfacing in automotive diagnostic applications. It is designed to interface between the vehicle’s on-board microcontroller and systems off-board the vehicle via the special ISO K line. The 33290 is designed to meet the Diagnostic Systems ISO9141 specification. The device’s K line bus driver’s output is fully protected against bus shorts and overtemperature conditions. The 33290 derives its robustness to temperature and voltage extremes by being built on a SMARTMOS process, incorporating CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs. Although the 33290 was principally designed for automotive applications, it is suited for other serial communication applications. It is parametrically specified over an ambient temperature range of -40ºC ≤ TA ≤ 125ºC and 8.0 V ≤ VBB ≤ 18 V supply. The economical SO-8 surface-mount plastic package makes the 33290 very cost effective. ISO9141 PHYSICAL INTERFACE D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-PIN SOICN ORDERING INFORMATION Features • • • • • • • • • • • Device Operates Over Wide Supply Voltage of 8.0 to 18V Operating Temperature of -40 to 125°C MC33290D/R2 Interfaces Directly to Standard CMOS Microprocessors MCZ33290EF/R2 ISO K Line Pin Protected Against Shorts to Ground Thermal Shutdown with Hysteresis ISO K Line Pin Capable of High Currents ISO K Line Can Be Driven with up to 10 nF of Parasitic Capacitance 8.0 kV ESD Protection Attainable with Few Additional Components Standby Mode: No VBat Current Drain with VDD at 5.0 V Low Current Drain During Operation with VDD at 5.0 V Pb-Free Packaging Designated by Suffix Code EF Temperature Range (TA) Package -40 to 125°C 8-SOICN +VBAT VDD 33290 VDD VDD VBB CEN RX TX ISO MCU Dx SCIRx D SCITx D ISO K-Line GND Figure 1. 33290 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006-2008. All rights reserved. T xD R xD ARCHIVE INFORMATION ARCHIVE INFORMATION ISO K Line Serial Link Interface INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VBB 1 3.0 kΩ 50 V 20 V 200 Ω 10 V 10 V RX 6 ISO RHys Master Bias CEN 8 VDD 7 TX 5 40 V 125 kΩ Thermal Shutdown 125 kΩ GND 2.0 kΩ 10 V 3 10 V Figure 2. 33290 Simplified Block Diagram 33290 2 Analog Integrated Circuit Device Data Freescale Semiconductor ARCHIVE INFORMATION ARCHIVE INFORMATION 4 PIN CONNECTIONS PIN CONNECTIONS VBB 11 88 NC 22 77 VDD GND 33 66 RX ISO 44 55 TX CEN Figure 3. 33290 Pin Connections Pin Number Pin Name 1 VBB Battery power through external resistor and diode. Definition 2 NC Not to be connected. (1) 3 GND Common signal and power return. 4 ISO Bus connection. 5 TX Logic level input for data to be transmitted on the bus. 6 RX Logic output of data received on the bus. 7 VDD Logic power source input. 8 CEN Chip enable. Logic “1” for active state. Logic “0” for sleep state. ARCHIVE INFORMATION ARCHIVE INFORMATION Table 1. 33290 Pin Definitions Notes 1. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits. 33290 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings Rating Symbol Value Unit VDD -0.3 to 7.0 V VBB(LD) 45 V VISO 40 V IISO(LIM) 1.0 A Human Body Model (4) VESD1 ±2000 Machine Model (4) VESD2 ±200 ISO Clamp Energy (5) Eclamp 10 mJ Storage Temperature Tstg -55 to +150 °C Operating Case Temperature TC -40 to +125 °C Operating Junction Temperature TJ -40 to +150 °C Power Dissipation PD VDD DC Supply Voltage ARCHIVE INFORMATION VBB Load Dump Peak Voltage ISO Pin Load Dump Peak Voltage (2) ISO Short Circuit Current Limit ESD Voltage (3) V TA = 25°C Peak Package Reflow Temperature During Reflow Thermal Resistance Junction-to-Ambient W 0.8 (6) (7) , TPPRT Note 7. °C °C/W RθJA 150 Notes 2. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain within specified parametric limits during this duration. 3. ESD data available upon request. 4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 5. 6. 7. Nonrepetitive clamping capability at 25°C. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33290 4 Analog Integrated Circuit Device Data Freescale Semiconductor ARCHIVE INFORMATION All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER AND CONTROL IDD(SS) mA – Tx = 0.8 VDD, CEN = 0.3 VDD ARCHIVE INFORMATION VDD Quiescent Operating Current 0.1 IDD(Q) mA – Tx = 0.2 VDD, CEN = 0.7 VDD VBB Sleep State Current – – 1.0 IBB(SS) µA – VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD VBB Quiescent Operating Current – 50 IBB(Q) mA – TX = 0.2 VDD, CEN = 0.7 VDD – 1.0 Chip Enable V Input High-Voltage Threshold (8) VIH(CEN) 0.7 VDD – – Input Low-Voltage Threshold (9) VIL(CEN) – – 0.3 VDD Chip Enable Pull-Down Current (10) IPD(CEN) 2.0 – 40 – – 0.3 x VDD 0.7 x VDD – – -40 – -2.0 – – 0.2 VDD 0.8 VDD – – 150 170 – TX Input Low-Voltage Threshold VIL(Tx) TX Input High-Voltage Threshold VIH(Tx) (12) TX Pull-Up Current (13) IPU(Tx) RX Output Low-Voltage Threshold VOL(Rx) V VOH(Rx) RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA Thermal Shutdown (14) µA V RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA RX Output High-Voltage Threshold µA V RISO = 510 Ω (11) RISO = 510 Ω ARCHIVE INFORMATION VDD Sleep State Current V TLIM °C Notes 8. When IBB transitions to >100 µA. 9. When IBB transitions to