MC33399DR2

Freescale Semiconductor Technical Data Document Number: MC33399 Rev. 10.0, 4/2013 Local Interconnect Network (LIN) Physical Interface 33399 Local interconnect network (LIN) is a serial communication protocol designed to support automotive networks in conjunction with controller area network (CAN). As the lowest level of a hierarchical network, LIN enables cost-effective communication with sensors and actuators when all the features of CAN are not required. This device is powered by SMARTMOS technology. The 33399 is a physical layer component dedicated to automotive sub-bus applications. It offers communication speed from 1.0 kbps to 20 kbps, and up to 60 kbps for programming mode. It has two operating modes: Normal and Sleep. The 33399 supports LIN protocol specification 1.3. LIN PHYSICAL INTERFACE Features • Nominal operation from VSUP 7.0 to 18 V DC, functional up to 27 V DC battery voltage and capable of handling 40 V during load dump • Active bus waveshaping to minimize radiated emission • ± 5.0 kV ESD on LIN Bus Pin, ± 4.0 kV ESD on other pins • 30 k internal pull-up resistor • Ground shift operation and ground disconnection Fail-safe at module level • An unpowered node does not disturb the network • 20 µA in Sleep mode • Wake-up capability from LIN Bus, MCU command and dedicated high voltage wake-up input (interface to external switch) • Interface to MCU with CMOS compatible I/O pins • Control of external voltage regulator EF SUFFIX (PB-FREE) 98ASB42564B 8 PIN SOICN ORDERING INFORMATION Device (Add R2 Suffix for Tape and Reel) MC33399PEF Temperature Range (TA) Package - 40 to 125 °C 8 SOICN VPWR Regulator 12 V 5.0 V 33399 VSUP INH WAKE GND EN MCU TXD RXD Figure 1. 33399 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006-2013. All rights reserved. LIN LIN Bus INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VSUP WAKE INF Wake-up VREG Control EN VREF Bias 30 k Logic RXD Receiver LIN Protection TXD Driver GND Figure 2. 33399 Simplified Internal Block Diagram 33399 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS RXD 1 8 INH EN 2 7 VSUP WAKE 3 6 LIN TXD 4 5 GND Figure 3. 33399 8-SOICN Pin Connections Table 1. 8-SOICN Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. Pin Pin Name Formal Name Definition 1 RXD Data Output 2 EN Enable Control 3 WAKE Wake Input High voltage input used to wake up the device from the Sleep mode. 4 TXD Data Input MCU interface that controls the state of the LIN output. 5 GND Ground Device ground pin. 6 LIN LIN Bus Bidirectional pin that represents the single-wire bus transmitter and receiver. 7 VSUP Power Supply Device power supply pin. 8 INH Inhibit Output Controls an external switchable voltage regulator having an inhibit input. MCU interface that reports the state of the LIN bus voltage. Controls the operation mode of the interface. 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit ELECTRICAL RATINGS Power Supply Voltage VSUP Continuous Supply Voltage V 27 40 Transient Voltage (Load Dump) WAKE DC and Transient Voltage (Through a 33 k Serial Resistor) VWAKE - 18 to 40 V Logic Voltage (RXD, TXD, EN Pins) VLOG - 0.3 to 5.5 V LIN Pin VBUS DC Voltage V - 18 to 40 - 150 to 100 Transient (Coupled Through 1.0 nF Capacitor) INH Voltage / Current VINH DC Voltage ESD Voltage, Human Body Model (1) - 0.3 to VSUP + 0.3 V ESD1 V All Pins ± 4000 LIN Bus Pin with Respect to Ground ± 5000 ESD Voltage, Machine Model V ESD2 All Pins V V ± 200 THERMAL RATINGS Operating Temperature C Ambient TA - 40 to 125 Junction TJ - 40 to 150 TSTG - 55 to 150 C RJA 150 C/W TPPRT Note 3. °C Thermal Shutdown TSHUT 150 to 200 C Thermal Shutdown Hysteresis THYST 8.0 to 20 C Storage Temperature Thermal Resistance, Junction to Ambient Peak Package Reflow Temperature During Reflow (2) (3) , Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 220 pF, RZAP = 0 ). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33399 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 7.0 V  VSUP  18 V, -40C  TA  125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 7.0 13.5 18 V VLIN > VSUP - 0.5 V, VSUP < 14 V IS1 — 20 50 14 V VSUP < 18 V IS2 — — 150 IS(REC) — — 2.0 IS(DOM) — — 3.0 VSUP_UV 5.5 6.4 6.8 0.0 — 0.9 3.75 — 5.25 VSUP PIN (DEVICE POWER SUPPLY) Supply Voltage Range Supply Current in Sleep Mode A Supply Current in Normal Mode Recessive State Dominant State, Total Bus Load > 500  Supply Undervoltage Threshold mA V RXD OUTPUT PIN (LOGIC) Low-Level Output Voltage IIN 1.5 mA High-Level Output Voltage IOUT  VOL V VOH V TXD INPUT PIN (LOGIC) Low-Level Input Voltage VIL — — 1.5 V High-Level Input Voltage VIH 3.5 — — V VINHYST 100 550 800 mV - 50 — - 25 Input Voltage Threshold Hysteresis Pullup Current Source A IPU 1.0 V < VTXD < 4.0 V, VEN = 5.0 V EN INPUT PIN (LOGIC) Low-Level Input Voltage VIL — — 1.5 V High-Level Input Voltage VIH 3.5 — — V VINHYST 100 480 800 mV 5.0 20 30 — 20 40 — 20 — Input Voltage Threshold Hysteresis EN Low-Level Input Current High-Level Input Current 1.0 V < EN < 4.0 V A IIH VIN = 4.0 V Pulldown Current A IIL VIN = 1.0 V A IPD 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V  VSUP  18 V, -40C  TA  125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PIN (VOLTAGE EXPRESSED VERSUS VSUP VOLTAGE) Low Level Bus Voltage (Dominant State) VDOM TXD LOW, VLIN = 40 mA V 0.0 — 1.4 0.85 VSUP — — - 40 °C  TA  70 °C 20 30 47 70 °C < TA  125 °C 35 49 60 50 150 200 0.0 — 10 VSUP Disconnected, -18 V VLIN 18 V (Excluding Internal Pull-up Source) - 40 — 40 VSUP Disconnected, VLIN = -18 V (Including Internal Pull-up Source) — - 600 — VSUP Disconnected, VLIN = +18 V (Including Internal Pull-up Source) — 15 — 0 VSUP — 0.4 VSUP 0.6 VSUP — VSUP — VSUP/2 — 0.05 VSUP — 0.15 VSUP V LINWU 3.5 4.5 6.0 V High Level Voltage (Normal Mode) VWUH VSUP - 0.8 — VSUP V Leakage Current (Sleep Mode) I LEAK High Level Voltage (Recessive State) VREC TXD HIGH, IOUT = 1.0 A Internal Pullup Resistor to VSUP (4) RPU Current Limitation k I LIM TXD LOW, VLIN = VSUP Leakage Current to GND Recessive State, VSUP - 0.3 V VLIN VSUP V mA A I LEAK (4) LIN Receiver, Low Level Input Voltage V LINL TXD HIGH, RXD LOW LIN Receiver, High Level Input Voltage V LINH TXD HIGH, RXD HIGH LIN Receiver Threshold Center V V LINHYS VLINH - VLINL LIN Wake-up Threshold Voltage V V LINTH (VLINH - VLINL) / 2 LIN Receiver Input Voltage Hysteresis V V INH OUTPUT PIN 0 < VINH < VSUP A 0.0 — 5.0 HIGH-to-LOW Transition 0.3 VSUP 0.43 VSUP 0.55 VSUP LOW-to-HIGH Transition 0.4 VSUP 0.55 VSUP 0.65 VSUP 0.1 VSUP 0.16 VSUP 0.2 VSUP WAKE INPUT PIN Typical Wake-Up Threshold (EN = 0 V, 7.0 V  VSUP  18 V) (5) Wake-up Threshold Hysteresis WAKE Input Current VWUTH VWUHYS V V A I WU VWAKE  14 V — 1.0 5.0 VWAKE > 14 V — — 100 Notes 4. A diode structure is inserted with the pullup resistor to avoid parasitic current path from LIN to VSUP. 5. When VSUP is greater than 18 V, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 V. 33399 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V  VSUP  18 V, -40C  TA  125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Falling Edge t FALL 0.75 2.0 3.0 Rising Edge t RISE 0.75 2.0 3.0 t SYM - 2.0 — 2.0 Unit DIGITAL INTERFACE TIMING LIN Slew Rate (6) , (7) V/s LIN Rise/Fall Symmetry (t RISE - t FALL) Driver Propagation Delay (8) , (9) s s TXD LOW-to-LIN LOW t TXDLINL 0.0 — 4.0 TXD HIGH-to-LIN HIGH t TXDLINH 0.0 — 4.0 t RXDLINL 2.0 4.0 6.0 t RXDLINH 2.0 4.0 6.0 t RECSYM - 2.0 — 2.0 s Transmitter Propagation Delay Symmetry t TRSYM - 2.0 — 2.0 s (11) t PROPWL 45 70 130 Receiver Propagation Delay (9) , (10) LIN LOW to RXD LOW LIN HIGH to RXD HIGH Receiver Propagation Delay Symmetry Propagation Delay LIN Bus Wake-up to INH HIGH s s Notess 6. Measured between 20 and 80 percent of bus signal for 10 V 9.0 V. Below 9.0 V VSUP, a ground shift can reduce VSUP value below the minimum VSUP operation of 7.0 V. LIN BUS PIN (LIN) The LIN bus pin represents the single-wire bus transmitter and receiver. Transmitter Characteristics The LIN driver is a low side MOSFET with internal current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pullup components are required for the application in a slave node. An additional pull-up resistor of 1.0 k must be added when the device is used in the master node. Voltage can go from - 18 to 40 V without current other than the pull-up resistance. The LIN pin exhibits no reverse current from the LIN bus line to VSUP, even in the event of GND shift or VPWR disconnection. LIN thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant and the rise time from dominant to recessive are controlled to typically  2.0 V/µs. The symmetry between rise and fall time is also guaranteed. When going from dominant to recessive, the bus impedance parasitic capacitor must be charged up to VSUP. This charge-up is achieved by the total system pull-up current resistors. In order to guarantee that the rise time is within specification, maximum bus capacitance should not exceed 10 nF with bus total pull-up resistance less than 1.0 k. Receiver Characteristics The receiver thresholds are ratiometric with the device supply pin. Typical threshold is 50%, with a hysteresis between 5% and 10% of VSUP. DATA INPUT PIN (TXD) The TXD input pin is the MCU interface that controls the state of the LIN output. When TXD is LOW, LIN output is LOW; when TXD is HIGH, the LIN output transistor is turned OFF. This pin has an internal 5.0 V internal pull-up current source to set the bus in a recessive state in case the MCU is not able to control it; for instance, during system power-up/ power-down. During the Sleep mode, the pull-up current source is turned OFF. DATA OUTPUT PIN (RXD) The RXD output pin is the MCU interface that reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high level on RXD; LIN LOW (dominant) is reported by a low voltage on RXD. RXD output structure is a CMOS-type push-pull output stage. ENABLE INPUT PIN (EN) The EN pin controls the operation mode of the interface. If EN = logic [1], the interface is in normal mode, with the transmission path from TXD to LIN and from LIN to RXD both active. If EN = logic [0], the device is in Sleep mode or low power mode, and no transmission is possible. In Sleep mode, the LIN bus pin is held at VSUP through the bus pull-up resistors and pull-up current sources. The device can transmit only after being awakened. Refer to the INHIBIT OUTPUT PIN (INH) description on page 11. During Sleep mode, the device is still supplied from the battery voltage (through VSUP pin). Supply current is 20 µA typical. Setting the EN pin to LOW will turn the INH to highimpedance. The EN pin has an internal 20 µA pull-down current source to ensure the device is in Sleep mode if EN floats. 33399 10 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION INHIBIT OUTPUT PIN (INH) The INH pin controls an external switchable voltage regulator having an inhibit input. This pin is a high side switch structure to VSUP. When the device is in the Normal mode, the inhibit high side switch is turned ON and the external voltage regulator is activated. When the device is in Sleep mode, the inhibit switch is turned OFF and disables the voltage regulator (if this feature is used). A wake-up event on the LIN bus line will switch the INH pin to VSUP level. Wake-up output current capability is limited to 280 µA. INH can also drive an external MOSFET connected to an MCU IRQ or XIRQ input to generate an interrupt. See the typical application illustrated in Figure 13, page 15. WAKE INPUT PIN (WAKE) The WAKE pin is a high voltage input used to wake up the device from Sleep mode. WAKE is usually connected to an external switch in the application. The typical WAKE thresholds are VSUP / 2. The WAKE pin has a special design structure and allows wake-up from both HIGH-to-LOW or LOW-to-HIGH transitions. When entering the Sleep mode, the LIN monitors the state of the WAKE pin and stores it as a reference state. The opposite state of this reference state will be the wake-up event used by the device to re-enter Normal mode. An internal filter is implemented (50 s typical filtering time delay). The WAKE pin input structure exhibits a high impedance with extremely low input current when voltage at this pin is below 14 V. When voltage at the WAKE pin exceeds 14 V, input current starts to sink into the device. A series resistor should be inserted in order to limit the input current, mainly during transient pulses. Recommended resistor value is 33 k. Important The WAKE pin should not be left open. If the wake-up function is not used, WAKE should be connected to GND to avoid false wake-up. 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES As described below and depicted in Figure 10 and Table 5 on page 13, the 33399 has two operational modes, normal and sleep, and one transitional mode, Awake. NORMAL MODE • LIN bus activity • Internal node wake-up (EN pin) • Wake-up from WAKE pin Figures 7, 8, and 9 on page 9 show device application circuit and detail of wake-up operations. This is the normal transmitting and receiving mode. All features are available. Wake-up from LIN Bus (Awake Transitional Mode) SLEEP MODE In this mode the transmission path is disabled and the device is in low power mode. Supply current from VSUP is 20 µA typical. Wake-up can occur from LIN bus activity, as well as from node internal wake-up through the EN pin and the WAKE input pin. DEVICE POWER-UP (AWAKE TRANSITIONAL MODE) At system power-up (VSUP rises from zero), the 33399 automatically switches into the “Awake” mode (refer to Figure 10 below and Table 5 on page 13. It switches the INH pin in HIGH state to VSUP level. The microcontroller of the application then confirms the Normal mode by setting the EN pin HIGH. DEVICE WAKE-UP EVENTS The device can be awakened from Sleep mode by three wake-up events: A wake-up from the LIN pin switching from recessive to dominant state (switch from VSUP to GND) can occur. This is achieved by a node sending a wake-up frame on the bus. This condition internally wakes up the interface, which switches the INH pin to a HIGH level to enable the voltage regulator. The device switches into the Awake mode. The microcontroller and the complete application power up. The microcontroller must switch the EN pin to a HIGH level to allow the device to leave the Awake mode and turn it into Normal mode in order to allow communication on the bus. Wake-up from Internal Node Activity (Normal Mode) The application can internally wake-up. In this case, the microcontroller of the application sets the EN pin in the HIGH state. The device switches into Normal mode. Wake-up from WAKE Pin (Awake Transitional Mode) The application can wake up with the activation of an external switch. Refer to Table 1, 8-SOICN Pin Definitions on page 3. Power-Up/ Down VPWR < 7.0 V VPWR < 7.0 V VPWR > 7.0 V Sleep LIN Bus or WAKE Pin Wake-up Awake VPWR < 7.0 V Normal 1.0 to 20 kbps EN HIGH EN HIGH (Local Wake-up Event) EN LOW Note Refer to Table 5 for explanation. Figure 10. Operational and Transitional Modes State Diagram 33399 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES Table 5. Explanation of Operational and Transitional Modes State Diagram Operational/ Transitional LIN INH EN TXD RXD Sleep Mode Recessive state, driver off.  20 A pull-up current source. LOW LOW X High-impedance. Awake Recessive state, driver off.  HIGH LOW X LOW. Driver active. 30 k pullup active. HIGH HIGH Normal Mode LOW to drive LIN bus in dominant. HIGH to drive LIN bus in recessive. Report LIN bus level: • LOW LIN bus dominant • HIGH LIN bus recessive X = Don’t care. PROTECTION AND DIAGNOSIS FEATURES ELECTROSTATIC DISCHARGE (ESD) The 33399 has two Human Body Model ESD values. All pins can handle ± 4.0 kV. The LIN bus pin, with respect to ground, can handle ± 5.0 kV. ELECTROMAGNETIC COMPATIBILITY RADIATED EMISSION ON LIN BUS OUTPUT LINE Radiated emission level on the LIN bus output line is internally limited and reduced by active slew rate control of the output bus driver. Figure 11 shows the results in the frequency range 100 kHz to 2.0 MHz. ELECTROMAGNETIC IMMUNITY (EMI) On the LIN bus pin, the 33399 offers high EMI level from external disturbance occurring at the LIN bus pin in order to guarantee communication during external disturbance. On the WAKE input pin, an internal filter is implemented to reduce false wake-up during external disturbance. NOISE FILTERING Noise filtering is used to protect the electronic module against illegal wake-up spikes on the bus. Integrated receiver filters suppress any high-frequency (HF) noise induced into the bus wires. The cut-off frequency of these filters is a compromise between propagation delay and HF suppression. Figure 11. Radiated Emission in Normal Mode 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 13 TYPICAL APPLICATIONS TYPICAL APPLICATIONS The 33399 can be configured in several applications. Figures 12 and 13 show slave and master node applications. An additional pull-up resistor of 1.0 k in series with a diode must be added when the device is used in the master node. External Switch VPWR VREG Regulator INH 12 V VSUP 5.0 V Wake-up Regulator Control INH VDD I/O EN MCU M 33399 Actuator Driver VREF Bias 30 k LIN Bus 5.0 V WAKE Logic RXD Receiver LIN Protection SCI TXD Driver GND Figure 12. Slave Node Typical Application with WAKE Input Switch and INH (Switchable 5.0 V Regulator) 33399 14 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS External Switch VPWR Master Node Pullup Regulator 5.0 V 12 V WAKE 33399 1.0 k VSUP Wake-up Regulator Control INH 5.0 V M Actuator Driver VDD IRQ I/O I/O(2) MCU EN VREF Bias LIN Bus 5.0 V 30 k Logic RXD SCI Receiver LIN Protection TXD Driver GND Figure 13. Master Node Typical Device Application with MCU Wake-Up from Stop Mode (Non-Switchable 5.0 V Regulator, MCU Stop Mode) 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 15 REFERENCE DOCUMENTS REFERENCE DOCUMENTS Table 6. Reference Documents Title Local Interconnect Network (LIN) Physical Interface: Difference Between MC33399 and MC33661 LIterature Order Number EB215 33399 16 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98ASB42564B drawing number below. Dimensions shown are provided for reference ONLY. EF SUFFIX (Pb-FREE) 8-PIN SOIC NARROW BODY 98ASB42564B ISSUE U 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 17 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 7.0 7/2006 • • • • Implemented Revision History page Added Pb-Free suffix code EF Added EPP ordering part number MCZ33399EF/R2 Adjusted to the Freescale prevailing form and style 8.0 10/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from MAXIMUM RATINGS on page 4. Added note with instructions to obtain this information from www.freescale.com. 9.0 6/2012 • • • • Removed MC33399D from the ordering information. Removed D Suffix Updated orderable part number from MCZ33399EF to MC33399PEF. Updated Freescale form and style 10.0 4/2013 • • Change TSTG to -55 to 150 No other technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to first paragraph. 33399 18 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits on Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. 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Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Document Number: MC33399 Rev. 10.0 4/2013