Freescale Semiconductor
Advance Information
Document Number: MC33874
Rev. 9.0, 8/2008
Quad High Side Switch
(Quad 35mΩ)
33874
The 33874 is one in a family of devices designed for low-voltage
automotive and industrial lighting and motor control applications. Its
four low RDS(ON) MOSFETs (four 35mΩ) can control the high sides of
four separate resistive or inductive loads.
HIGH SIDE SWITCH
Programming, control, and diagnostics are accomplished using a
16-bit SPI interface. Additionally, each output has its own parallel input
for pulse-width modulation (PWM) control if desired. The 33874 allows
the user to program via the SPI the fault current trip levels and duration
of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can protect
wiring harnesses and circuit boards as well as loads.
The 33874 is packaged in a power-enhanced 12 x 12 nonleaded
Power QFN package with exposed tabs.
Features
• Quad 35mΩ high side switches (at 25°C)
• Operating voltage range of 6.0V to 27V with standby current <
5.0μA
• SPI control of over-current limit, over-current fault blanking time,
output OFF open load detection, output ON / OFF control,
watchdog timeout, slew rates, and fault status reporting
• SPI status reporting of over-current, open and shorted loads,
over-temperature, under-voltage and over-voltage shutdown,
fail-safe pin status, and program status
• Analog current feedback with selectable ratio
• Analog board temperature feedback
• Enhanced -16V reverse polarity VPWR protection
• Pb-free packaging designated by suffix code PNA
VDD
VDD
VPWR
PNA SUFFIX (PB_FREE)
98ART10510D
24-PIN PQFN (12 x 12)
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33874BPNA/R2
- 40°C to 125°C
24 PQFN
VDD
VPWR
33874
VDD
VPWR
HS0
WAKE
SO
SCLK
MCU
SI
CS
CS
SI
SO
I/O
RST
I/O
I/O
FS
IN0
I/O
IN1
I/O
IN2
I/O
IN3
A/D
GND A/D
LOAD 0
SCLK
CSNS
TEMP
FSI
HS1
LOAD 1
HS2
LOAD 2
HS3
LOAD 3
GND
Figure 1. 33874 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
VIC
Internal
Regulator
IUP
CS
SCLK
Over/Under-voltage
Protection
VIC
Selectable Slew
Rate Gate Drive
SPI
3.0MHz
IDWN
Selectable Over-current
High Detection
HS[0:3]: 55A or 40A
SO
SI
RST
WAKE
FS
IN0
Logic
IN1
IN2
Selectable Overcurrent Low Detection
Blanking Time
0.15ms–155ms
HS0
Selectable Overcurrent Low Detection
HS[0:3]: 2.8A–10A
Open Load
Detection
IN3
Over-temperature
Detection
RDWN
HS0
IDWN
HS1
Programmable
Watchdog
279ms–2250ms
HS1
VIC
HS2
HS2
FSI
HS3
HS3
TEMP
Temperature
Feedback
Selectable Output Current
Recopy (Analog MUX)
HS[0:3]: 1/7200 or 1/21400
GND
CSNS
Figure 2. 33874 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
RST
WAKE
FS
IN3
IN2
TEMP
IN1
IN0
CSNS
9
8
7
6
5
4
3
2
1
SI
SO
16
GND
17
HS3
18
SCLK
13 12 11 10
VDD
CS
Transparent Top View of Package
14
GND
24
FSI
23
GND
22
HS2
15
VPWR
19
20
21
HS1
NC
HS0
Figure 3. 33874 Pin Connections
Table 1. 33874 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin
Number
Pin Name
Pin
Function
1
CSNS
Output
Output Current
Monitoring
The Current Sense pin sources a current proportional to the designated
HS0 : HS3 output.
2
3
5
6
IN0
IN1
IN2
IN3
Input
Parallel Inputs
The IN0 : IN3 high side input pins are used to directly control HS0 : HS3 high
side output pins, respectively.
4
TEMP
Output
Temperature
Feedback
This pin reports an analog value proportional to the temperature of the GND
flag (pins 14, 17, 23). It is used by the MCU to monitor board temperature.
7
FS
Output
Fault Status
(Active Low)
This pin is an open drain configured output requiring an external pull-up
resistor to VDD for fault reporting.
8
WAKE
Input
Wake
This input pin controls the device mode and watchdog timeout feature if
enabled.
9
RST
Input
Reset
This input pin is used to initialize the device configuration and fault registers,
as well as place the device in a low-current Sleep Mode.
10
CS
Input
Chip Select
(Active Low)
This input pin is connected to a chip select output of a master microcontroller
(MCU).
11
SCLK
Input
Serial Clock
This input pin is connected to the MCU providing the required bit shift clock for
SPI communication.
12
SI
Input
Serial Input
This pin is a command data input pin connected to the SPI Serial Data Output
of the MCU or to the SO pin of the previous device of a daisy-chain of devices.
13
VDD
Power
Digital Drain Voltage
(Power)
This pin is an external voltage input pin used to supply power to the SPI circuit.
Formal Name
Definition
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33874 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin
Number
Pin Name
Pin
Function
Formal Name
14, 17, 23
GND
Ground
Ground
15
VPWR
Power
16
SO
Output
Serial Output
18
19
21
22
HS3
HS1
HS0
HS2
Output
High Side Outputs
Definition
These pins are the ground for the logic and analog circuitry of the device.
Positive Power Supply This pin connects to the positive power supply and is the source of operational
power for the device.
20
NC
N/A
No Connect
24
FSI
Input
Fail-safe Input
This output pin is connected to the SPI Serial Data Input pin of the MCU or to
the SI pin of the next device of a daisy-chain of devices.
Protected 35mΩ high side power output pins to the load.
This pin may not be connected.
The value of the resistance connected between this pin and ground
determines the state of the outputs after a watchdog timeout occurs.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Operating Voltage Range
VPWR(SS)
Steady-State
V
-16 to 41
VDD Supply Voltage
-0.3 to 5.5
V
See note (1)
- 0.3 to 7.0
V
VSO
- 0.3 to VDD + 0.3
V
WAKE Input Clamp Current
ICL(WAKE)
2.5
mA
CSNS Input Clamp Current
ICL(CSNS)
10
mA
Input / Output
VDD
Voltage(1)
SO Output Voltage(1)
HS [0:3] Voltage
VHS
V
Positive
41
Negative
-16
Current(2)
IHS[0:3]
11
A
Output Clamp Energy(3)
ECL [0:3]
85
mJ
VESD
± 2000
Output
ESD Voltage(4)
V
Human Body Model (HBM)
Charge Device Model (CDM)
Corner Pins (1, 13, 19, 21)
± 750
All Other Pins (2-12, 14-18, 20, 22-24)
± 500
THERMAL RATINGS
°C
Operating Temperature
Ambient
Junction
TA
- 40 to 125
TJ
- 40 to 150
TSTG
- 55 to 150
Junction to Case
RθJC
0.7 x VDD,
RST = VLOGIC HIGH
Sleep State Supply Current (VPWR = 14V, RST < 0.5V, WAKE < 0.5V)
mA
–
–
5.0
μA
IPWR(SLEEP)
TA = 25°C
–
1.0
TA = 85°C
–
–
50
4.5
5.0
5.5
No SPI Communication
–
–
1.0
3.0MHz SPI Communication(7)
–
–
5.0
VDD Supply Voltage
VDD(ON)
VDD Supply Current
IDD(ON)
10
V
mA
IDDSLEEP
–
–
5.0
μA
Over-voltage Shutdown Threshold
VOV
28
32
36
V
Over-voltage Shutdown Hysteresis
VOVHYS
0.2
0.8
1.5
V
VUV
4.75
5.25
5.75
V
Under-voltage Hysteresis
VUVHYS
–
0.25
–
V
Under-voltage Power-ON Reset
VUVPOR
–
–
4.75
V
VDD Sleep State Current
Under-voltage Shutdown Threshold(8)
(9)
Notes
7. Not guaranteed in production.
8. The under-voltage fault condition is reported to SPI register as long as the external VDD supply is within specification and the VPWR
voltage level does not go below the under-voltage Power-ON Reset threshold.
9. This applies when the under-voltage fault is not latched (IN = [0:3]).
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VPWR = 6.0V
–
–
55
VPWR = 10V
–
–
35
VPWR = 13V
–
–
35
VPWR = 6.0V
–
–
94
VPWR = 10V
–
–
60
VPWR = 13V
–
–
60
–
–
70
Unit
OUTPUTS (HS0, HS1, HS2, HS3)
Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 25°C)
Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 150°C)
Output Source-to-Drain ON
Resistance(10)
RDS(ON)
mΩ
RDS(ON)
mΩ
RSD(ON)
IHS = 1.0A, TA = 25°C, VPWR = -12V
mΩ
Output Overcurrent High Detection Levels (9.0V < VPWR < 16V)
A
SOCH = 0
IOCH0
44
55
66
SOCH = 1
IOCH1
32
40
48
Overcurrent Low Detection Levels (9.0V < VPWR < 16V)
A
SOCL[2:0] : 000
IOCL0
8.0
10
12
SOCL[2:0] : 001
IOCL1
7.1
8.9
10.7
SOCL[2:0] : 010
IOCL2
6.3
7.9
9.5
SOCL[2:0] : 011
IOCL3
5.6
7.0
8.5
SOCL[2:0] : 100
IOCL4
4.6
5.8
7.0
SOCL[2:0] : 101
IOCL5
3.8
4.8
5.8
SOCL[2:0] : 110
IOCL6
3.1
3.9
4.7
SOCL[2:0] : 111
IOCL7
2.2
2.8
3.4
Current Sense Ratio (9.0V < VPWR < 16V, CSNS < 4.5V)
–
DICR D2 = 0
CSR0
–
1/7200
–
DICR D2 = 1
CSR1
–
1/21400
–
Current Sense Ratio (CSR0) Accuracy
CSR0_ACC
%
Output Current
2.0A to 10A
-17
–
17
Notes
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS (HS0, HS1, HS2, HS3) (continued)
Current Sense Ratio (CSR1) Accuracy
CSR1_ACC
%
Output Current
10A to 20A
Current Sense Clamp Voltage
-19
–
19
4.5
6.0
7.0
30
–
100
2.0
3.0
4.0
- 20
–
-16
TSD
155
175
190
°C
TSD(HYS)
5.0
–
20
°C
VCL(CSNS)
CSNS Open; IHS[0:3] = 11A
Open Load Detection Current(11)
IOLDC
Output Fault Detection Threshold
VOFD(THRES)
Output Programmed OFF
Output Negative Clamp Voltage
Over-temperature Shutdown
Hysteresis(12)
μA
V
VCL
0.5A < IHS[0:3] < 2.0A, Output OFF
Over-temperature Shutdown(12)
V
V
Notes
11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of
an open load condition when the specific output is commanded OFF.
12. Guaranteed by process monitoring. Not production tested.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Logic High-voltage(13)
VIH
0.7 VDD
Input Logic Low-voltage(13)
VIL
–
–
–
V
–
0.2 VDD
V
CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI)
Input Logic Voltage
Hysteresis(14)
VIN(HYS)
100
850
1200
mV
Input Logic Pull-down Current (SCLK, SI, IN[0:3], VIN>0.2 x VDD)
IDWN
5.0
–
20
μA
RST Input Voltage Range
VRST
4.5
5.0
5.5
V
SO, FS Tri-State Capacitance(14)
CSO
–
–
20
pF
RDWN
100
200
400
kΩ
CIN
–
4.0
12
pF
7.0
–
14
Input Logic Pull-down Resistor (RST) and WAKE
Input Capacitance(15)
Wake Input Clamp
Voltage(16)
VCL(WAKE)
ICL(WAKE) < 2.5mA
Wake Input Forward Voltage
VF(WAKE)
ICL(WAKE) = -2.5mA
SO High-state Output Voltage
- 0.3
0.8 VDD
–
–
–
0.2
0.4
- 5.0
0
5.0
5.0
–
20
V
V
μA
μA
IUP
CS, VIN < 0.7 x VDD
FSI Input pin External Pull-down Resistance(18)
–
ISO(LEAK)
CS > 0.7 x VDD, 0 < VSO < VDD
Input Logic Pull-up Current(17)
- 2.0
VSOL
IOL = -1.6mA
SO Tri-state Leakage Current
V
VSOH
IOH = 1.0mA
FS, SO Low-state Output Voltage
V
RFS
FSI Disabled, HS[0:3] state according to direct inputs state and SPI
INx_SPI bits and A/O_s bit
kΩ
–
0
1.0
FSI Enabled, HS[0:3] OFF
6.0
6.5
7.0
FSI Enabled, HS0 ON, HS[1:3] OFF
15
17
19
FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
40
Infinite
–
3.8
3.9
4.0
-7.2
-7.5
-7.8
Temperature Feedback
TFEED
TA = 25°C
Temperature Feedback Derating
DTFEED
V
mV/°C
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST
signals may be supplied by a derived voltage referenced to VPWR.
14.
15.
16.
17.
18.
No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested.
Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
The current must be limited by a series resistance when using voltages > 7.0V.
Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the
resistance value will always be within the desired (specified) range.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (HS0, HS1, HS2, HS3)
Output Rising Slow Slew Rate A (DICR D3 = 0)(19)
SRRA_SLOW
9.0V < VPWR < 16V
Output Rising Slow Slew Rate B (DICR D3 = 0)(20)
DICR = 0
Output Turn-OFF Delay Time in Fast Slew Rate Mode(22)
3.0
0.025
0.3
1.0
0.1
0.3
0.75
0.015
0.05
0.15
0.5
1.5
3.0
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
0.025
0.3
1.0
2.0
30
200
1.0
6.0
100
40
200
800
μs
μs
t DLY_FAST(ON)
DICR = 1
Output Turn-OFF Delay Time in Slow Slew Rate Mode(22)
1.5
t DLY_SLOW(ON)
DICR = 0
Output Turn-ON Delay Time in Fast Slew Rate(21)
0.5
V/μs
SRFB_FAST
9.0V < VPWR < 16V
Output Turn-ON Delay Time in Slow Slew Rate(21)
0.15
SRFA_FAST
9.0V < VPWR < 16V
Output Falling Fast Slew Rate B (DICR D3 = 1)(20)
0.05
SRFB_SLOW
9.0V < VPWR < 16V
Output Falling Fast Slew Rate A (DICR D3 = 1)(19)
0.015
SRFA_SLOW
9.0V < VPWR < 16V
Output Falling Slow Slew Rate B (DICR D3 = 0)(20)
0.75
SRRB_FAST
9.0V < VPWR < 16V
Output Falling Slow Slew Rate A (DICR D3 = 0)(19)
0.3
SRRA_FAST
9.0V < VPWR < 16V
Output Rising Fast Slew Rate B (DICR D3 = 1)(20)
0.1
SRRB_SLOW
9.0V < VPWR < 16V
Output Rising Fast Slew Rate A (DICR D3 = 1)(19)
V/μs
t DLY_SLOW(OF
F)
μs
t DLY_FAST(OFF)
DICR = 1
μs
20
50
400
108
155
202
Over-current Low Detection Blanking Time
OCLT[1:0]: 00
OCLT[1:0]: 01(23)
OCLT[1:0]: 10
OCLT[1:0]: 11
ms
t OCL0
t OCL1
t OCL2
t OCL3
–
–
–
55
75
95
0.08
0.15
0.3
Notes
19. Rise and Fall Slew Rates A measured across a 5.0Ω resistive load at high side output = 0.5V to VPWR - 3.5V (see Figure 4, page 12).
These parameters are guaranteed by process monitoring.
20. Rise and Fall Slew Rates B measured across a 5.0Ω resistive load at high side output = 0.5V to VPWR - 3.5V (see Figure 4). These
parameters are guaranteed by process monitoring.
21. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output ON to VHS[0 : 3] = 0.5V with
RL = 5.0Ω resistive load.
22.
Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output OFF to VHS[0 : 3] = VPWR 0.5V with RL = 5.0Ω resistive load.
23.
This logical bit is not defined. Do not use.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued)
Over-current High Detection Blanking Time
CS to CSNS Valid Time(24)
Watchdog
tOCH
1.0
5.0
20
μs
t CNSVAL
–
–
10
μs
t WDTO0
t WDTO1
t WDTO2
t WDTO3
446
558
725
Timeout(25)
ms
WD[1:0] : 00
WD[1:0] : 01
WD[1:0] : 10
WD[1:0] : 11
223
279
363
1800
2250
2925
900
1125
1463
fPWM
-
300
-
Hz
f SPI
–
–
3.0
MHz
t WRST
–
50
350
ns
t CS
–
–
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
t ENBL
–
–
5.0
μs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(27)
t LEAD
–
50
167
ns
(27)
t WSCLKh
–
–
167
ns
Required Low-state Duration of SCLK (Required Setup Time)(27)
t WSCLKl
–
–
167
ns
Direct Input Switching Frequency (DICR D3 = 0)
SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO)
Maximum Frequency of SPI Operation
(26)
Required Low-state Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(27)
(27)
Required High-state Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)(28)
Falling Edge of SCLK to SI (Required Setup Time)
(28)
(27)
t LAG
–
50
167
ns
t SI (SU)
–
25
83
ns
t SI (HOLD)
–
25
83
ns
–
25
50
–
25
50
t RSO
SO Rise Time
CL = 200pF
ns
t FSO
SO Fall Time
CL = 200pF
ns
SI, CS, SCLK, Incoming Signal Rise Time(28)
t RSI
–
–
50
ns
SI, CS, SCLK, Incoming Signal Fall Time(28)
t FSI
–
–
50
ns
Low-impedance(29)
t SO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High-impedance(30)
t SO(DIS)
–
65
145
ns
–
65
105
Time from Falling Edge of CS to SO
Time from Rising Edge of SCLK to SO Data Valid
0.2 VDD ≤ SO ≤ 0.8 x VDD, CL = 200pF
(31)
t VALID
ns
Notes
24. Time necessary for the CSNS to be with ±5% of the targeted value.
25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t WDTO is consistent for all configured
watchdog timeouts.
26. RST low duration measured with outputs enabled and going to OFF or disabled condition.
27. Maximum setup time required for the 33874 is the minimum guaranteed time needed from the microcontroller.
28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
29. Time required for output status data to be available for use at SO. 1.0kΩ on pull-up on CS.
30. Time required for output status data to be terminated at SO. 1.0kΩ on pull-up on CS.
31. Time required to obtain valid data out from SO following the rise of SCLK.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
VPWR
V
PWR
VPWR - 0.5V
VPWR -0.5 V
SRFB_SLOW & SRFB_FAST
SRRB_SLOW & SRRB
VPWR
- 3V
-3.5
V
VPWR
SRFA_SLOW & SRFA_FAST
SRRA_SLOW & SRRA_FAST
t
0.5V
0.5 V
t DLY_SLOW(OFF) & t DLY_FAST(OFF)
tDLY(ON)
Figure 4. Output Slew Rate and Time Delays
IOCHx
Load
Current
t OCH
IOCLx
t OCLx
Time
Figure 5. Over-current Shutdown
33874
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
IOCH0
IOCH1
IOCL0
IOCL1
IOCL2
Load
Current
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
Time
t OCH
t OCL3
t OCL2
t OCL0
Figure 6. Over-current Low and High Detection
VIH
VIH
RSTB
RST
0.2
VDD
0.2
VDD
tWRST
TwRSTB
tENBL
VIL
VIL
tTCSB
CS
TENBL
VIH
VIH
0.7
VDD
0.7VDD
CS
CSB
0.2
VDD
0.7VDD
tTlead
LEAD
VIL
VIL
t RSI
t WSCLKh
TwSCLKh
TrSI
t LAG Tlag
0.70.7VDD
VDD
SCLK
SCLK
VIH
VIH
0.2 VDD
0.2VDD
t TSIsu
SI(SU)
VIL
VIL
t WSCLKl
TwSCLKl
t SI(HOLD)
TSI(hold)
SI
SI
0.7
0.7 V
VDD
DD
0.2VDD
0.2
VDD
Don’t Care
Valid
tTfSI
FSI
Don’t Care
Valid
Don’t Care
VIH
VIH
VIH
VIL
Figure 7. Input Timing Switching Characteristics
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
tFSI
tRSI
TrSI
TfSI
VOH
VOH
3.5 V
3.5V
50%
SCLK
SCLK
1.0VV
1.0
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
0.7 V
VDD
DD
0.20.2
VDD
VDD
Low-to-High
Low
to High
TrSO
t RSO
VOH
VOH
VOL
VOL
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
VDD
VDD
High to Low 0.70.7
High-to-Low
0.2VDD
0.2 VDD
TdlyHL
VOL
VOL
t SO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
33874
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33874 is one in a family of devices designed for lowvoltage automotive and industrial lighting and motor control
applications. Its four low RDS(ON) MOSFETs (35mΩ) can
control the high sides of four separate resistive or inductive
loads.
allows the user to program via the SPI the fault current trip
levels and duration of acceptable lamp inrush or motor stall
intervals. Such programmability allows tight control of fault
currents and can protect wiring harnesses and circuit boards
as well as loads.
Programming, control, and diagnostics are accomplished
using a 16-bit SPI interface. Additionally, each output has its
own parallel input for PWM control if desired. The 33874
The 33874 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
The Current Sense pin sources a current proportional to
the designated HS0 : HS3 output. That current is fed into a
ground-referenced resistor and its voltage is monitored by an
MCU's A/D. The output to be monitored is selected via the
SPI. This pin can be tri-stated through the SPI.
SERIAL INPUTS (IN0, IN1, IN2, IN3)
The IN0 : IN3 high side input pins are used to directly
control HS0 : HS3 high side output pins, respectively. A SPI
register determines if each input is activated or if the input
logic state is OR ed or AND ed with the SPI instruction. These
pins are to be driven with 5.0V CMOS levels, and they have
an active internal pull-down current source.
TEMPERATURE FEEDBACK (TEMP)
This pin reports an analog voltage value proportional to the
temperature of the GND. It is used by the MCU to monitor
board temperature.
FAULT STATUS (FS)
This pin is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. If a device
fault condition is detected, this pin is active LOW. Specific
device diagnostic faults are reported via the SPI SO pin.
WAKE
This input pin controls the device mode and watchdog
timeout feature if enabled. An internal clamp protects this pin
from high damaging voltages when the output is current
limited with an external resistor. This input has a passive
internal pull-down.
RESET (RST)
This input pin is used to initialize the device configuration
and fault registers, as well as place the device in a lowcurrent sleep mode. The pin also starts the watchdog timer
when transitioning from logic [0] to logic [1]. This pin should
not be allowed to be logic [1] until VDD is in regulation. This
pin has a passive internal pull-down.
CHIP SELECT (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33874 latches in
data from the Input Shift registers to the addressed registers
on the rising edge of CS. The device transfers status
information from the power output to the Shift register on the
falling edge of CS. The SO output driver is enabled when CS
is logic [0]. CS should transition from a logic [1] to a logic [0]
state only when SCLK is a logic [0]. CS has an active internal
pull-up, IUP.
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the
33874 device. The serial input (SI) pin accepts data into the
input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK pin be in a logic low state whenever CS
makes any transition. For this reason, it is recommended the
SCLK pin be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an active internal
pull-down. When CS is logic [1], signals at the SCLK and SI
pins are ignored and SO is tri-stated (high-impedance) (see
Figure 9, page 18).
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 to D0. The internal registers of the 33874 are configured
and controlled using a 5-bit addressing scheme described in
Table 8, page 22. Register addressing and configuration are
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
described in Table 9, page 22. The SI input has an active
internal pull-down, IDWN.
DIGITAL DRAIN VOLTAGE (VDD)
This pin is an external voltage input pin used to supply
power to the SPI circuit. In the event VDD is lost, an internal
supply provides power to a portion of the logic, ensuring
limited functionality of the device.
GROUND (GND)
This pin is the ground for the device.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the
source of operational power for the device. The VPWR contact
is the backside surface mount tab of the package.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
the CS pin is put into a logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes state on
the rising edge of SCLK and reads out on the falling edge of
SCLK. Fault and input status descriptions are provided in
Table 16, page 26.
HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2)
Protected 35mΩ high side power output pins to the load.
FAIL-SAFE INPUT (FSI)
The value of the resistance connected between this pin
and ground determines the state of the outputs after a
watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is
ON. If the FSI pin is left to float up to a logic [1] level, then the
outputs HS0 and HS2 will turn ON when in the Fail-safe state.
When the FSI pin is connected to GND, the watchdog circuit
and Fail-safe operation are disabled. This pin incorporates an
active internal pull-up current source.
33874
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33874 - Functional Block Diagram
Analog Control Circuitry
ANALOG CONTROL CIRCUITRY
The 33874 is designed to operate from 6.0V to 27V on the
VPWR Pin. The VPWR Pin supplies power to all internal
regulators, analog and logic circuit blocks. The VDD supply is
used for setting communication threshold levels and
supplying power to the SPI interface logic. This IC
architecture provides a very low standby current. The analog
circuitry provides for over-current and over-temperature
protection as well as temperature warning features.
MCU INTERFACE AND OUTPUT CONTROL
The device is designed with 4 inputs for PWM Output
driver control, if desired. MCU programming, control and
diagnostics are accomplished using the 16-bit SPI interface.
Several parallel control and status lines are provided.
HIGH–SIDE DRIVERS: HS0 – HS3
The 33874 provides high side load drive capability for 4
outputs. The RDSON for the output MOSFETs is 35mΩ. The
outputs are protected for over-current and over-temperature.
The MOSFET gate drive can be slew rate controlled using the
SPI interface. There is also an open load detection feature. A
ratioed value of the MOSFET output current is available to
the MCU.
The device allows for control of the 4 outputs through the
SPI interface or by use of the parallel inputs, which allows for
PWM capability.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
SPI PROTOCOL DESCRIPTION
The SI / SO pins of the 33874 follow a first-in first-out (D15
to D0) protocol, with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0V CMOS logic levels.
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),
and Chip Select (CS).
CSB
CS
CS
SCLK
SI
D15
SO
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
D8
OD8
D7
D6
OD7
OD6
D5
OD5
D4
D3
OD4
OD3
D2
OD2
D1
D0
OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
D15is: D0
to the
most
ordered entry of data into the device.
NOTES: 1. 2.RSTB
in arelate
logic H state
during
therecent
above operation.
OD15
: OD0
relate
thetofirst
16 bits
ofordered
ordered
fault
and status
data
out IC
of the device.
device.
2. 3.DO,
D1, D2,
... , and
D15to
relate
the most
recent
entry
of program
data into
the LUX
Figure 9. Single 16-Bit Word SPI Communication
OPERATIONAL MODES
The 33874 has four operating modes: Sleep, Normal,
Fault, and Fail-safe. Table 5 summarizes details contained in
succeeding paragraphs.
Table 5. Fail-Safe Operation and Transitions to Other
33874 Modes
FS
Sleep
x
0
0
x
Device is in Sleep mode. All
outputs are OFF
Normal
1
x
1
No
Normal mode. Watchdog is
active if enabled.
Fault
0
1
1
No
0
1
0
NORMAL MODE
0
0
1
Device is currently in fault
mode. The faulted output(s)
is (are) OFF.
1
0
1
1
1
1
1
1
0
Watchdog has timed out and
the device is in Fail-safe
Mode. The outputs are as
configured with the RFS
resistor connected to FSI.
RST and WAKE must go
from logic [1] to logic [0]
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied the
FSI pin to ground.
FAIL-SAFE MODE
x = Don’t care.
Yes
Comments
The Default mode of the 33874 is the Sleep Mode. This is
the state of the device after first applying battery voltage
(VPWR) prior to any I/O transitions. This is also the state of the
device when the WAKE and RST are both logic [0]. In the
Sleep Mode, the output and all unused internal circuitry, such
as the internal 5.0V regulator, are off to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to logic [0]. The 33874 will transition to the
Normal or Fail-safe operating modes based on the WAKE
and RST inputs as defined in Table 5.
Mode
FailSafe
Wake RST WDTO
SLEEP MODE
The 33874 is in Normal Mode when:
• VPWR and VDD are within the normal voltage range.
• RST pin is logic [1].
• No fault has occurred.
FAIL-SAFE MODE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input pin
transitions from logic [0] to logic [1]. The WAKE input is
capable of being pulled up to VPWR with a series of limiting
33874
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
resistance limiting the internal clamp current according to the
specification.
Table 5 summarizes the various methods for resetting the
device from the latched Fail-safe Mode.
The Watchdog timeout is a multiple of an internal oscillator
and is specified in the Table 15, page 24. As long as the WD
bit (D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), based on the
programmed value of the WDR, the device will operate
normally. If an internal watchdog timeout occurs before the
WD bit, the device will revert to a Fail-safe mode until the
device is reinitialized.
If the FSI pin is tied to GND, the Watchdog fail-safe
operation is disabled.
During the Fail-safe Mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 6).
Table 6. Output State During Fail-safe Mode
RFS (kΩ)
High Side State
0 (shorted to ground)
Fail-safe Mode Disabled
6.0
All HS OFF
15
HS0 ON
HS1 : HS3 OFF
30 (open)
HS0 and HS2 ON
HS1 and HS3 OFF
In the Fail-safe Mode, the SPI register content is retained
except for over-current high and low detection levels, timing
and latched over-temperature which are reset to their default
value (SOCL, SOCH, and OCTL and OT_latch_[0:3] bits).
Then the watchdog, over-voltage, over-temperature, and
over-current circuitry (with default value) are fully operational.
The Fail-safe Mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in Fail-safe Mode. The device can be brought out of
the Fail-safe Mode by transitioning the WAKE and RST pins
from logic [1] to logic [0] or forcing the FSI pin to logic [0].
LOSS OF VDD
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The outputs
can still be driven by the direct inputs IN0 : IN3. The 33874
uses the battery input to power the output MOSFET-related
current sense circuitry and any other internal logic providing
fail-safe device operation with no VDD supplied. In this state,
the watchdog, under-voltage, over-voltage, over-temperature
(latched) and over-current circuitry are fully operational with
default values.
FAULT MODE
This 33874 indicates the faults below as they occur by
driving the FS pin to logic [0]:
•
•
•
•
Over-temperature fault
Over-voltage and under-voltage fault
Open load fault
Over-current fault (high and low)
The FS pin will automatically return to logic [1] when the
fault condition is removed, except for overcurrent,
overtemperature (in case of latching configuration) and in
some cases of undervoltage.
The FS pin reports all faults. For latched faults, this pin is
reset by a new Switch ON command (via the SPI or direct
input IN).
Fault information is retained in the fault register and is
available (and reset) via the SO pin during the first valid SPI
communication (refer to Table 17, page 26).
PROTECTION AND DIAGNOSTIC FEATURES
OVER-TEMPERATURE FAULT (LATCHING OR
NON-LATCHING)
• in Fail-safe Mode: the FSI input must be grounded and
then set to its nominal voltage to switch ON the outputs.
The 33874 incorporates over-temperature detection and
shutdown circuitry for each output structure.
The over-temperature fault (one for each output) is
reported by SPI. If the over-temperature is latched, the SPI
reports OTF_s = [1] and OCLF_s = [1]. In case of nonlatched, OTF_s = [1] only is reported.
The over-temperature is latched per default and can be
unlatched through SPI with OT_latch_[0:3] bits.
An over-temperature fault condition results in turning OFF
the corresponding output. To remove the fault and be able to
turn ON again the outputs, the failure must be removed and:
• in Normal Mode: the corresponding output must be
commanded OFF and ON again in case of overtemperature latched (OT_latch bit = 0).
• in Normal Mode: the corresponding output turns ON
automatically if the temperature is below TSD-TSD(HYS) in
case of unlatched over-temperature (OT_latch bit = 1).
The fault bits will be cleared in the status register after either
a valid SPI read command or a power on reset of the device.
OVERCURRENT FAULT (LATCHING)
The 33874 has eight programmable over-current low
detection levels (IOCL) and two programmable over-current
high detection levels (IOCH) for maximum device protection.
The two selectable, simultaneously active over-current
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
detection levels, defined by IOCH and IOCL, are illustrated in
Figure 6, page 13. The eight different over-current low detect
levels (IOCL0 : IOCL7) are illustrated in Figure 6.
If the load current level ever reaches the selected overcurrent low detection level and the over-current condition
exceeds the programmed over-current time period (tOCx), the
device will latch the output OFF.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected tOCH driver.
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
OVER-VOLTAGE FAULT (NON-LATCHING)
The 33874 shuts down the output during an over-voltage
fault (OVF) condition on the VPWR pin. The output remains
in the OFF state until the over-voltage condition is removed.
When experiencing this fault, the OVF fault bit is set in the bit
D1 and cleared after either a valid SPI read or a power reset
of the device.
The over-voltage protection can be disabled through SPI
(bit OV_DIS). When disabled, the returned SO bit OD13 still
reflects any over-voltage condition (over-voltage warning).
UNDER-VOLTAGE SHUTDOWN (LATCHING OR
NON-LATCHING)
The output(s) will latch off at some battery voltage below
6.0 V. As long as the VDD level stays within the normal
specified range, the internal logic states within the device will
be sustained.
In the case where battery voltage drops below the undervoltage threshold (VPWRUV) output will turn off, FS will go to
logic 0, and the fault register UVF bit will be set to 1.
Two cases need to be considered when the battery level
recovers :
• If outputs command are low, FS will go to logic 1 but the
UVF bit will remain set to 1 until the next read operation
(warning report).
• If the output command is ON, then FS will remain at
logic 0. The output must be turned OFF and ON again
to re-enable the state of output and release FS. The
UVF bit will remain set to 1 until the next read operation.
The under-voltage protection can be disabled through SPI
(bit UV_dis = 1). In this case, the FS does not report any
under-voltage fault condition, UVF bit is set to 1, and the
output state is not changed as long as the battery voltage
does not drop any lower than 2.5 V.
The daisy chain feature is available under VDD in nominal
conditions.
33874
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Table 7. Device behavior in case of Under-voltage
Quad High Side
Switch
(VPWR Battery
Voltage) ∗∗
VPWR > VPWRUV
VPWRUV > VPWR
> UVPOR
UVPOR > VPWR >
2.5V ∗
State
Output State
UV Enable
UV Enable
UV Enable
UV Enable
IN[0:3] = 0
IN[0:3] = 0
IN_x*** = 1
IN_x*** = 1
(Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR)
UV Disable
UV Disable
IN[0:3] = 0
IN_x*** = 1
(Falling or
(Falling or
Rising VPWR) Rising VPWR)
OFF
OFF
ON
OFF
OFF
ON
FS State
1
1
1
0
1
1
SPI Fault Register
UVF Bit
0
1 until next read
0
1
0 (falling)
1 until next
read (rising)
0 (falling)
1 until next
read (rising)
OFF
OFF
OFF
OFF
OFF
ON
FS State
0
0
0
0
1
1
SPI Fault Register
UVF Bit
1
1
1
1
1
1
OFF
OFF
OFF
OFF
OFF
ON
1
1
1
1
1
1
Output State
Output State
FS State
SPI Fault Register 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read
UVF Bit
2.5V > VPWR > 0V
Output State
FS State
OFF
OFF
OFF
OFF
OFF
OFF
1
1
1
1
1
1
SPI Fault Register 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read
UVF Bit
Comments
UV fault is
not latched
UV fault is
not latched
UV fault
is latched
∗ = Typical value; not guaranteed
∗∗ = While VDD remains within specified range.
*** = IN_x is equivalent to IN_x direct input or IN_spi_s SPI input.
OPEN LOAD FAULT (NON-LATCHING)
The 33874 incorporates open load detection circuitry on
the output. Output open load fault (OLF) is detected and
reported as a fault condition when the output is disabled
(OFF). The open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OLF fault bit is set in the
status register. If the open load fault is removed, the status
register will be cleared after reading the register.
The open load protection can be disabled through SPI
(bit OL_DIS). It is recommended to disable open load
circuitry in case of a permanent disconnected load.
REVERSE BATTERY
The output survives the application of reverse voltage as
low as -16V. Under these conditions, the output’s gate is
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are
required except on VDD.
GROUND DISCONNECT PROTECTION
In the event the 33874 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the state of the output at the time of
disconnection. A 10KΩ resistor needs to be added between
the wake pin and the rest of the circuitry in order to ensure
that the device turns off in case of ground disconnect and to
prevent this pin to exceed its maximum ratings.
Current limit resistors in the digital input lines protect the
digital supply against excessive current (10kΩ typical).
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
D4 : D0, are used to configure and control the outputs and
their protection features.
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 (Table 8).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit. In some cases, output selection is
done with bits D12 : D11. The next three bits, D10 : D8, are
used to select the command register. The remaining five bits,
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 33874 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 9, page 22, summarizes the SI registers.
Table 8. SI Message Bit Assignment
Bit Sig
SI Msg Bit
MSB
D15
Message Bit Description
Watchdog in: toggled to satisfy watchdog requirements.
D14 : D15
Not used.
D12 : D11
Register address bits used in some cases for output selection.
D10 : D8
Register address bits.
D7 : D5
Not used.
D4 : D1
Used to configure the inputs, outputs, and the device protection features and SO status content.
D0
Used to configure the inputs, outputs, and the device protection features and SO status content.
LSB
Table 9. Serial Input Address and Configuration Bit Map
SI Data
SI Register
D15
D14 D13 D12 D11 D10 D9
D8 D7 D6 D5
D4
D3
D2
D1
D0
STATR_s
WDIN
0
0
0
0
0
0
0
0
0
0
SOA4
SOA3
SOA2
SOA1
SOA0
OCR0
WDIN
0
0
0
0
0
0
1
0
0
0
0
IN3_SPI
IN2_SPI
IN1_SPI
IN0_SPI
OCR1
WDIN
0
0
0
1
0
0
1
0
0
0
0
CSNS3 EN
CSNS2 EN
CSNS1 EN
CSNS0 EN
SOCHLR_s WDIN
0
0
A1
A0
0
1
0
0
0
0
0
SOCH_s
SOCL2_s
SOCL1_s
SOCL0_s
CDTOLR_s WDIN
0
0
A1
A0
0
1
1
0
0
0
0
OL_DIS_s
OCL_DIS_s
OCLT1_s
OCLT0_s
DICR_s
WDIN
0
0
A1
A0
1
0
0
0
0
0
0
FAST_SR_s
CSNS_high_s DIR_DIS_s
A/O_s
UOVR
WDIN
0
0
0
0
1
0
1
0
0
0
0
OT_latch-1
OT_latch_0
UV_DIS
OV_DIS
WDR
WDIN
0
0
0
1
1
0
1
0
0
0
0
OT_latch_3
OT_latch_2
WD1
WD0
NAR
WDIN
0
0
0
0
1
1
0
0
0
0
0
RESET
0
0
0
X
X
X
X
X
0
0
0
0
No Action (Allow Toggling of D15- WDIN)
0
0
0
0
x = Don’t care.
s = Output selection with the bits A1A0 as defined in Table 10.
D15 is used to toggle watchdog event (WDIN)
DEVICE REGISTER ADDRESSING
ADDRESS 00000 — STATUS REGISTER (STATR_S)
The following section describes the possible register
addresses and their impact on device operation.
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the OCR0, OCR1, SOCHLR,
33874
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to
the section entitled Serial Output Communication (Device
Status Return Data) beginning on page 24.)
ADDRESS 00001— OUTPUT CONTROL REGISTER
(OCR0)
The OCR0 register allows the MCU to control the ON / OFF
state of four outputs through the SPI. Incoming message bit
D3 : D0 reflects the desired states of the four high side outputs
(INx_SPI), respectively. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF.
ADDRESS 01001— OUTPUT CONTROL REGISTER
(OCR1)
Incoming message bits D3 : D0 reflect the desired output
that will be mirrored on the Current Sense (CSNS) pin. A
logic [1] on message bits D3 : D0 enables the CSNS pin for
outputs HS3 : HS0, respectively. In the event the current
sense is enabled for multiple outputs, the current will be
summed. In the event that bits D3 : D0 are all logic [0], the
output CSNS will be tri-stated. This is useful when several
CSNS pins of several devices share the same A /D converter.
ADDRESS A1A0010 — SELECT OVER-CURRENT
HIGH AND LOW REGISTER (SOCHLR_S)
The SOCHLR_s register allows the MCU to configure the
output over-current low and high detection levels,
respectively. Each output “s” is independently selected for
configuration based on the state of the D12 : D11 bits
(Table 10).
Table 10. Output Selection
A1 (D12)
A0 (D11)
HS_s
0
0
HS0
0
1
HS1
1
0
HS2
1
1
HS3
Each output can be configured to different levels. In
addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements matching system characteristics. Bits D2 : D0
set the over-current low detection level to one of eight
possible levels, as shown in Table 11, page 23. Bit D3 sets
the over-current high detection level to one of two levels, as
outlined in Table 12, page 23.
Table 11. Over-current Low Detection Levels
SOCL2_s* SOCL1_s* SOCL0_s*
(D2)
(D1)
(D0)
Over-current Low
Detection (Amperes)
HS0 to HS3
0
0
0
10
0
0
1
8.9
0
1
0
7.9
0
1
1
7.0
1
0
0
5.8
1
0
1
4.8
1
1
0
3.9
1
1
1
2.8
* “_s” refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 23.
Table 12. Over-current High Detection Levels
SOCH_s* (D3)
Over-current High Detection (Amperes)
HS0 to HS3
0
55
1
40
* “_s” refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 23.
ADDRESS A1A0011 — CURRENT DETECTION TIME
AND OPEN LOAD REGISTER (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an over-current low
condition before an output latches OFF. Each output is
independently selected for configuration based on A1A0 ,
which are the state of the D12 : D11 bits (refer to Table 10,
page 23).
Bits D1 : D0 (OCLT1_s : OCLT0_s) allow the MCU to select
one of three over-current fault blanking times defined in
Table 13. Note that these timeouts apply only to the overcurrent low detection levels. If the selected over-current high
level is reached, the device will latch off within 20μs.
Table 13. Over-current Low Detection Blanking Time
OCLT[1:0]_s*
Timing
00
155ms
01
Do not use
10
75ms
11
150μs
* “_s” refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 23.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent low detection feature. When disabled, there is no
timeout for the selected output and the over-current low
detection feature is disabled.
A logic [1] on bit D3 (OL_DIS_s) disables the open load
(OL) detection feature for the output corresponding to the
state of bits D12 : D11.
ADDRESS A1A0100 — DIRECT INPUT CONTROL
REGISTER (DICR)
The DICR register is used by the MCU to enable, disable,
or configure the direct IN pin control of each output. Each
output is independently selected for configuration based on
the state bits D12 : D11 (refer to Table 10, page 23).
For the selected output, a logic [0] on bit D1 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D1
will disable the output from direct control.
While addressing this register, if the Input was enabled for
direct control, a logic [1] for the D0 (A/O_s) bit will result in a
Boolean AND of the IN pin with its corresponding IN_SPI
D[4:0] message bit when addressing OCR0. Similarly, a logic
[0] on the D0 pin results in a Boolean OR of the IN pin to the
corresponding message bits when addressing the OCR0.
This register is especially useful if several loads are required
to be independently PWM controlled. For example, the IN
pins of several devices can be configured to operate all of the
outputs with one PWM output from the MCU. If each output
is then configured to be Boolean ANDed to its respective IN
pin, each output can be individually turned OFF by SPI while
controlling all of the outputs, commanded on with the single
PWM output.
A logic [1] on bit D2 (CSNS_high_s) is used to select the
high ratio on the CSNS pin for the selected output. The
default value [0] is used to select the low ratio (Table 14).
ADDRESS 00101 — UNDER-VOLTAGE / OVERVOLTAGE AND HS[0,1] OVER-TEMPERATURE
REGISTER (UOVR)
The UOVR register disables the under-voltage (D1) and/or
over-voltage (D0) protection. When these two bits are [0], the
under and over-voltages are active (default value).
The UOVR register allows the over-temperature detection
latching on the HS0 and HS1. To latch the over-temperature,
the bits (OT_latch_1 and OT_latch_0) must be set to [0]
which is the default value. To disable the latching, both bits
must be set to [1].
ADDRESS 01101 — WATCHDOG AND HS[2,3]
OVER-TEMPERATURE REGISTER (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. The watchdog timeout is configured using
bits D1 and D0. When D1 and D0 bits are programmed for
the desired watchdog timeout period (Table 15), the WDSPI
bit should be toggled as well, ensuring the new timeout period
is programmed at the beginning of a new count sequence.
The WDR register allows the over-temperature detection
latching on the HS2 and HS3. To latch the over-temperature,
the bits (OT_latch_3 and OT_latch_2) must be set to [0]
which is the default value. To disable the latching, both bits
must be set to [1].
Table 15. Watchdog Timeout
WD[1:0] (D1, D0)
Timing (ms)
00
558
01
279
10
2250
11
1125
Table 14. Current Sense Ratio
CSNS_high_s* (D2)
Current Sense Ratio
HS0 to HS3
0
1/7200
1
1/21400
* “_s” refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 23.
A logic [1] on bit D3 (FAST_SR_s) is used to select the
high speed slew rate for the selected output, the default value
[0] corresponds to the low speed slew rate.
ADDRESS 00110 — NO ACTION REGISTER (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy-chain SPI configuration. This would allow
devices to be unaffected by commands being clocked over a
daisy-chained SPI configuration. By toggling the WD bit
(D15) the watchdog circuitry would continue to be reset while
no programming or data read back functions are being
requested from the device.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
When the CS pin is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-)
first as the new message data is clocked into the SI pin. The
first sixteen bits of data clocking out of the SO, and following
a CS transition, is dependent upon the previously written SPI
word.
33874
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Any bits clocked out of the Serial Output (SO) pin after the
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the CS pin first transitioned to a
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
SO data will represent information ranging from fault
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, SOCHLR, CDTOLR, and
DICR registers.
Note that the SO data will continue to reflect the
information for each output (depending on the previous OD4,
OD3 state) that was selected during the most recent STATR
write until changed with an updated STATR write.
The output status register correctly reflects the status of
the STATR-selected register data at the time that the CS is
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• Battery transients below 6.0V resulting in an undervoltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI
communication following an under-voltage VPWR
condition should be ignored.
• The RST pin transition from a logic [0] to [1] while the
WAKE pin is at logic [0] may result in incorrect data
loaded into the Status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
SERIAL OUTPUT BIT ASSIGNMENT
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following
paragraphs. Table 16, page 26, summarizes SO returned
data for bits OD15 : OD0.
• Bit OD15 is the MSB; it reflects the state of the
watchdog bit from the previously clocked-in message.
• Bit OD14 remains logic [0] except when an undervoltage condition occurred.
• Bit OD13 remains logic [0] except when an over-voltage
condition occurred.
• Bits OD12 : OD8 reflect the state of the bits
SOA4 : SOA0 from the previously clocked in message.
• Bits OD7 : OD4 give the fault status flag of the outputs
HS3 : HS0, respectively.
• The contents of bits OD3 : OD0 depend on bits D4 : D0
from the most recent STATR command SOA4 : SOA0
as explained in the paragraphs following Table 16.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 16. Serial Output Bit Map Description
Previous STATR
SO Returned Data
SO SO SO SO SO OD
A4 A3 A2 A1 A0 15
OD
14
OD
13
OD
12
OD
11
OD
OD9 OD8 OD7 OD6 OD5 OD4
10
OD3
OD2
OD1
OD0
START
A1 A0
_s
0
0
0 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
OTF_s
OCHF_s
OCLF_s
OLF_s
OCR0
0
0
0
0
1 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
IN3_SPI
IN2_SPI
IN1_SPI
IN0_SPI
OCR1
0
1
0
0
1 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
CSNS3 EN
CSNS2 EN
CSNS1 EN CSNS0 EN
SOCHL
A1 A0
R_s
0
1
0 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
SOCH_s
SOCL2_s
SOCL1_s SOCL0_s
CDTOL
A1 A0
R_s
0
1
1 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
OL_DIS_s
OCL_DIS_s
OCLT1_s OCLT0_s
DICR_s A1 A0
1
0
0 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
Fast_SR_s CSNS_high_s DIR_DIS_s
UOVR
0
0
1
0
1 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0 OT_latch_1 OT_latch_0
WDR
0
1
1
0
1 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
PINR0
0
0
1
1
0 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0 HS2_failsafe HS0_failsafe
PINR1
0
1
1
1
0 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0
PINR2
0
1
1
1
1 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
ST2
ST1
ST0 OT_latch_3 OT_latch_2
0
0
RESET N/A N/A N/A N/A N/A
0
0
0
0
0
0
0
0
0
0
0
IN3
0
WDTO
IN2
0
A/O_s
UV_DIS
OV_DIS
WD1
WD0
WD_en
WAKE
IN1
IN0
X
X
0
0
s = Output selection with the bits A1A0 as defined in Table 10, page 23.
ID[1,0]: product identification
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0010
Bits OD3 : OD0 reflect the current state of the Fault register
(FLTR) corresponding to the output previously selected with
the bits A1A0 (Table 17).
Data returned in bits OD3 : OD0 are programmed current
values for the over-current high detection level (refer to
Table 12, page 23) and the over-current low detection level
(refer to Table 11, page 23), corresponding to the output
previously selected with A1A0.
Table 17. Output-Specific Fault Register
OD3
OD2
OD1
OD0
OTF_s
OCHF_s
OCLF_s
OLF_s
s = Selection of the output.
Note The FS pin reports all faults. For latched faults, this
pin is reset by a new Switch OFF command (via SPI or direct
input IN).
PREVIOUS ADDRESS SOA4 : SOA0 = 00001
Data in bits OD3 : OD0 contains IN3_SPI : IN0_SPI
programmed bits for outputs HS3 : HS0, respectively.
PREVIOUS ADDRESS SOA4 : SOA0 = 01001
Data in bits OD3 : OD0 contains the programmed
CSNS3 EN : CSNS0 EN bits for outputs HS3 : HS0,
respectively.
PREVIOUS ADDRESS SOA4 : SOA0= A1A0011
The returned data contains the programmed values in the
CDTOLR register for the output selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0100
The returned data contains the programmed values in the
DICR register for the output selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0 = 00101
The returned data contains the programmed values in the
UOVR register.
PREVIOUS ADDRESS SOA4 : SOA0 = 01101
The returned data contains the programmed values in the
WDR register. Bit OD2 (WDTO) reflects the status of the
33874
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
watchdog circuitry. If WDTO bit is logic [1], the watchdog has
timed out and the device is in Fail-safe mode. IF WDTO is
logic [0], the device is in Normal Mode (assuming the device
is powered and not in the Sleep Mode), with the watchdog
either enabled or disabled.
PREVIOUS ADDRESS SOA4 : SOA0 = 00110
The returned data OD3 and OD2 contain the state of the
outputs HS2 and HS0, respectively, in case of Fail-safe state.
This information is stated with the external resistance placed
at the FSI pin. OD1 indicates if the watchdog is enabled or
not. OD0 returns the state of the WAKE pin.
PREVIOUS ADDRESS SOA4 : SOA0 = 01110
The returned data OD3 : OD0 reflects the state of the direct
pins IN3 : IN0, respectively.
PREVIOUS ADDRESS SOA4 : SOA0 = 01111
The returned data OD3 -OD2 reports the over-temperature
bits configuration of the outputs [3, 2] set through the WDR
SPI register.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
TYPICAL APPLICATION
INTRODUCTION
TYPICAL APPLICATION
INTRODUCTION
The 33874 can be configured in several applications. The figure below shows the 33874 in a typical lighting application.
VPWR
VDD
Voltage regulator
VDD
VPWR
VDD
VPWR
VDD
VPWR
VDD
10k
10k
100nF
10µF
VDD
NC
WAKE
I/O
Microcontroller
I/O
I/O
I/O
I/O
SCLK
CS
I/O
SO
SI
10k
10k
10k
10k
SCLK
CS
RST
SI
SO
TEMP
CSNS
FSI
A/D
A/D
1k
HS0
FS
IN0
IN1
IN2
IN3
10k
10k
10k
10k
R1
100nF
LOAD 0
21W
5W
21W
5W
21W
5W
21W
5W
HS1
LOAD 1
33874
HS2
LOAD 2
HS3
GND
LOAD 3
Automotive lamps do not tolerate high voltages very well. Tests of a few lamps indicate that failures can occur when
18V is applied for a few seconds. Consequently, PWM switching reduces the effective RMS voltage in order to drive
bulbs safety.
For example, to maintain the power dissipation associated with a 13V battery at 100% duty cycle, the duty cycle
would be adjusted to (13/18)², or 52%, when the battery is at 18V.
The loads must be chosen in order to guarantee the device normal operating condition as junction temperature
from -40 to 150 °C. In case of permanent short-circuit conditions, the duration and number of activation cycles must
be limited with a dedicated MCU fault management using the fault reporting through SPI.
33874
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATION
STANDALONE MODE
This section consists of evaluating the MC33874
standalone capability.
CONFIGURATION WITHOUT MCU
The standalone mode is intended for customers who
desire to plug the device and then immediately “play” with it,
without having to connect it to a microcontroller. It also
provides an easy way to evaluate the main electrical features.
Without the Microcontroller to select programmable
parameters and get full diagnosis via the SPI, the MC33874
runs with all parameters set to default.
The input SPI pins and VDD must be connected to ground.
Fail-safe Mode and watchdog timeout must be disabled by
connecting the FSI to GND.
All protection functions are available without SPI
communication. Nevertheless, any configuration is possible
without an MCU to communicate by SPI. Some functions still
enable, but diagnosis is reduced. Available functions and
default parameters are detailed next.
FUNCTIONING WITHOUT MCU
Without an MCU, SPI communication is not possible. Failsafe Mode and watchdog timeout are not useful functions
without an MCU, but still enable. Wake/Sleep Mode is used
to minimize current consumption during Sleep Mode. IN pins
control the corresponding outputs and FS output is active (at
0V) when a default occurs.
The tables 1 and 2 illustrate the available functions without
SPI and default parameters.
Table 1. Available Functions
Function
With SPI
Without SPI
Wake/Sleep Mode
Available
Available
Output ON/OFF control
Via SPI or IN pin
Only with IN pin
Over-temperature protection
Available, can be unlatched
Available
Over-voltage protection
Available, can be disabled
Available, always enable
Under-voltage protection
Available, can be disabled
Available, always enable
Over-current protection
Available, configurable (with 8 low levels and
2 high levels), can be disabled
Available, always enable with default values
Open load, battery disconnect, reverse
battery, ground disconnect protections
Available
Available
Fault diagnosis
Full diagnosis with report by SPI and fault
status pin (/FS)
Limited fault diagnosis with Fault status pin
only
Current sense
Available, 2 configurable ratios
Not available
Watchdog timeout
Available, 4 configurable timings
Available, default value
Configurable slew rate
2 slew rate modes
Default slew rate mode
Analog temperature feedback
Available
Available
Table 2. Default SPI-configurable parameters
Configulable parameter
Default typical value
Over-voltage protection
Enable
Under-voltage protection
Enable
Over-current protection
Enable
Over-current low level
OCLO0
Over-current high level
OCHI0
Over-current detect blanking time
tOCLO0
Current sense
Disable
Watchdog time timeout
TWDTO0
Slew rate mode
Slow mode
Table 2 illustrates default parameters after resetting or
applying supply voltage to the MC33874. Levels and timings
are typical values.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
TYPICAL APPLICATION
DIAGNOSIS WITHOUT MCU
When any fault appears (over-current, open load…), a full
diagnosis can be reported via the SPI. Without an MCU, the
fault status pin allows reduced diagnosis, as illustrated in
table 3.
Table 3. Diagnosis without SPI
Normal operation
Over-temperature
Under-voltage
Over-voltage
Over-current
Short-circuit to VPWR
Open load
IN[x] level
HS[x] level
FS level
H
H
H
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
H
L
H
H
H
L
Z
L
H
H
H
Latched
N/A
YES
YES
NO
YES
NO
NO
H : High Level, L : Low Level, Z : High-impedance, potential depends on the external circuit
We can note that it is not possible to distinguish over
temperature, over-current, under-voltage, and over-voltage.
Nevertheless, Open load and short-circuit to VPWR fault can
be singled out. All protections are reported to Fault status pin
(FS), Open load and short-circuit to VPWR are reported only if
the Output is OFF. If the fault is latched, the output must be
turned OFF then ON to disable the fault.
CONCLUSION
Although the MC33874 is not fully functional without a
microcontroller to control and program it, standalone
functioning is safe because all protections are available.
Diagnosis is limited, but the fault status pin will report any
malfunction.
This is a good way to evaluate the main electrical
MC33874 features. Some simplified applications can also
use the MC33874 switch without an MCU to drive a high
power load with full protection.
33874
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 33874 is packaged in a surface mount power package
intended to be soldered directly on the printed circuit board.
The 33874 was qualified in accordance with JEDEC
standards JESD22-A113-B, J-STD-020A with MSL3/245°C
Sn-Pb soldering profile and JESD22-B102D as for
solderability test, with reflow conditions as follows:
Reflow Soldering: 215°C+/-5°C
Wave Soldering: 245°C +/-5°C
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ART10510D listed below.
PNA SUFFIX (PB-FREE)
24-PIN PQFN
NONLEADED PACKAGE
98ART10510D
ISSUE O
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
PACKAGING
PACKAGE DIMENSIONS
PNA SUFFIX (PB-FREE)
24-PIN PQFN
NONLEADED PACKAGE
98ART10510D
ISSUE O
33874
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PNA SUFFIX (PB-FREE)
24-PIN PQFN
NONLEADED PACKAGE
98ART10510D
ISSUE O
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33874
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the 33874 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
HIGH SIDE SWITCH
Packaging and Thermal Considerations
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to RθJ21
and RθJ22, respectively.
TJ1
TJ2
=
RθJA11 RθJA12
RθJA21 RθJA22
.
P1
P2
PNA SUFFIX
98ART10510D
24-PIN PQFN (12 x 12)
Note For package dimensions, refer to
the 33874 data sheet.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained
by measurement and simulation according to the standards listed below.
Table 18. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
Resistance
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
20
16
39
RθJBmn(2), (3)
6
2.0
26
RθJAmn(1), (4)
53
40
73
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