NXP Semiconductors
Data sheet: Advance Information
Document Number: MC33SA0528
Rev. 3.0, 7/2016
Dual DSI master transceiver
The 33SA0528 is a third generation SMARTMOS standalone, dual-channel
distributed system interface (DSI) master device.
Each of the two independent channels contain a differential driver and a dual
adder receiver. The embedded DSI protocol engine converts the DSI data
between the physical interface and the two redundant SPI interfaces. The MCU
can control and configure the 33SA0528 and extract all of the slaves
transceivers data from it via the dual SPI.
To ensure the communication reliability, the 33SA0528 uses an on-chip band
gap reference regulator to monitor all of the supply voltages, and uses an onchip oscillator to monitor the PLL clock for the external clock error detection.
Features
• Two independent DSI master channels
• Supports command and response mode for slave configuration
• Supports periodic data collection mode (PDCM) for periodic slave data
transfers
• Supports discovery mode for slave physical address self-programming
• 10 MHz 32-bit dual SPI: main SPI for device configuration and DSI operation,
and redundant SPI for safety purposes
• Point-to-point, parallel, daisy chain bus topologies
• Various diagnostic features
VCC5
33SA0528
Automotive restraint system
AC SUFFIX (PB-FREE)
98ASH70029A
32-PIN LQFP
Applications
• Automotive airbag and safety
• Industrial systems
• Sense and trigger applications
VDSI
MCU
33SA0528
VDSI
VCC5
GPIO
RSTB
SPI0_SCK
SPI0_CS
SPI0_MOSI
SPI0_MISO
SCK0
CS0B_D
MOSI0
MISO0
SPI1_SCK
SPI1_CS
SPI1_MOSI
SPI1_MISO
SCK1
CS1B
MOSI1
MISO1
CLKOUT
CLK_IN
V2P5A
V2P5D
GNDA
GNDD
DH0
DL0
GNDP_DSI0
GNDP_DSI1
DH1
DL1
CLK_OUT
GNDSUB
Figure 1. 33SA0528 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
DSI Slaves Interfaces
CLK
Table of Contents
1
2
3
4
5
6
7
8
9
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4 Supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General IC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 DSI protocol engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Power supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 Clock and reset module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
33SA0528
NXP Semiconductors
2
1
Orderable parts
This section describes the part numbers available to be purchased along with their differences.
Table 1. Orderable part variations
Part number
MC33SA0528AC
Notes
Temperature (TA)
Package
(1)
-40 °C to 125 °C
32-PIN LQFP
Notes
1. To order parts in tape & reel, add the R2 suffix to the part number.
33SA0528
3
NXP Semiconductors
2
Internal block diagram
VDSI
Voltage Supplies Monitors
Ch0 Driver/Receiver
VCC5
CLK_IN
CLK_OUT
Bus Receiver
Current Limiter
DH0
CLK Monitor
and PLL
CS0B_D
SCLK0
MOSI0
MISO0
SPI0_D
Registers
and
State Machine
CS1B
SCLK1
MOSI1
MISO1
SPI1
Registers
and
State Machine
GNDA
GNDD
V2P5A
V2P5D
Bus Driver
POR
Adder
DSI Protocol Engine
RSTB
TS
DL0
Receiver Sum1
Receiver Sum2
DH1
Ch1 Driver/Receiver
DL1
Bandgap References
Internal
Voltages
GNDP_DSI
Figure 2. 33SA0528 simplified internal block diagram
33SA0528
NXP Semiconductors
4
GNDD
VCC5
NC
NC
V2P5D
Pinout diagram
V2P5A
3.1
GNDA
Pin connections
NC
3
CLKOUT
GNDP_DSI0
3
22
MISO1
DL0
4
21
GNDSUB
GNDSUB
5
20
CLKIN
DH1
6
19
NC
GNDP_DSI1
7
18
NC
DL1
8
17
10 11 12 13 14 15 16
NC
MISO0
MOSI1
RSTB
9
MOSI0
23
NC
2
CS1B
DH0
SCK1
32 21 30 29 28 27 26 25
24
CS0B_D
1
SCK0
VDSI
Figure 3. 33SA0528 32-pin LQFP pinout diagram
3.2
Pin definitions
A functional description of each pin can be found in the functional pin description section beginning on page 9.
Table 2. 33SA0528 pin definitions
Pin number
Pin name
Pin function
Definition
1
VDSI
Power
2
DH0
Output driver
3
GND_DSI0
Ground
4
DL0
Output driver
5
GNDSUB
Ground
6
DH1
Output driver
7
GND_DSI1
Ground
8
DL1
Output driver
9
RSTB
Reset
A low level on this pin returns all registers to a known initial state.
10
SCK0
Input
Clocks data in from and out to DSI_SPI0. MISO0 data changes on the negative transition of SCLK0.
MOSI0 is sampled on the positive edge of SCLK0
11
CS0B_D
Input
When this signal is high, SPI signals on DSI_SPI0 are ignored. Asserting this pin low starts a DSI_SPI0
transaction. The DSI_SPI0 transaction is signaled as completed when this signal returns high
12
SCK1
Input
Clocks data in from and out to DSI_SPI1. MISO1 data changes on the negative transition of SCLK1.
MOSI1 is sampled on the positive edge of SCLK1
This supply input is used to provide the positive level output of buses
Bus 0 high-side
Bus power return
Bus 0 low-side
This pin must be tied to ground in the application.
Bus 1 high-side
Bus power return
Bus 1 low-side
33SA0528
5
NXP Semiconductors
Table 2. 33SA0528 pin definitions(continued)
Pin number
Pin name
Pin function
Definition
13
CS1B
Input
When this signal is high, SPI signals on DSI_SPI1 are ignored. Asserting this pin low starts a DSI_SPI1
transaction. The DSI_SPI1 transaction is signaled as completed when this signal returns high
14
N.C
—
15
MOSI0
Input
SPI data into DSI_SPI0. This data input is sampled on the positive edge of SCLK0
16
MOSI1
Input
SPI data into DSI_SPI1. This data input is sampled on the positive edge of SCLK1
17
N.C
—
This pin is not internally connected and must be left unconnected or tied to ground in the application
18
N.C
—
This pin is not internally connected and must be left unconnected or tied to ground in the application
This pin is not internally connected and must be left unconnected or tied to ground in the application
This pin is not internally connected and must be left unconnected or tied to ground in the application
19
N.C
—
20
CLK_IN
Input
21
GNDSUB
Ground
This pin must be tied to ground in the application
22
MISO1
Output
DSI_SPI1 data sent to the MCU by this device. This data output changes on the negative edge of
SCLK1. When CS1B_D is high, this pin is high
23
CLK_OUT
Output
Output buffered clock signal that is input from CLK_IN
24
MISO0
Output
DSI_SPI0 data sent to the MCU by this device. This data output changes on the negative edge of
SCLK0. When CS0B_D is high, this pin is set at high impedance
25
GNDD
Ground
Ground for the digital circuits. Ground for IDDQ. This pin should be tied to MCU ground
26
VCC5
Power
Regulated 5.0 V input
27
N.C
—
This pin is not internally connected and must be left unconnected or tied to ground in the application
28
N.C
—
This pin is not internally connected and must be left unconnected or tied to ground in the application
29
V2P5D
Output
0.1 μF capacitor should be connected between this pin and ground
30
V2P5A
Output
0.1 μF capacitor should be connected between this pin and ground
31
GNDA
Ground
Ground for the analog circuits. This pin is not connected internally to the other grounds on the chip. It
should be connected to a quiet ground on the board
32
N.C
—
This pin is not internally connected and must be left unconnected or tied to ground in the application
4.0 MHz clock input
33SA0528
NXP Semiconductors
6
4
General product characteristics
4.1
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Electrical ratings
VDSI
DSI bus voltage supply
• Steady-state
-0.3
10
V
VCC5
VCC logic supply voltage
-0.3
7.0
V
V2P5A
Regulated output voltage
-0.3
3.0
V
V2P5D
Regulated output voltage
-0.3
3.0
V
VLOGIC
Voltage on logic input/output pins
-0.3
VCC5 + 3.0
V
ILOGIC
Current on logic input/output pins
—
20
mA
VBUS
Voltage on DSI bus pins
-0.3
20
V
IBUS
Current on DSI bus pins
—
200
mA
VESD
ESD voltage
• Human body model (HBM)
• Machine model (MM)
• Charge device model (CDM)
—
—
—
±2000
±150
±500
V
(2)
Notes
2. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the machine model (MM)
(CZAP = 200 pF, RZAP = 0 Ω), and the charge device model.
4.2
Thermal characteristics
Table 4. Thermal ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Min.
Max.
Unit
Operating temperature
• Ambient
• Junction
-40
-40
105
150
°C
TSTG
Storage temperature
-55
150
°C
TSD
Thermal shutdown (bus driver)
155
195
°C
TA
TJ
Description (rating)
Notes
33SA0528
7
NXP Semiconductors
4.3
Operating conditions
This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.
Table 5. Operating conditions
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Min.
Max.
Unit
VDSI
Full characteristics are guaranteed
9.0
9.6
V
VDSI
Some characteristics are out of specification, but the 33SA0528 can
communicate with the bus slaves
8.8
9.0
V
VDSI
Some characteristics are out of specification, but the VDSI monitor is active, so
the RNE bit is never set
8.2
8.8
V
VCC5
Functional operating VCC5 voltage
4.8
5.25
V
4.4
Notes
Supply currents
This section describes the current consumption characteristics of the device, as well as the conditions for the measurements.
Table 6. Supply currents
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device. Typical values noted reflect the approximate parameter mean at TA = 25 °C.
Symbol
Ratings
IVDSI
Current on DSI bus
• 9.6 V (disabled)
• 9.6 V (enabled 1.0 mA/channel)
• 9.6 V (enabled 40 mA/channel)
IVCC
Current on VCC5 supply
Min.
Typ.
Max.
8.0
11
13
18
24
30
96
108
114
—
—
2.0
Unit
Notes
mA
(3)
mA
Notes
3. IOUT is the total current for all sensors connected to two DSI interfaces. For example: If 40 mA is flowing out (DHx to DLx) on each DSI channel,
then IOUT = 2 x 40 mA = 80 mA. The max. internal current flowing from VDSI to GND is ’28 mA + (80 mA/14) = 34 mA’. The max. total current is
flowing from VDSI (includes sensor current) is ’34 mA + 80 mA = 114 mA’. If the DSI channel-0 is enabled and 40 mA is flowing out (DHx to DLx),
the other DSI channel (ch1) is the disabled case. The max. internal current flowing from VDSI to GND is ’19 mA + (40 mA/14) = 22 mA’. The Max.
total current flowing from VDSI (include sensor current) is ’22 mA + 40 mA = 62 mA’.
33SA0528
NXP Semiconductors
8
5
General IC functional description
5.1
Block diagram
Main SPI
Redundant SPI
Power Supply
Monitoring
Clock Monitoring
and Reset
DSI Protocol Engine
Figure 4. 33SA0528 functional block diagram
5.2
•
•
•
•
•
•
•
Features
Main SPI at 10 MHz and 32-bit frame size provides access to all main registers
Redundant SPI with the same format provides access to redundant registers with slaves’ data, for safety purposes
DSI protocol engine provides two independent channels to communicate and decode up to eight sensors
Power supplies monitor detects and informs undervoltages on all four power pins (VDSI, VCC5, V2P5A, V2P5D)
Internal PLL block generates 10 MHz stable frequency from 4.0 Mhz input clock
Internal clock generator (no resonator) provides internal 4.0 MHz reference for clock frequency watchdog block
Clock monitor sets proper flags if any abnormality is detected in clock or PLL frequencies
5.3
Functional description
The 33SA0528 is a DSI master device behaving as an interface between the MCU and the DSI slaves connected to the system bus. It
supports up to four slaves connected to each of the two available DSI channels, allowing for a total of eight slaves. The MCU can access
the registers in the 33SA0528 via two independent SPIs, the first one being for configuration purposes and to interact with the DSI slaves.
The second one provides full redundancy of slaves’ responses, which is designed for safety applications. The 33SA0528 can also act as
a DSI Companion Chip when working together with a DSI SBC, expanding this last chip’s capacity regarding the maximum number of DSI
slaves it can decode.
5.4
Communication
5.4.1
SPI
Both SPI channels share the same speed and format, so only one MCU configuration scheme is needed to communicate with the
33SA0528. The maximum frequency of this interface is clocked at 10 MHz and provided by the internal PLL, generated from the 4.0 MHz
clock input. Each command follows a 32-bit format, with the 5th byte being optional. The SPI is in-command full-duplex, which means the
33SA0528 responds during the same SPI frame in which it demands to read a register, meaning the device can write or read any register
in just one SPI command.
5.4.2
DSI
The 33SA0528 provides an interface for a DSI Differential bus, having two independent channels. Each channel can drive and decode up
to four slaves connected in either point-to-point, parallel, or resistor-based daisy-chained bus. For each channel, the DSI Receiver block
provides a doubled redundancy when composing the differential (high/send and low/return) values read from the bus, which makes this
device is ideal for safety applications. For more information on the DSI protocol, refer to its consortium web site: http://
www.dsiconsortium.org.
33SA0528
9
NXP Semiconductors
6
Functional block description
6.1
SPI
6.1.1
Block diagram
SPI0
SPI1
SCK0
CS0B_D
MOSI0
MISO0
SCK1
CS1B
MOSI1
MISO1
To MCU
SPI0
To MCU
SPI1
Figure 5. SPI modules pins and block diagram
6.1.2
Timings and configuration
The timings and commands format is the same for both SPI modules.
tNEG
CSB
VIH
VIL
VIL
t LAG
t CYC
t LEAD
tHI
tLO
tF
tR
VIH
VIL
SCLK
tSU
tH
VIH
MOSI
X
VIH
MSB
LSB
tV
tDIS
VOH
MISO
VOL
X
MSB
LSB
Figure 6. SPI modules timings
33SA0528
NXP Semiconductors
10
Table 7. SPI modules timings
Symbol
Parameter
Min.
Typ.
Max.
Unit
tCYC
SPI clock cycle time
99
—
—
ns
tHI
SPI clock high time
40
—
—
ns
tLO
SPI clock low time
40
—
—
ns
tLEAD
SPI chip select lead time
50
—
—
ns
tLAG
SPI chip select lag time
50
—
—
ns
tSU
Data setup time
• MOSI valid after SCK rising edge
10
—
—
ns
tH
Data hold time
• MOSI valid after SCK rising edge
10
—
—
ns
tV
Data valid time
• SCK falling edge to MISO valid, C = 50 pF
—
—
25
ns
Output disable time
• CSB rise to MISO high-impedance
—
—
50
ns
tR
Rise time (30% VCC to 70% VCC)
• SCK, MOSI
—
—
10
ns
tF
Fall time (70% VCC to 30% VCC)
• SCK, MOSI
—
—
10
ns
600
—
—
ns
tDIS
tNEG
6.1.3
Chip select negate timer (read/write)
Notes
Frame format
The SPI module transactions start with a command and address byte and can be followed by three or four bytes of data. The start of a
SPI transaction is signaled by the CSB signal being asserted low. The first bit sent (bit 7) of the first byte signals a read (bit = ‘0’) or write
(bit = ‘1’) operation. The last seven bits (bit 6 to 0) of the first byte indicate the address of the desired register. Both 4-byte access and 5byte access are valid for all register address. During a SPI transaction the 33SA0528 checks for SPI framing errors. A framing error is
defined as any number of clocks received which is neither 32 nor 40. If this occurs, all bits sent by the SPI master are discarded and no
registers are updated.
CSB
SCK
1st byte
MOSI
REG ADDR
Write/Read bit
MISO
2nd byte
3rd byte
4th byte
DATA
DATA
DATA
DATA
DATA
DATA
7 bits
N/A
Figure 7. SPI module frames format - 4 byte access
33SA0528
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NXP Semiconductors
CSB
SCK
1st byte
MOSI
2nd byte
3rd byte
4th byte
5th byte
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
REG ADDR
Write/Read bit
MISO
7 bits
N/A
5th byte is only available for SPI0 registers 0x00 and 0x10
Figure 8. SPI modules frames format - 5 bytes access
6.1.4
Register maps
Table 8. SPI0 register map
Address
Name
Type
2nd byte
3rd byte
4th byte
5th byte (optional)
0x00
CRM Tx/Rx Data Buffer D0
R/W
D0DATA2
0x01
CRM Tx/Rx Data Buffer D0
R
D0DATA1
D0DATA1
D0DATA0
D0RES_STAT
D0DATA0
D0RES_STAT
—
0x02
PDCM Data Buffer D0R0
R
D0R0DATA2
D0R0DATA1
D0R0DATA0
—
0x04
PDCM Data Buffer D0R1
R
D0R1DATA2
D0R1DATA1
D0R1DATA0
—
0x06
0x08
PDCM Data Buffer D0R2
R
D0R2DATA2
D0R2DATA1
D0R2DATA0
—
PDCM Data Buffer D0R3
R
D0R3DATA2
D0R3DATA1
D0R3DATA0
—
0x0A
PDCM Control D0
R/W
D0PDCM_CTRL
D0PDCM_DLY
N/A
—
0x0B
Channel Control D0
R/W
D0CTRL
D0DPC
D0STAT
—
0x0C
PDCM Configuration D0
R/W
D0CHIP_TIME
D0SID_R0R1
D0SID_R2R3
—
0x0E
Channel Clear D0
R/W
D0CLR
N/A
N/A
—
0x10
CRM Tx/Rx Data Buffer D1
R/W
D1DATA2
D1DATA1
D1DATA0
D1RES_STAT
0x11
CRM Tx/Rx Data Buffer D1
R
D1DATA1
D1DATA0
D1RES_STAT
—
0x12
PDCM Data Buffer D1R0
R
D1R0DATA2
D1R0DATA1
D1R0DATA0
—
0x14
PDCM Data Buffer D1R1
R
D1R1DATA2
D1R1DATA1
D1R1DATA0
—
0x16
PDCM Data Buffer D1R2
R
D1R2DATA2
D1R2DATA1
D1R2DATA0
—
0x18
PDCM Data Buffer D1R3
R
D1R3DATA2
D1R3DATA1
D1R3DATA0
—
0x1A
PDCM Control D1
R/W
D1PDCM_CTRL
D1PDCM_DLY
N/A
—
0x1B
Channel Control D1
R/W
D1CTRL
D1DPC
D1STAT
—
0x1C
PDCM Configuration D1
R/W
D1CHIP_TIME
D1SID_R0R1
D1SID_R2R3
—
0x1E
Channel Clear D1
R/W
D1CLR
N/A
N/A
—
0x40
NCKPTN
R
0xAA
0xAA
0xAA
—
0x41
CHKPTN
R
0x55
0x55
0x55
—
0x42
MASKID
R
MASKID
—
—
—
Notes
4. Dn registers refer to the DSI channel n, so D0 corresponds to channel 0 and D1 corresponds to channel 1.
5. Rm registers refer to the DSI slave addressed at m, so R0 corresponds to slave at address 0 and so on.
6. The registers that correspond to different DSI channels and addresses have the same format and description.
33SA0528
NXP Semiconductors
12
Table 9. SPI1 register map
Address
Name
Type
2nd byte
3rd byte
4th byte
5th byte (optional)
0x02
PDCM Data Buffer D0R0
R
D0R0DATA2
D0R0DATA1
D0R0DATA0
-
0x04
PDCM Data Buffer D0R1
R
D0R1DATA2
D0R1DATA1
D0R1DATA0
-
0x06
PDCM Data Buffer D0R2
R
D0R2DATA2
D0R2DATA1
D0R2DATA0
-
0x08
PDCM Data Buffer D0R3
R
D0R3DATA2
D0R3DATA1
D0R3DATA0
-
0x12
PDCM Data Buffer D1R0
R
D1R0DATA2
D1R0DATA1
D1R0DATA0
-
0x14
PDCM Data Buffer D1R1
R
D1R1DATA2
D1R1DATA1
D1R1DATA0
-
0x16
PDCM Data Buffer D1R2
R
D1R2DATA2
D1R2DATA1
D1R2DATA0
-
0x18
PDCM Data Buffer D1R3
R
D1R3DATA2
D1R3DATA1
D1R3DATA0
-
0x40
NCKPTN
R
0xAA
0xAA
0xAA
-
0x41
CHKPTN
R
0x55
0x55
0x55
-
Notes
• These registers have the same format and description as their SPI0 counterparts, as they are just for redundancy purposes.
6.1.5
6.1.5.1
Registers description
CRM Tx/Rx data buffer Dn
Table 10. 2nd byte - DnDATA2
Bit
R
W
Reset
7
6
5
4
3
2
1
0
DnDATA[23]
DnDATA[22]
DnDATA[21]
DnDATA[20]
DnDATA[19]
DnDATA[18]
DnDATA[17]
DnDATA[16]
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DnDATA[15]
DnDATA[14]
DnDATA[13]
DnDATA[12]
DnDATA[11]
DnDATA[10]
DnDATA[9]
DnDATA[8]
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DnDATA[7]
DnDATA[6]
DnDATA[5]
DnDATA[4]
DnDATA[3]
DnDATA[2]
DnDATA[1]
DnDATA[0]
0
0
0
0
0
0
0
0
Table 11. 3rd byte - DnDATA1
Bit
R
W
Reset
Table 12. 4th byte - DnDATA
Bit
R
W
Reset
Table 13. 5th byte - DnRES_STAT
Bit
7
6
5
4
3
2
1
0
R
ER
-
-
UV
TE
RNE
0
1
33SA0528
13
NXP Semiconductors
Table 13. 5th byte - DnRES_STAT
Bit
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
1
W
Reset
Table 14. CRM Tx/Rx data buffer Dn fields description
Field
Description
DnDATA[23:0]
CRM data to transmit or CRM data received from slaves
If the DSI channel EN bit is set, and the 33SA0528 is not in PDCM, data is transmitted after being written to the register. Also,
slaves’ CRM data is written back to the buffer as soon as it is received through the bus.
ER
Error bit
This bit indicates, for received data, there is either a CRC error, an undefined symbol error, or data mismatch between the dual
DSI receivers.
UV
Undervoltage
This bit indicates VDSI dropped below its minimum threshold for a specified time. Refer to Power supply monitor on page 30.
TE
Transmit empty
This bit indicates there is no data in the transmit buffer.
Receiver not empty
This bit indicates there is data available that has been received from the slaves.
RNE
6.1.5.2
PDCM data buffer DnRm
Table 15. 2nd byte - DnRmDATA2
Bit
7
6
5
4
3
2
1
0
R
ER
-
RNE
UV
DnRmData[19]
DnRmData[18]
DnRmData[17]
DnRmData[16]
0
0
0
0
0
0
0
0
W
Reset
Table 16. 3rd byte - DnRmDATA1
Bit
7
6
5
4
3
2
1
0
R
DnRmData[15]
DnRmData[14]
DnRmData[13]
DnRmData[12]
DnRmData[11]
DnRmData[10]
DnRmData[9]
DnRmData[8]
0
0
0
0
0
0
0
0
W
Reset
Table 17. 4th byte - DnRmDATA0
Bit
7
6
5
4
3
2
1
0
R
DnRmData[7]
DnRmData[6]
DnRmData[5]
DnRmData[4]
DnRmData[3]
DnRmData[2]
DnRmData[1]
DnRmData[0]
0
0
0
0
0
0
0
0
W
Reset
33SA0528
NXP Semiconductors
14
Table 18. PDCM data buffer DnRm fields description
Field
Description
DnRmDATA[19:0]
PDCM data received from slaves
DnRmDATA[19:16] represent the source ID field of the slave, and it is used as seed for CRC calculation.
ER
Error bit
This bit indicates, for received data, that there is either a CRC error, an undefined symbol error, or data mismatch between the
dual DSI receivers.
UV
Undervoltage
This bit indicates VDSI dropped below its minimum threshold for a specified time. Refer to Power supply monitor on page 30.
Receiver not empty
This bit indicates there is data available that has been received from the slaves.
RNE
6.1.5.3
PDCM control Dn
Table 19. 2nd byte - DnPDCM_CTRL
Bit
R
W
Reset
7
6
5
4
3
2
1
0
DnBRC
-
-
-
-
-
DnAUTO
DnPDCM_EN
0
0
0
0
0
0
0
0
Table 20. 3rd byte - DnPDCM_DLY
Bit
R
W
Reset
7
6
5
4
3
2
1
0
DELAY[7]
DELAY[6]
DELAY[5]
DELAY[4]
DELAY[3]
DELAY[2]
DELAY[1]
DELAY[0]
0
0
0
0
0
0
0
0
Table 21. PDCM control Dn fields description
Field
Description
DnBRC
Broadcast read command
Each time this bit is set, a manual BRC is transmitted through the DSI bus. Only valid when DnPDCM_EN is 1 and DnAUTO is 0.
DnAUTO
Automatic BRC
When this bit is set, a BRC is transmitted automatically through the DSI bus every 500 µs. Write access to this bit is ignored when
DnPDCM_EN is 0.
DnPDCM_EN
Periodic data collection mode enable
Once this bit is set, the 33SA0528 enters PDCM, preventing any CRM communication or any configuration change. This bit can
be cleared by clearing the channel, by writing to the channel clear Dn register.
DELAY[7:0]
Broadcast read command delay
This bits set the delay to be applied to both manual and automatic BRCs, from BRC bit set to its transmission through the DSI bus.
It is calculated as Delay time = DELAY [ 7:0 ] × 5clockcounts , with a range of 0 ‘~ 127.5 µs and a 0.5 µs step at 10 MHz.
33SA0528
15
NXP Semiconductors
6.1.5.4
Channel control Dn
Table 22. 2nd byte - DnCTRL
Bit
7
6
5
4
3
2
1
0
R
0
0
0
0
UVDSI_ON
EN
BCK[1]
BCK[0]
0
0
0
0
0
0
0
0
2
1
0
DPC[2]
DPC[1]
DPC[0]
W
Reset
Table 23. 3rd byte - DnDPC
Bit
7
6
5
4
3
R
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Table 24. 4th byte - DnSTAT
Bit
7
6
5
4
3
2
1
0
R
CFM3
CFM2
GNDA_OP
GNDD_OP
OCS
TS
0
UV
W
w0c
w0c
w0c
w0c
w0c
w0c
Reset
0
0
0
0
0
0
w0c
0
0
Table 25. Channel control Dn fields description
Field
UVDSI_ON
EN
Description
VDSI undervoltage monitor test function
This bit forces an undervoltage detection on the UVDSI monitor, for test purposes, by forcing its input to ground.
0: Normal operation. UVDSI module monitors the voltage in VDSI pin.
1: Test operation. UVDSI is forced to ground, so the UV bit in status registers should be set.
DSI channel enable
0: Disable the DSI channel, if conditions are met.
1: Enable the DSI channel, if conditions are met.
BCK[1:0]
Buffer check mode
If both these bits are set simultaneously (in the same SPI transaction), the 33SA0528 enters BCM. Refer to the DSI protocol
engine module. Note that the BCK[1:0] bits have higher priority than EN and DPC[2:0], meaning if are three fields are written at
the same time, only BCK[1:0] is considered.
DPC[2:0]
Discovery pulses count
If conditions are met, setting these bits transmits the set number of discovery pulses through the DSI bus. Refer to DSI protocol
engine on page 20 for required conditions.
CFM3 and CFM2
Clock failure monitor flags
CFM3=0 and CFM2=0: Normal case. Each bit can be cleared by writing a 0 to them.
CFM3=1: The internal PLL in charge of generating the internal 10 MHz frequency is unlocked.
CFM2=1: The clock watchdog indicates CLKIN is out of its 4.0 MHz accepted range.
GNDA_OP
GNDA open pin
0: Normal case. The bit can be cleared by writing a 0 to it.
1: GNDA pin is open.
GNDD_OP
GNDD open pin
0: Normal case. The bit can be cleared by writing a 0 to it.
1: GNDD pin is open.
OCS
Overcurrent shutdown
0: Normal case. The bit can be cleared by writing a 0 to it.
1: The DSI bus current limiter has worked for a certain amount of time. Refer to Power supply monitor on page 30.
33SA0528
NXP Semiconductors
16
Table 25. Channel control Dn fields description (continued)
Field
Description
TS
Thermal shutdown
0: Normal case. The bit can be cleared by writing a 0 to it.
1: The DSI bus thermal limit has been reached. Refer to Power supply monitor on page 30.
UV
Undervoltage
0: Normal case. The bit can be cleared by writing a 0 to it.
1: VDSI dropped below its minimum threshold for a specified time. Refer to Power supply monitor on page 30.
6.1.5.5
PDCM configuration Dn
Table 26. 2nd byte - DnCHIP_TIME
Bit
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
CHIPTIME[1]
CHIPTIME[0]
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
SID_R0[3]
SID_R0[2]
SID_R0[1]
SID_R0[0]
SID_R1[3]
SID_R1[2]
SID_R1[1]
SID_R1[0]
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
SID_R2[3]
SID_R2[2]
SID_R2[1]
SID_R2[0]
SID_R3[3]
SID_R3[2]
SID_R3[1]
SID_R3[0]
0
0
0
0
0
0
0
0
W
Reset
Table 27. 3rd byte - DnSID_R0R1
Bit
R
W
Reset
Table 28. 4th byte - DnSID_R2R3
Bit
R
W
Reset
Table 29. PDCM configuration Dn fields description
Field
CHIPTIME[3:0]
SID_Rm[3:0]
Description
DSI responses chip time
These bits set the chip duration to use when decoding the current responses from slaves in the DSI bus.
00: 3.0 µs
01: 3.5 µs
10: 4.0 µs
11: 4.5 µs
Source ID
These bits set the expected source ID of the DSI slave at address m. These values are used as CRC seeds.
33SA0528
17
NXP Semiconductors
6.1.5.6
Channel clear Dn
Table 30. 2nd byte - DnCLR
Bit
R
W
7
6
5
4
3
2
1
0
DnCLR[7]
DnCLR[6]
DnCLR[5]
DnCLR[4]
DnCLR[3]
DnCLR[2]
DnCLR[1]
DnCLR[0]
0
0
0
0
0
0
0
0
Reset
Table 31. Channel clear Dn fields description
Field
Description
Channel clear
When writing 0xFF to this byte, all the registers of the corresponding channel n are reset to its initial values.
DnCLR[7:0]
6.1.5.7
NCKPTN
Table 32. 2nd byte - 0xAA
Bit
7
6
5
4
3
2
1
0
R
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
Reset
Table 33. 3rd byte - 0xAA
Bit
7
6
5
4
3
2
1
0
R
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
Reset
Table 34. 4th byte - 0xAA
Bit
7
6
5
4
3
2
1
0
R
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
Reset
Table 35. NCKPTN fields description
Field
0xAA
Description
Inverted pattern check
This register and its bytes are meant to check validate the communication with the device.
33SA0528
NXP Semiconductors
18
6.1.5.8
CHKPTN
Table 36. 2nd byte - 0x55
Bit
7
6
5
4
3
2
1
0
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
Reset
Table 37. 3rd byte - 0x55
Bit
7
6
5
4
3
2
1
0
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
Reset
Table 38. 4th byte - 0x55
Bit
7
6
5
4
3
2
1
0
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
Reset
Table 39. CHKPTN fields description
Field
Description
Pattern check
This register and its bytes are meant to check validate the communication with the device.
0x55
6.1.5.9
MASKID
Table 40. 2nd byte - MASKID
Bit
7
6
5
4
3
2
1
0
R
MASKID[7]
MASKID[6]
MASKID[5]
MASKID[4]
MASKID[3]
MASKID[2]
MASKID[1]
MASKID[0]
W
Reset
Table 41. MASKID fields description
Field
MASKID[7:0]
Description
Mask ID
These bits indicate the chip's silicon revision number
33SA0528
19
NXP Semiconductors
6.1.6
Electrical characteristics
Table 42. SPI modules electrical characteristics
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
2.0
—
0.1
—
—
0.35
—
0.9
0.8
Unit
VIH
VIL
I/O logic levels (CSB, MOSI, SCK)
• Input high-voltage
• Input low-voltage
• Input hysteresis
CI
Input capacitance
• CSB, MOSI, and SCK
—
—
10
pF
VOL
Output low voltage
• MISO pin = 1.0 mA
0.0
—
0.5
V
VOH
Output high voltage
• MISO pin = -1.0 mA
VCC5 - 0.5
—
IMISO
Output leakage current
• MISO pin = 0 V
• MISO pin = VCC5
-10
-10
—
—
10
10
μA
VHYST
V
V
IPU
SCK, CSB pull-up current
• VOUT = VCC5 - 2.0 V
-50
-30
-10
μA
IPD
MOSI pull-down current
• VOUT = 1.0 V
5.0
10
13
μA
6.2
DSI protocol engine
6.2.1
Block diagram
Notes
SPI
DSI Channel 1
DSI Channel 0
DH1
DL1
GNDP_DSI1
DH0
DL0
GNDP_DSI0
CH0
To DSI3 bus
(slaves)
CH1
Figure 9. DSI modules pins and block diagram
33SA0528
NXP Semiconductors
20
6.2.2
DSI implementation parameters
6.2.2.1
Bus driver
VDSI
VHIGH
Bus Receiver
DnH
SPI
Current
Limitation
DSI Logic
Differential voltage
(DnH – DnL)
VLOW
DnL
Hi Z
Figure 10. DSI bus driver block diagram
CS0B
2V
tSE_DLY
Command
VHIGH
DnH
VHIGH-0.6
VHIGH-0.9
VHIGH-1.1
VHIGH-1.4
VLOW
tSLEW
VHIGH
VHIGH-0.3
0.9*VHIGH
VHIGH-0.9
VHIGH-1.1
VLOW
tDISC_PULSE
tDISC_Per
0.1*VHIGH
GND
tEN_Rise
Figure 11. DSI bus voltages timings
33SA0528
21
NXP Semiconductors
Table 43. Bus driver characteristics
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
VHIGH
DSI voltage level high (DnH open, DnL open)
7.5
—
—
V
VLOW
DSI voltage level low (DnH open, DnL open)
VHIGH - 2.2
—
VHIGH - 1.8
V
-150
—
150
mV
Common mode voltage peak to peak during single bit signal
—
—
100
mV
RHIGH
High-side output resistance
—
3.0
5.4
W
RLOW
Low-side output resistance
—
3.0
5.4
W
Total output resistance (RHIGH + RLOW)
—
—
10
W
DRATE
Communication data rate
—
125
—
kbps
tSE_DLY
Command start delay (CS0B rising edge to command start edge)
• PDCM (DnPDCM_DLY = 0)
• CRM
—
—
—
—
1.5
5.0
μs
Voltage signal slew rate
2.0
—
6.0
V/μs
Bus enable rising time
—
—
10
μs
tDISC_PULSE
Self discovery pulse width
15
16
17
μs
tDISC_PER
Self discovery pulse period
120
125
130
μs
VHIGH_Drift
RM
tSLEW
tEN_Rise
6.2.2.2
DSI high level voltage drift
Notes
Bus receiver
DHn
SPI0 Data buffer
Adder 1
Receiver
Decision
Logic
Adder 1
Receiver
SPI1 Data buffer
Adder 2
Receiver
Decision
Logic
Adder 2
Receiver
DLn
Figure 12. DSI bus receiver block diagram
The bus receiver presents doubled redundancy for safety purposes. It consists of two receivers and two independent decision logics.
• The first decision logic checks data integrity of the first receiver (referring to the second receiver), and transfers this data to SPI0
data buffer.
• The second decision logic checks data integrity of the second receiver (referring to the first receiver), and transfers this data to SPI1
data buffer.
The only case where ER bit is not set is given by satisfying all three conditions below. Any other case sets an ER bit.
• Receiver 1 CRC is OK
• Receiver 2 CRC is OK
• Receiver 1 XOR (bitwise) receiver 2 is OK
33SA0528
NXP Semiconductors
22
VH
2*Iresp
VH-1.1V
90%
VL
tRESP_START_CRM
10%
Iq+2.1mA
tSLEW_RESP
Iq
2*Iresp
Iresp
IQ
0A
tVLD
CS0B
Can read response data
Slave N response
tCHIP
Slave N+1 response
tIPS
Figure 13. DSI bus currents timings
Table 44. Bus receiver characteristics
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
IQ_TOTAL
IRESP_TH_LOW_
DnH
IRESP_TH_HIGH_
DnH
IRESP_TH_LOW_
ADDER
IRESP_TH_HIGH_
ADDER
tRESP_START_CRM
tSLEW_RESP
tCHIP_CRM
Characteristic
Min.
Typ.
Max.
Unit
-
-
40
mA
Response current low threshold (receiver 1)
IQ_TOTAL
+5.0
-
IQ_TOTAL
+7.0
mA
Response current high threshold (receiver 1)
IQ_TOTAL
+15
-
IQ_TOTAL
+20
mA
Response current low threshold (receiver 2)
IQ_TOTAL
+5.0
-
IQ_TOTAL
+7.0
mA
Response current high threshold (receiver 2)
IQ_TOTAL
+15
-
IQ_TOTAL
+20
mA
280
295
310
μs
Total slaves quiescent current
Response start time in command and response mode
Response current slew rate
Chip time in command and response mode
21
-
45
mA/μs
4.75
5.0
5.25
μs
Notes
33SA0528
23
NXP Semiconductors
Table 44. Bus receiver characteristics (continued)
Characteristics noted under conditions 9.0 V ≤ VDSI < 9.6 V, 4.8 V < VCC5 < 5.25 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. All parameters
not mentioned in this table are compliant with those described in the DSI protocol specification, unless otherwise noted.
Symbol
Characteristic
tVLD
Data valid time
tIPS
Inter packet separation
6.2.3
Min.
Typ.
Max.
Unit
-
-
1.0
μs
3.0
-
-
chips
Notes
Block logic and operation
Buffer Check
Mode
BCK[1:0]
BCK0 | BCK1
DnCLR[7:0]
Enabled
POR
EN
Disabled
EN
DnCLR[7:0]
DPC[2:0]
Command and
Response
Mode
Send
Discovery
Pulses
PDCM_EN
Periodic Data
Collection Mode
Figure 14. DSI block main states diagram for channel n
There are three states in the DSI protocol engine’s logic for each channel: disabled, enabled and buffer check mode. In the disabled state,
all SPI data buffers are reset to their initial values and any write access to the Tx buffer is ignored. The enabled state contains two modes,
command and response mode, and periodic data collection mode. In command and response mode, the MCU can request the 33SA0528
to transceive any data (Tx/Rx buffers) or DSI discovery pulses to the DSI slaves in the bus. In periodic data collection mode, the DSI
master stores and decodes four slaves responses per channel after every broadcast read command is sent through the DSI bus, which
happens every 500 μs if in auto mode, or manually each time the DnBRC bit is set.
33SA0528
NXP Semiconductors
24
6.2.3.1
Command and response mode
Command
(Manchester encoded)
Voltage
Response
(Tri-level current moduration)
Current
Figure 15. DSI Command and response mode operating principle
In this mode, any data written to the CRM Tx/Rx data buffer registers by the MCU, via SPI0, is outputted through the DSI bus as
Manchester encoded voltage pulses, composing a command. The DSI slaves connected to the bus then receive this command and, if
applicable, send back their responses following a tri-level current modulation, as detailed in the DSI protocol specification. The response
is decoded by the DSI block and stored back to the corresponding CRM Tx/Rx Data Buffer register.
SPI Transaction
Write to
Tx buffer
SPI Tx
Read from Write to
Tx buffer Tx buffer
When TE is 0, write access
to Tx buffer is ignored.
MCU can read Rx buffer in any
cases.
SPI Rx
TE bit:
RNE bit:
Command
1
0
1
0
0
1
1
0
at least 500us
Response
Figure 16. Command and response mode behavior on TE and RNE bits
The DSI voltage command is transmitted through the DSI bus immediately after the MCU completes writing data, via SPI0, to the CRM
Tx/Rx data buffer register. This is not valid if the elapsed time from the start of the previous command is less than 500 μs. If the MCU
writes data to the CRM Tx buffer when the TE bit is set (TE=1) and 500 μs have not yet elapsed from the start of the previous command,
a new command is queued and outputted once this time is concluded. When the TE bit is cleared (TE=0), any MCU write operation to the
CRM Tx buffer are ignored. However, the MCU can read the CRM Rx Data Buffer at any time.
Received data is stored
RNE=0
RNE=1
New data arrives
Overwrite data and status
Rx Data Buffer register is read by MCU
Clear other status bits
Figure 17. Command and response mode RNE bit behavior
33SA0528
25
NXP Semiconductors
If a DSI slave response is detected by the receiver logic, the RNE bit is set (RNE=1), indicating there is new data in the buffer. When the
MCU reads the Rx data buffer register, the RNE bit clears (RNE=0). If another DSI slave response is detected with the receiver not being
empty, the Rx data buffer overwrites with the new data and the RNE bit is kept set (RNE=1).
To enter into command and response mode, the corresponding EN bit from the channel control register must be set (EN=1). If BCK[1:0]
bits and EN bit are set in the same SPI transaction, the operation on the EN bit is ignored as the BCK bits have higher priority.
There are two ways to exit this mode (note that data buffers are cleared entering into disabled mode):
• Clear the corresponding EN bit (EN=0).
• Write 0xFF to the DnCLR byte of the channel clear register in SPI0.
6.2.3.2
Discovery pulses
The 33SA0528 can send DSI discovery commands as detailed in the DSI protocol specification, for the automatic addressing of the slaves
connected to the bus (discovery mode). For this, the device must first enter command and response mode.
Command and
Response
Mode
DPC[2:0]
t
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