MC34708VMR2

Freescale Semiconductor Technical Data MC34708 Rev. 11.0, 11/2013 Power Management Integrated Circuit (PMIC) for i.MX50/53 Families 34708 The MC34708 is the Power Management Integrated Circuit (PMIC) designed specifically for use with the Freescale i.MX50 and i.MX53 families. This device is powered by SMARTMOS technology. POWER MANAGEMENT Features • Six multi-mode buck regulators for direct supply of the processor core, memory, and peripherals • Boost regulator for USB OTG support • Eight regulators with internal and external pass devices for thermal budget optimization • USB/UART/Audio switching for mini-micro USB connector • 10-bit ADC for monitoring battery and other inputs • Real time clock and crystal oscillator circuitry with coin cell backup/ charger • SPI/I2C bus for control and register interface VK SUFFIX (PB-FREE) 98ASA00312D 206 MAPBGA 8.0 X 8.0 (0.5 MM PITCH) Applications Tablets Smart Mobile Devices Portable Navigation Devices 3          ! !"# &            '%   "!   !  ! "!  ' !$   '%  '%$ &     !$  ! " #$  ! %  1 ! 2 !  %  (( (  ( (/ * + 0 , ) VM SUFFIX (PB-FREE) 98ASA00299D 206 MAPBGA 13.0 X 13.0 (0.8 MM PITCH) .  Figure 1. MC34708 Simplified Application Diagram There are no disclaimers required on the Final publication of a data sheet. © Freescale Semiconductor, Inc., 2011-2013. All rights reserved. !& & Table of Contents 1 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Format and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 5 Simplified Internal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 5.3 6 5.3.2 General PMIC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 7 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Startup Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Bias and References Block Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 7.4 7.5 7.6 7.7 Clocking and Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.2 SRTC Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.3 Coin Cell Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.2 Interrupt Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5.1 Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5.3 Power Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5.4 Buck Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5.5 Boost Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5.6 Linear Regulators (LDOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Battery Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.7.1 7.8 Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.7.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.7.3 Dedicated Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.7.4 Touch Screen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.7.5 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Auxiliary Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.8.1 General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.8.2 PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.8.3 General Purpose LED Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.8.4 Mini/Micro USB Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 2 7.9 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.9.1 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.9.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.9.3 SPI/I2C Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.10 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8 Register Set structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.10.2 Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.10.3 SPI/I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.10.4 SPI Register’s Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.2 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.3 8.4 9 7.10.1 MC34708 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.1 General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.2 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.3 General Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.4 Parallel Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.5 Differential Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.3.6 Switching Regulator Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.4.1 Rating Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.4.2 Estimation of Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.1 206-pin MAPBGA (8 x 8), 0.5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.2 206-pin MAPBGA (13 x 13), 0.8 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 10 Reference Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 MC34708 3 Analog Integrated Circuit Device Data Freescale Semiconductor Orderable Parts 1 Orderable Parts This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. Table 1. Orderable Part Variations Part Number (1) Temperature (TA) MC34708VK MC34708VM -40 to 85 °C Package 206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm pitch 206 MAPBGA - 13 x 13 mm - 0.8 mm pitch Notes 1. To Order parts in Tape & Reel, add the R2 suffix to the part number. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 4 Part Identification 2 Part Identification This section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 Description Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received. 2.2 Format and Examples Part numbers for a given device have the following format, followed by a device example: Table 2 - Part Numbering - Analog: MC tt xxx r v PP RR - MC34708VKR2 2.3 Fields These tables list the possible values for each field in the part number (not all combinations are valid). Table 2: Part Numbering - Analog FIELD DESCRIPTION VALUES MC Product Category • MC- Qualified Standard • PC- Prototype Device tt Temperature Range • 34 = -40 °C to  105 °C xxx Product Number • Assigned by Marketing r Revision • (default blank) v Variation • (default blank) PP Package Identifier RR Tape and Reel Indicator • Varies by package • R2 = 13 inch reel hub size MC34708 5 Analog Integrated Circuit Device Data Freescale Semiconductor Input/Battery Monitoring O/P Drive General Purpose LED Drivers SW1 Dual Phase GP 2000 mA Buck LICELL, UID, Die Temp, GPO4 GNDADC ADIN9 Voltage / Current Sensing & Translation 10 Bit GP ADC O/P Drive SW2 LP ` 1000 mA Buck ADIN13/TSX2 ADIN15/TSY2 Touch Screen Interface Die Temp & Thermal Warning Detection TSREF BPTHERM To Interrupt Section SW3 INT MEM 500 mA Buck NTCREF BATTISNSCCP SW4 Dual Phase DDR 1000 mA Buck BATTISNSCCN CFP Package Pin Legend CFN Input Pin CS CLK MOSI MISO GNDSPI Shift Register SPI Interface + Muxed I2C Optional Interface SPI SW5 I/O 1000 mA Buck To Enables & Control SWBST 380 mA Boost MC34708 VCORE VDDLP SW3IN SW3LX GNDSW3 SW3FB O/P Drive SW4AIN SW4ALX GNDSW4A SW4AFB O/P Drive SW4BIN SW4BLX GNDSW4B SW4BFB O/P Drive SW5IN SW5LX GNDSW5 SW5FB O/P Drive SWBSTIN SWBSTLX SWBSTFB Shift Register VALWAYS VCOREDIG O/P Drive Bi-directional Pin Registers SW2IN SW2LX GNDSW2 SW2FB SW2PGD SW4CFG Output Pin SPIVCC SW1BLX GNDSW1B SW1PWGD A/D Control ADIN12/TSX1 ADIN14/TSY1 O/P Drive DVS CONTROL MUX SW1IN SW1ALX GNDSW1A SW1FB SW1CFG SW1VSSSNS A/D Result ADIN10 ADIN11 GNDCHRG GNDACHRG CHRGLEDG LEDVDD CHRGLEDR PRETMR VAUX GAUX AUXVIN GOTG CHRGLX BP BPSNS BATTISNSN BATT VBUSVIN Simplified Internal Diagram GBAT 3.1 BATTISNSP ITRIC Internal Block Diagram CHRGFB 3 TRICKLESEL Internal Block Diagram Reference Generation GNDSWBST VINREFDDR SPI Control VCOREREF GNDCORE GNDREF VHALF VREFDDR 10mA SPKR SPKL MIC VREFDDR VPLL 50 mA Pass FET VUSB2 350mA Pass FET VINPLL VPLL VUSB2DRV TXD RXD VBUS/ID Detectors, Host Auto detection DPLUS DMINUS VDAC 250mA UART Switches Audio Switches SPI Connector Interface DP DM GNDUSB UID To Trimmed Circuits Trim-In-Package Control Logic VUSB2 VDACDRV VDAC VGEN1 250mA Pass FET VINGEN1 VGEN1 VBUS 32 KHz Buffers GNDREG1 GNDREG2 PWM Outputs GNDREF1 GNDREF2 PWM2 VSRTC CLK32KVCC CLK32KMCU CLK32K VSRTC RESETB SDWNB INT WDI RESETBMCU GLBRST PWRON2 STANDBY PUMS1 PWRON1 PUMS3 PUMS2 PUMS4 PUMS5 ICTEST XTAL2 VGEN2 LDOVDD Best of Supply GPIO Control Core Control Logic, Timers, & Interrupts Digital Core GNDCTRL XTAL1 SUBSLDO SUBSANA3 SUBSANA2 SUBSPWR2 SUBSANA1 SUBSREF GNDRTC 32 KHz Crystal Osc Li Cell Charger Pass FET PWM1 Enables & Control GNDGPIO Interrupt Inputs BP SPI Result Registers LCELL SUBSPWR1 VGEN2 250mA LICELL RTC + Calibration 32 KHz Internal Osc Switch SUBSGND VGEN2DRV Switchers GPIOVDD BP LICELL PLL Monitor Timer VUSB Regulator VUSB Control Logic GPIOLV4 VINUSB GPIOLV3 Startup Sequencer Decode Trim? PUMSx GPIOLV1 GPIOLV2 OVP Figure 2. Simplified Internal Block Diagram MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 6 Pin Connections 4 Pin Connections 4.1 Pinout Diagram 1 A 2 3 4 5 6 7 8 9 10 11 12 13 14 TRICKLESEL GNDACHRG BATT CFP BP VBUSVIN CHRGLX GNDCHRG LEDVDD LICELL PWM1 GPIOVDD PUMS4 15 B AUXVIN AUXVIN PRETMR BPTHERM CFN GBAT VBUSVIN CHRGLX GNDCHRG CHRGLEDG GPIOLV1 GNDGPIO PUMS3 PUMS2 SUBSANA2 C AUXVIN AUXVIN SUBSANA3 NTCREF CHRGFB BPSNS VBUSVIN CHRGLX GNDCHRG PWM2 GPIOLV3 PUMS1 GNDSW2 GNDSW2 GNDSW2 D VAUX GOTG GAUX SDWNB VBUSVIN CHRGLX GNDCHRG ICTEST GPIOLV2 PUMS5 SW2LX SW2LX SW2LX E RESETB GNDCTRL PWRON2 INT BATTISNSCCN BATTISNSP ITRIC SUBSPWR1 CHRGLEDR GPIOLV0 SW2FB SW2IN SW2IN SW2IN F MISO GNDSPI MOSI SPIVCC RESETBMCU BATTISNSCCP BATTISNSN SUBSPWR1 SUBSPWR1 GNDREF2 SWBSTIN SWBSTIN GNDSW3 GNDSW3 G CLK CS VINUSB RXD TXD GLBRST PWRON1 SUBSPWR1 SW2PWGD SW3FB GNDSWBST GNDSWBST SW3LX SW3LX H VBUS VUSB UID VALWAYS SUBSREF SUBSPWR1 MIC SUBSPWR1 SUBSPWR1 CLK32KMCU CLK32KVCC SWBSTFB CLK32K SW3IN SW3IN J DM SPKR VCOREDIG VDDLP STANDBY TSY2 TSY1 SUBSPWR1 SUBSPWR1 VDACDRV VINPLL VPLL VSRTC SWBSTLX SWBSTLX K DP SPKL VCORE TSX1 ADIN10 ADIN9 SUBSPWR1 SUBSPWR1 VHALF VGEN2 VDAC GNDREG1 GNDRTC SUBSLDO L DPLUS GNDCORE GNDUSB WDI ADIN11 SUBSPWR1 GNDREF1 SW1VSSSNS SW1CFG VINREFDDR GNDREG2 VUSB2 LDOVDD XTAL2 M DMINUS GNDREF SW4CFG SW5FB SW1FB SW1PWGD VGEN1 VUSB2DRV XTAL1 N VCOREREF GNDADC GNDADC GNDADC P TSREF GNDSW4A GNDADC GNDADC SW4BFB SW4ALX SW4AIN SW4BIN SW4BLX R TSX2 SW5IN SW5LX GNDSW5 SW4AFB SW5IN SW5LX GNDSW5 GNDSW4B SW5IN SW5LX GNDSW5 SW1IN SW1IN SUBSANA1 VINGEN1 VGEN2DRV GNDSW1A SW1ALX SW1IN SW1BLX GNDSW1B VREFDDR GNDSW1A SW1ALX SW1IN SW1BLX GNDSW1B Legend LDOs Switching Regulators Control Logic Misc RTC Ground USB ADC SPI/I2C No Connect No Ball Figure 3. Top View Ballmap MC34708 7 Analog Integrated Circuit Device Data Freescale Semiconductor Pin Connections 4.2 Pin Definitions Table 3. MC34708 Pin Definitions Pin Number Pin Name Pin Function Definition Charger (Function no longer supported on MC34708) A7, B7, C7, D7 VBUSVIN NC Charger Not supported. No Connect B1, B2, C1, C2 AUXVIN NC Charger Not supported. No Connect VAUX NC Charger Not supported. No Connect A8, B8, C8, D8 CHRGLX NC Charger Not supported. No Connect C5 CHRGFB I GOTG NC Charger Not supported. No Connect GAUX NC Charger Not supported. No Connect BPSNS I BP sense point BP I 1. Application supply point 2. Input supply to the IC core circuitry 3. Application supply voltage sense GBAT O Connect to GND ITRIC NC BATTISNSP I Battery current sensing point.(Optional) If required, connect a 20 m sense resistor between BATTISNSP and BATTISNSN BATTISNSN I Battery current sensing point (Optional) If required, connect a 20 m sense resistor between BATTISNSP and BATTISNSN BATT I 1. Battery positive terminal 2. Battery current sensing point 2 3. Battery supply voltage sense BATTISNSCCP NC Coulomb counter Not supported. No Connect BATTISNSCCN NC Coulomb counter Not supported. No Connect A2 TRICKLESEL I Connect to VCOREDIG B3 PRETMR I Connect to Ground CFP NC Coulomb Counter Not supported. No Connect CFN NC Coulomb Counter Not supported. No Connect A10 LEDVDD O LED supply E10 CHRGLEDR I Red LED driver D1 D2 D3 C6 A6 B6 E8 E7 F7 A4 F6 E6 A5 B5 Connect to BATT pin Charger Not supported. No Connect MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 8 Pin Connections Table 3. MC34708 Pin Definitions (continued) Pin Number Pin Name Pin Function B10 CHRGLEDG I A3 GNDACHRG GND Analog ground A9, B9, C9, D9 GNDCHRG GND Ground NTCREF NC BPTHERM I Connect to Ground K3 VCORE O Regulated supply for the IC analog core circuitry J3 VCOREDIG O Regulated supply for the IC digital core circuitry H4 VALWAYS O Always on supply for internal core circuitry N1 VCOREREF O Main bandgap reference J4 VDDLP O VDDLP reference L2 GNDCORE GND Ground for the IC core circuitry M2 GNDREF GND Ground reference for the IC core circuitry C4 B4 Definition Green LED driver Charger Not supported. No Connect IC Core Switching Regulators N11, N12, P12, R12 SW1IN I SW1 input P11, R11 SW1ALX O SW1A switch node connection M10 SW1FB I SW1 feedback P10, R10 GNDSW1A GND Ground for SW1A L9 SW1VSSSNS GND SW1 sense M11 SW1PWGD O Powergood signal for SW1 P13, R13 SW1BLX O SW1B switch node connection P14, R14 GNDSW1B GND L10 SW1CFG I SW1A/B mode configuration E13, E14, E15 SW2IN I SW2 input D13, D14, D15 SW2LX O SW2 switch node connection E12 SW2FB I SW2 feedback C13, C14, C15 GNDSW2 GND G10 SW2PWGD O Powergood signal for SW2 H14, H15 SW3IN I SW3 input G14, G15 SW3LX O SW3 switch node connection G11 SW3FB I SW3 feedback F14, F15 GNDSW3 GND Ground for SW3 F11 GNDREF2 GND Ground reference for switching regulators R3 SW4AIN I Ground for SW1B Ground for SW2 SW4A input MC34708 9 Analog Integrated Circuit Device Data Freescale Semiconductor Pin Connections Table 3. MC34708 Pin Definitions (continued) Pin Number Pin Name Pin Function R2 SW4ALX O SW4A switch node connection P6 SW4AFB I SW4A feedback P2 GNDSW4A GND R4 SW4BIN I SW4B input R5 SW4BLX O SW4B switch node connection P5 SW4BFB I SW4B feedback R6 GNDSW4B GND M6 SW4CFG I SW4A/B mode configuration N7, P7, R7 SW5IN I SW5 input N8, P8, R8 SW5LX O SW5 output M7 SW5FB I SW5 feedback N9, P9, R9 GNDSW5 GND Ground for SW5 L8 GNDREF1 GND Ground reference for Switching Regulators F12, F13 SWBSTIN I Boost Regulator BP supply J14, J15 SWBSTLX O SWBST switch node connection H12 SWBSTFB I Boost Regulator feedback G12, G13 GNDSWBST GND Definition Ground for SW4A Ground for SW4B Ground for boost Regulator LDO Regulators L11 VINREFDDR I VREFDDR input supply P15 VREFDDR O VREFDDR regulator output K10 VHALF O Half supply reference for VREFDDR J11 VINPLL I VPLL input supply J12 VPLL O VPLL regulator output J10 VDACDRV O Drive output for VDAC regulator using external PNP device K12 VDAC O VDAC regulator output LDOVDD I Supply pin for VUSB2, VDAC, and VGEN2. Must always be connected to the same supply as the PNP emitter. Recommended to use BP as the LDOVDD supply. See Figure 38 for a typical connection diagram. I 1. VUSB2 input using internal PMOS FET O 2. Drive output for VUSB2 regulator using external PNP device L14 M14 VUSB2DRV L13 VUSB2 O VUSB2 regulator output N14 VINGEN1 I VGEN1 input supply M13 VGEN1 O VGEN1 regulator output I 1. VGEN2 input using internal PMOS FET O 2. Drive output for VGEN2 regulator using external PNP device N15 VGEN2DRV K11 VGEN2 O VGEN2 regulator output J13 VSRTC O Output regulator for SRTC module on processor K13 GNDREG1 GND Ground for regulators 1 MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 10 Pin Connections Table 3. MC34708 Pin Definitions (continued) Pin Number Pin Name Pin Function L12 GNDREG2 GND A13 GPIOVDD I E11 GPIOLV0 I/O General purpose input/output 0 B11 GPIOLV1 I/O General purpose input/output 1 D11 GPIOLV2 I/O General purpose input/output 2 C11 GPIOLV3 I/O General purpose input/output 3 A12 PWM1 O PWM output 1 C10 PWM2 O PWM output 2 B12 GNDGPIO - GPIO ground LICELL I/O M15 XTAL1 I 32.768 kHz Oscillator crystal connection 1 L15 XTAL2 I 32.768 kHz Oscillator crystal connection 2 K14 GNDRTC GND H11 CLK32KVCC I Supply voltage for 32 kHz buffer H13 CLK32K O 32 kHz Clock output for peripherals H10 CLK32KMCU O 32 kHz Clock output for processor E1 RESETB O Reset output for peripherals F5 RESETBMCU O Reset output for processor L4 WDI I Watchdog input J5 STANDBY I Standby input signal from processor E4 INT O Interrupt to processor G8 PWRON1 I Power on/off button connection 1 E3 PWRON2 I Power on/off button connection 2 G7 GLBRST I Global Reset C12 PUMS1 I Power up mode supply setting 1 B14 PUMS2 I Power up mode supply setting 2 B13 PUMS3 I Power up mode supply setting 3 A14 PUMS4 I Power up mode supply setting 4 D12 PUMS5 I Power up mode supply setting 5 D10 ICTEST I Connect to ground for normal mode operation. E2 GNDCTRL GND F4 SPIVCC I Supply for SPI bus G2 CS I Primary SPI select input G1 CLK I Primary SPI clock input F3 MOSI I Primary SPI write input F1 MISO O Primary SPI read output Definition Ground for regulators 2 Supply for GPIO Control Logic A11 1. Coin cell supply input 2. Coin cell charger output Ground for the RTC block Ground for control logic MC34708 11 Analog Integrated Circuit Device Data Freescale Semiconductor Pin Connections Table 3. MC34708 Pin Definitions (continued) Pin Number Pin Name Pin Function D4 SDWNB O F2 GNDSPI GND H3 UID I/O L3 GNDUSB GND USB Ground K1 DP I/O USB Data + J1 DM I/O USB Data – L1 DPLUS I/O Processor D+ M1 DMINUS I/O Processor D- G4 RXD O UART Receive G5 TXD I/O UART Transmit H7 MIC O Mic output J2 SPKR I Speaker right K2 SPKL I Speaker left H1 VBUS I/O USB transceiver cable interface VBUS & OTG supply output H2 VUSB O USB transceiver regulator output G3 VINUSB I Input option for VUSB; tie to SWBST at top level. K7 ADIN9 I ADC generic input channel 9 K6 ADIN10 I ADC generic input channel 10, L6 ADIN11 I ADC generic input channel 11 K4 TSX1/ADIN12 I Touch Screen Interface X1 or ADC generic input channel 12 L5 TSX2/ADIN13 I Touch Screen Interface X2 or ADC generic input channel 13 J7 TSY1/ADIN14 I Touch Screen Interface Y1 or ADC generic input channel 14 J6 TSY2/ADIN15 I Touch Screen Interface Y2 or ADC generic input channel 15 P1 TSREF O Touch Screen Reference N2, N3, N4, P3, P4 GNDADC GND Ground for ADC USB Definition Indication of imminent system shutdown Ground for SPI interface (2) USB OTG transceiver cable ID A to D Converter Thermal Grounds H5 SUBSREF GND Substrate ground connection for reference circuitry E9, F8,F9, L7, G9, H6, H8, H9, J8, J9, K8, K9 SUBSPWR1 GND Substrate ground connection for power devices SW1, SW4, SW5 K15 SUBSLDO GND Substrate ground connection for all LDOs N13 SUBSANA1 GND Substrate ground connection for analog circuitry of SW1, SW4, SW5 B15 SUBSANA2 GND Substrate ground connection for analog circuitry of SW2, SW3, SWBST MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 12 Pin Connections Table 3. MC34708 Pin Definitions (continued) Pin Number Pin Name Pin Function C3 SUBSANA3 GND Definition Substrate ground connection for analog circuitry Notes 2. In applications without USB support, leave all USB pins unconnected. MC34708 13 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics 5 General Product Characteristics 5.1 Maximum Ratings Table 4. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (Rating) Max. Unit Notes ELECTRICAL RATINGS VBATT, VBP, VLICELL Input Supply Pins V • BATT, BP, BPSNS 4.8 • LICELL 4.8 Input Sense Pins V • CHRGFB 7.5 • BATTISNSP, BATTISNSN 5.5 LED Drivers Pins • CHRGLEDR, CHRGLEDG V 7.5 IC Core Reference V • VCOREREF 1.5 • VCOREDIG, VDDLP 1.65 • VCORE 3.6 • VALWAYS 7.5 Switching Regulators Pins V • SWxIN, SWxLX, SWBSTFB 5.5 • SWxFB, SWxPWGD, SWxCFG 3.6 • SWBSTLX 7.5 LDO Regulator Pins V • VREFDDR, VHALF 1.5 • VPLL, VGEN1, VINGEN1, VSRTC 2.5 • VINREFDDR,VDAC, VUSB2, VGEN2, 3.6 • VINPLL, VDACDRV, VUSB2DRV, VGEN2DRV 4.8 • LDOVDD 5.5 GPIO Pins • GPIOVDD, GPIOLVx, PWMx V 2.5 Control Logic Pins V • ICTEST 1.8 • XTAL1, XTAL2 2.5 • CLK32KVCC, CLK32K, CLK32KMCU, WDI, STANDBY,INT, PWRON1, PWRON2, GLBRST, PUMSx, SPIVCC, CS, CLK, MOSI, MISO, SDWNB 3.6 Mini/Micro USB Interface Pins V • VBUS input sense pin 20 • VUSB 3.6 • UID, DP, DM, DPLUS, DMINUS, RXD, TXD, MIC, SPKR, SPKL, VINUSB 5.5 ADC Interface Pins • ADINx, TSX1/ADIN12, TSX2/ADIN13, TSY1/ADIN14, TSY2/ADIN15, TSREF V 4.8 MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 14 General Product Characteristics Table 4. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol VESD Description (Rating) Max. Unit Notes V ESD Ratings • Human Body Model All pins 2000 (3) • Charge Device Model All pins 500 (3) • Air Gap Discharge Model for UID, VBUS, DP, and DM pins 15000 (4) • Human Body Model (HBM) for UID, VBUS, DP, and DM pins 8000 (4) Notes 3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 4. Need external ESD protection diode array to meet IEC1000-4-2 15000 V Air Gap discharge and 8000 V HBM requirements. (CZAP = 150 pF, RZAP = 330 ohm). 5.2 Thermal Characteristics Table 5. Thermal Ratings Symbol Description (Rating) Min. Max. Unit Notes THERMAL RATINGS TA Ambient Operating Temperature Range -40 85 °C TJ Operating Junction Temperature Range -40 125 °C Storage Temperature Range -65 150 °C - Note 7 °C (6), (7) - 93 °C/W (8), (9) - 53 °C/W (8), (10) - 80 °C/W (8), (10) - 49 °C/W (8), (10) TST TPPRT Peak Package Reflow Temperature During Reflow (5) 8.0 X 8.0 MM, THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS RθJA Junction to Ambient Natural Convection • Single layer board (1s) RθJMA Junction to Ambient Natural Convection • Four layer board (2s2p) RθJMA Junction to Ambient (@200 ft/min.) • Single layer board (1s) RθJMA Junction to Ambient (@200 ft/min.) • Four layer board (2s2p) RθJB Junction to Board - 34 °C/W (11) RθJC Junction to Case - 25 °C/W (12) θJT Junction to Package Top - 3.0 °C/W (13) - 57 °C/W (8), (9) - 36 °C/W (8), (9), (10) • Natural Convection 13 X 13 MM, THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS RθJA Junction to Ambient Natural Convection • Single layer board (1s) RθJMA Junction to Ambient Natural Convection • Four layer board (2s2p) MC34708 15 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics Table 5. Thermal Ratings (continued) Symbol RθJMA Description (Rating) Junction to Ambient (@200 ft/min.) Min. Max. Unit Notes - 48 °C/W (8), (10) - 32 °C/W (8), (10) • Single layer board (1s) RθJMA Junction to Ambient (@200 ft/min.) • Four layer board (2s2p) RθJB Junction to Board - 22 °C/W (11) RθJC Junction to Case - 15 °C/W (12) θJT Junction to Package Top - 3.0 °C/W (13) • Natural Convection Notes 5. Do not operate above 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 8. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 9. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 10. Per JEDEC JESD51-6 with the board horizontal. 11. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 12. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 13. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 16 General Product Characteristics 5.2.1 Power Dissipation During operation, the temperature of the die should not exceed the maximum junction temperature. To optimize the thermal management scheme and avoid overheating, the MC34708 PMIC provides a thermal management system. The thermal protection is based on a circuit with a voltage output proportional to the absolute temperature.This voltage can be read out via the ADC for specific temperature readouts, see Channel 3 Die Temperature. The ADEN SPI bit must be set = 1 to enable the comparators for the thermal monitoring (THERM110, THERM120, THERM125, THERM130, and thermal shutdown). With ADEN = 0 the thermal monitors and thermal shutdown are disabled. Interrupts THERM110, THERM120, THERM125, and THERM130 will be generated when respectively crossing in either direction the thresholds specified in Table 6. The temperature range can be determined by reading the THERMxxxS bits. Thermal protection is integrated to power off the MC34708 PMIC in case of over dissipation. This thermal protection will act above the maximum junction temperature to avoid any unwanted power downs. The protection is debounced for 8.0 ms in order to suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism and therefore the application design should be dimensioned such that this protection is not tripped under normal conditions. The temperature thresholds and the sense bit assignment are listed in Table 6 . Table 6. Thermal Protection Thresholds Parameter Min Typ Max Units Thermal 110 °C threshold (THERM110) 105 110 115 °C Thermal 120 °C threshold (THERM120) 115 120 125 °C Thermal 125 °C threshold (THERM125) 120 125 130 °C Thermal 130 °C threshold (THERM130) 125 130 135 °C Thermal warning hysteresis 2.0 - 4.0 °C Thermal protection threshold 130 140 150 °C Notes (14) Notes 14. Equivalent to approx. 30 mW min, 60 mW max The THERM1xx thresholds are debounced by the SPI bits DIE_TEMP_DB[1:0], which are programmable from 100 s to 4.0 ms (4.0 ms by default), see Table 7. When the die temperature crosses these thresholds, the corresponding sense bit will change, and an interrupt will be generated to notify the software the hardware is reaching its thermal limit. Table 7. Die Temp Debounce Settings DIE_TEMP_DB [1:0] Time Units 00 0.100 ms 01 1.0 ms 10 2.5 ms 11 (default) 4.0 ms MC34708 17 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics 5.3 Electrical Characteristics 5.3.1 Recommended Operating Conditions Table 8. Recommended Operating Conditions Symbol Description (Rating) VBP VLICELL TA 5.3.2 Min. Max. Unit Main Input Supply 3.0 4.5 V LICELL Backup Battery 1.8 3.6 V Ambient Temperature -40 85 °C Notes General PMIC Specifications Table 9. Pin Logic Thresholds Pin Name Internal Termination (19) PWRON1, PWRON2, GLBRST Pull-up STANDBY, WDI Weak Pull-down CLK32K CLK32KMCU CMOS CMOS RESETB, Open Drain RESETBMCU, SDWNB, SW1PWGD, SW2PWGD CMOS GPIOLV1,2,3,4 Open Drain PWM1, PWM2 CMOS CLK, MOSI CS Weak Pull-down CS, MOSI (at Booting Weak Pull-down for SPI / I2C decoding) on CS Load Condition Min Max (22) Unit Notes Input Low 47 kOhm 0.0 0.3 V (16) Input High 1.0 MOhm 1.0 VCOREDIG V (16) Input Low - 0.0 0.3 V (21) Input High - 0.9 3.6 V (21) Output Low -100 A 0.0 0.2 V Output High 100 A CLK32KVCC - 0.2 CLK32KVCC V Output Low -100 A 0.0 0.2 V Output High 100 A VSRTC - 0.2 VSRTC V Output Low -2.0 mA 0.0 0.4 V (20) Open Drain - 3.6 V (20) Input Low - 0.0 0.3 * GPIOVDD V Input High - 0.7 * GPIOVDD GPIOVDD + 0.3 V Output Low - 0.0 0.2 V Output High - GPIOVDD - 0.2 GPIOVDD V Output Low -2.0 mA 0 0.4 V Output High Open Drain - GPIOVDD + 0.3 V Output Low - 0.0 0.2 V Output High - GPIOVDD - 0.2 GPIOVDD V Input Low - 0.0 0.3 * SPIVCC V (15) Input High - 0.7 * SPIVCC SPIVCC + 0.3 V (15) Input Low - 0.0 0.4 V (15) Input High - 1.1 SPIVCC + 0.3 V (15) Input Low - 0.0 0.3 * VCOREDIG V (15) (23) V (15) (23) Parameter Output High Input High - 0.7 * VCOREDIG VCOREDIG , , MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 18 General Product Characteristics Table 9. Pin Logic Thresholds Pin Name MISO, INT PUMS1,2,3,4,5 ICTEST SW1CFG, SW4CFG Notes 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. Internal Termination (19) Load Condition Min Max (22) Unit Output Low -100 A 0.0 0.2 V Output High 100 A SPIVCC - 0.2 SPIVCC V Input Low PUMSxS = 0 - 0.0 0.3 V (17) Input High PUMSxS = 1 - 1.0 VCOREDIG V (17) Input Low - 0.0 0.3 V (18) Input High - 1.1 1.7 V (18) Input Low - 0.0 0.3 V Input Mid - 1.3 2.0 V Input High - 2.5 3.1 V Parameter CMOS Notes MISO (15) (24) MISO (15) (24) SPIVCC is typically connected to the output of buck regulator SW5 and set to 1.800 V Input has internal pull-up to VCOREDIG equivalent to 200 kOhm Input state is latched in first phase of cold start, refer to Serial Interfaces for a description of the PUMS configuration Input state is not latched A weak pull-down represents a nominal internal pull-down of 100 nA unless otherwise noted RESETB, RESETBMCU, SDWNB, SW1PWGD, SW2PWGD have open drain outputs, external pull-ups are required SPIVCC needs to remain enabled for proper detection of WDI High to avoid involuntary shutdown The maximum should never exceed the maximum rating of the pin as given in Pin Connections The weak pull-down on CS is disabled if a VIH is detected at startup to avoid extra consumption in I2C mode The output drive strength is programmable MC34708 19 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics 5.3.3 Current Consumption The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary table follows for standard use cases. Table 10. Current Consumption Summary (27) Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Mode Description All blocks disabled, no main battery attached, coin cell is attached to LICELL  (at 25 °C only) RTC / Power cut Typ Max Unit 4.0 8.0 A 20 55 A 340 424 A 480 561 A Notes • RTC Logic • VSRTC • 32 kHz Oscillator • Clk32KMCU buffer active(10 pF load) All blocks disabled, main battery attached • Digital Core OFF (good battery) • RTC Logic • VSRTC • 32 kHz Oscillator • CLK32KMCU buffer active (10 pF load) Low Power Mode (Standby pin asserted and ON_STBY_LP=1) • Digital Core • RTC Logic • VCORE Module • VSRTC LPM ON Standby • CLK32KMCU/CLK32K active (10 pF load) • 32 kHz Oscillator • IREF • SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM (26),(30) • VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC in low power mode (25),(28) • Mini-USB • Digital Core • RTC Logic • VCORE module • VSRTC • CLK32KMCU/CLK32K active (10 pF load) • 32 kHz Oscillator ON Standby • Digital • IREF • SW1, SW2, SW3 SW4A, SW4B, SW5 in PFM (26),(30) • VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on  in low power mode (26),(28) • Mini-USB • PLL (for mini USB) MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 20 General Product Characteristics Table 10. Current Consumption Summary (27) Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Typical use case 1600 3000 A • Digital Core • RTC Logic • VCORE Module • VSRTC CLK32KMCU/CLK32K active (10 pf) • 32 kHz Oscillator • IREF ON • SW1, SW2, SW3 SW4A, SW4B, SW5 in Apskip SWBST (26),(29),(30) • VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on  in low power mode (25),(28) • Digital • PLL • Mini-USB Notes 25. 26. 27. 28. 29. 30. Equivalent to approx. 30 mW min, 60 mW max Current in RTC Mode is from LICELL=2.5 V; in all other modes from BP = 3.6 V. External loads are not included (1) VUSB2, VGEN2 external pass PNPs SWBST in auto mode SW4A output 2.5 V MC34708 21 Analog Integrated Circuit Device Data Freescale Semiconductor General Description 6 General Description 6.1 Features Power Generation • Six Buck Switching Regulators • Two Single/Dual Phase Buck Regulators • Three Single Phase Buck Regulators • PFM/Auto Pulse Skip/PWM Operation Mode • Dynamic Voltage Scaling • 5 V Boost Regulator • USB On-the-go Support • Eight LDO Regulators • Two with Selectable Internal or External Pass Devices • Five with Embedded Pass Devices • One with an External PNP Device Analog to Digital Converter • Seven General Purpose Channels • Internal Dedicated Channels • Resistive Touchscreen Interface Auxiliary Circuits • Mini/Micro USB Switch • Bidirectional Audio/Data/UART • Accessory Identification Circuit • General Purpose I/Os • PWM Outputs • Two general purpose LED Drivers. Clocking and Oscillators • Real Time clock • Time and day Counters • Time of day Alarm • 32.768 kHz Crystal Oscillator • Coin Cell Battery Backup and Charger Serial Interface • SPI • I2C MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 22 General Description 6.2 Block Diagram SIX BUCK REGULATORS Processor Core Split Power Domains DDR Memory I/O EIGHT LDO REGULATORS Peripherals 10-BIT ADC CORE General Purpose Resistive Touch Screen Interface 32.768 kHz CRYSTAL OSCILLATOR Real Time Clock SRTC Support with Coin Cell Charger 5 V BOOST REGULATOR USB On The Go Supply MC34708 BIAS & REFERENCES Trimmed Bandgap CONTROL INTERFACE SPI/I2C MINI/MICRO USB INTERFACE USB/UART/Audio Auto Accessory Detect GENERAL PURPOSE I/O & PWM OUTPUTS Dual LED Indicator POWER CONTROL LOGIC State Machine Figure 4. Functional Block Diagram 6.3 Functional Description The MC34708 Power Management Integrated Circuit (PMIC) represents a complete system power solution in a single package. Designed specifically for use with the Freescale i.MX50/53 families. The MC34708 integrates six multi-mode buck regulators and eight LDO regulators for direct supply of the processor core, memory and peripherals. The USB switch enables the use of a single, mini or micro USB connector for USB, UART and audio connections, switching the relevant signals to the connector depending on the type of device connected. In addition, the MC34708 also integrates a real time clock, coin cell charger, a 13-channel 10-bit ADC, 5 V USB Boost regulator, two PWM outputs, touch-screen interface, status LED drivers and four GPIOs. MC34708 23 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7 Functional Block Description 7.1 Startup Requirements When power is applied, there is an initial delay of 8.0 ms during which the core circuitry is enabled. The switching and linear regulators are then sequentially enabled in time slot steps of 2.0 ms. This allows the PMIC to limit the inrush current. The outputs of the switching regulators not enabled are discharged with weak pull-downs on the output to ensure a proper powerup sequence. Any undervoltage detection at BP is masked while the power-up sequencer is running. When the switching regulators are enabled, they will start in PWM mode. After 3.0 ms, the switching regulators will transition to the mode programmed in the SPI register map. The Power-up mode select pins PUMSx (x = 1, 2, 3, 4, and 5) are used to configure the start-up characteristics of the regulators. Supply enabling and output level options are selected by hardwiring the PUMSx pins. It is recommended to minimize the load during system boot-up by supplying only the essential voltage domains. This allows the start-up transients to be minimized after which the rest of the system power tree can be brought up by software. The PUMSx pins also allow optimization of the supply sequence and default values. Software code can load the required programmable options without any change to hardware. The state of the PUMSx pins are latched before any of the regulators are enabled, with the exception of VCORE. PUMSx options and start-up configurations are robust to a PCUT event, whether occurring during normal operation or during the 8.0 ms of presequencer initialization, i.e. the system will not end up in an unexpected / undesirable consumption state. Table 11 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled. Table 11. Power Up Defaults i.MX Reserved 53 LPM 53 DDR2 53 DDR3 53 LVDDR3 53 LVDDR2 50 MDDR 50 50 50 50 50 LPDDR2 LPDDR2 MDDR LPDDR2 MDDR PUMS[4:1] 0000-0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PUMS5=0 VUSB2 VGEN2 Reserved Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP PUMS5=1 VUSB2 VGEN2 Reserved Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS SW1A (VDDGP) Reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 SW1B (VDDGP) Reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 SW2(31) (VCC) Reserved 1.225 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 SW3(31) (VDDA) Reserved 1.2 1.3 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 SW4A(31) (DDR/SYS) Reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 3.15 3.15 3.15 3.15 SW4B(31) (DDR/SYS) Reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 1.2 1.8 1.2 1.8 SW5(31) (I/O) Reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 SWBST Reserved Off Off Off Off Off Off Off Off Off Off Off VUSB(32) Reserved 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 VUSB2 Reserved 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 24 Functional Block Description Table 11. Power Up Defaults i.MX Reserved 53 LPM 53 DDR2 53 DDR3 53 LVDDR3 53 LVDDR2 50 MDDR 50 50 50 50 50 LPDDR2 LPDDR2 MDDR LPDDR2 MDDR VSRTC Reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 VPLL Reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 VREFDDR Reserved On On On On On On On On On On On VDAC Reserved 2.775 2.775 2.775 2.775 2.775 2.5 2.5 2.5 2.5 2.5 2.5 VGEN1 Reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 VGEN2 Reserved 2.5 2.5 2.5 2.5 2.5 3.1 3.1 3.1 3.1 2.5 2.5 Notes 31. The SWx node are activated in APS mode when enabled by the startup sequencer. 32. VUSB regulator is only enabled if 5.0 V is present on VBUS. By default VUSB will be supplied by VBUS. SWBST = 5.0 V powers up as does VUSB, regardless of 5.0 V present on UVBUS. By default VUSB is supplied by SWBST. The power up sequence is shown in Tables 12 and 13. VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer startup. Table 12. Power Up Sequence i.MX53 Tap x 2.0 ms PUMS [4:1] = [0101,0110,0111,1000,1001] (i.MX53) 0 SW2 (VCC) 1 VPLL (NVCC_CKIH = 1.8 V) 2 VGEN2 (VDD_REG= 2.5 V, external PNP 3 SW3 (VDDA) 4 SW1A/B (VDDGP) 5 SW4A/B, VREFDDR (DDR/SYS) 6 7 SW5 (I/O), VGEN1 8 VUSB (33), VUSB2 9 VDAC Notes: 33. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By default VUSB will be supplied by the VBUS pin. MC34708 25 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 13. Power Up Sequence i.MX50 Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53) 0 SW2 1 SW3 2 SW1A/B 3 VDAC 4 SW4A/B, VREFDDR 5 SW5 6 VGEN2, VUSB2 7 VPLL 8 VGEN1 9 VUSB (34) Notes: 34. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By default VUSB will be supplied by the VBUS pin. 7.2 Bias and References Block Description and Application Information All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on the performance of VCORE and the bandgap. No external DC loading is allowed on VCORE, VCOREDIG, and REFCORE. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. Table 14 shows the main characteristics of the core circuitry. Table 14. Core Voltages Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • ON mode - 1.5 - • OFF mode with good battery and RTC mode - 1.2 - - 1.0 - • ON mode with good battery - 1.5 - • OFF mode with good battery - 1.2 - • RTC mode - 1.2 - - 100 - Unit Notes VCOREDIG (DIGITAL CORE SUPPLY) VCOREDIG CCOREDIG Output voltage VCOREDIG bypass capacitor V (35) F VDDLP (DIGITAL CORE SUPPLY - LOWER POWER) VDDLP CDDLP Output voltage VDDLP bypass capacitor V (36) pF (37) MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 26 Functional Block Description Table 14. Core Voltages Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit • ON mode - 2.775 - • OFF and RTC mode - 0.0 - - 1.0 - F Output voltage - 1.2 - V Absolute Accuracy - 0.5 - % Temperature Drift - 0.25 - % VCOREREF bypass capacitor - 100 - nF Notes VCORE (ANALOG CORE SUPPLY) VCORE CCORE Output voltage VCORE bypass capacitor V (35) VCOREREF (BANDGAP VOLTAGE/ REGULATOR REFERENCE) VCOREREF CCOREREF (35) Notes 35. 3.0 V < BP < 4.5 V, no external loading on VCOREDIG, VDDLP, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction. 36. Powered by VCOREDIG 37. Maximum capacitance on VDDLP should not exceed 1000 pF, including the board capacitance. 7.3 7.3.1 Clocking and Oscillators Clock Generation A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running (for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. Support is also provided for an external Secure Real Time Clock (SRTC) which may be integrated on a companion system processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented. 7.3.1.1 Clocking Scheme The internal 32 kHz oscillator is an integrated backup for the crystal oscillator, and provides a 32.768 kHz nominal frequency at 60% accuracy, if running. The internal oscillator only runs if a valid supply is available at BP, and would not be used as long as the crystal oscillator is active. In absence of a valid supply at the BP supply node, the crystal oscillator will continue to operate as it is powered from the coin cell battery. All control functions will run off the crystal derived frequency, occasionally referred to as “32 kHz” for brevity’s sake. During the switch-over between the two clock sources (such as when the crystal oscillator is starting up), the output clock is maintained at a stable active low or high phase of the internal 32 kHz clock to avoid any clocking glitches. If the XTAL clock source suddenly disappears during operation, the IC will revert back to the internal clock source. Given the unpredictable nature of the event and the startup times involved, the clock may be absent long enough for the application to shutdown during this transition due to various reasons, for example a sag in the regulator output voltage or absence of a signal on the clock output pins. A status bit, CLKS, is available to indicate to the processor which clock is currently selected: CLKS = 0 when the internal RC is used and CLKS = 1 if the crystal source is used. The CLKI interrupt bit will be set whenever a change in the clock source occurs, and an interrupt will be generated if the corresponding CLKM mask bit is cleared. MC34708 27 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.3.1.2 Oscillator Specifications The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A32.768 kHz-9.0 pF-30 ppm or equivalent (such as Micro Crystal CC5V-T1A or Epson FC135) and is capable of handling its parametric variations. Ensure that the chosen crystal has a typical drive level of 0.5 µW or above to ensure proper operation of the crystal oscillator. Using a crystal with a lower drive level can cause overtone oscillations. The electrical characteristics of the 32 kHz Crystal oscillator are given in the following table, taking into account the crystal characteristics noted above. The oscillator accuracy depends largely on the temperature characteristics of the crystal. Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component accuracy and/ or tuning). Additionally, a clock calibration system is provided to adjust the 32.768 cycle counter that generates the 1.0 Hz timer and RTC registers; see SRTC Support for more detail. Table 15. Oscillator and Clock Main Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes OSCILLATOR AND CLOCK OUTPUT VINRTC IINRTC Operating Voltage 1.8 - 4.5 • Oscillator and RTC Block from LICELL 1.8 - 3.6 - 2.0 5.0 - - 1.0 0.0 - 0.2 • CLK32K Output source 100 A   CLK32K VCC -0.2 - CLK32K VCC • CLK32KMCU Output sink 50 A VSRTC-0.2 - VSRTC • CLK32KDRV [1:0] = 00 - 6.0 - • CLK32KDRV [1:0] = 01 (default) - 2.5 - • CLK32KDRV [1:0] = 10 - 3.0 - • CLK32KDRV [1:0] = 11 - 2.0 - - 22 - 45 - 55 - - 30 Operating Current Crystal Oscillator and RTC Module • All blocks disabled, no main battery attached, coin cell is attached to LICELL tSTART-RTC A RTC oscillator startup time • Upon application of power VRTCLO V • Oscillator and RTC Block from BP sec Output Low • CLK32K Output sink 100 A V • CLK32KMCU Output source 50 A VRTCHI tCLK32KET tCKL32K MCUET Output High V CLK32K Rise and Fall Time, CL = 50 pF ns CLK32KMCU Rise and Fall Time • CL = 12 pF CLK32KDC/ CLK32K and CLK32KMCU Output Duty Cycle CLK32K • Crystal on XTAL1, XTAL2 pins MCUDC ns % RMS Output Jitter • 1 Sigma for Gaussian distribution ns RMS MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 28 Functional Block Description 7.3.2 SRTC Support When configured for DRM mode (SPI bit DRM = 1), the CLK32KMCU driver will be kept enabled through all operational states to ensure the SRTC module always has its reference clock. If DRM = 0, the CLK32KMCU driver will not be maintained in the Off state. It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed for such capability. This can be accomplished by connecting an open drain NMOS driver to the PWRON pin of the MC34708 PMIC, so it is in effect, a parallel path for the power key. The MC34708 PMIC will not be able to discern the turn on event from a normal power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is generated locally. Open Drain output for RTC wake-up 34708 Processor 32 kHz SPIVCC=1.8 V I/O GP Domain=1.1 V Core Supply VCOREDIG LP Dominant=1.2 V SOG Supply On Detect SRTC HP-RC 32 kHz for DSM timing VCOREDIG Best of Supply VSRTC=1.2 V LP-RTC PWRONx CKIL: VSRTC 0.1 F On/Off Button VSRTC & Detect CLK32KMCU Coin Cell + Battery - + Main - Battery Figure 5. SRTC Block Diagram 7.3.2.1 VSRTC The VSRTC regulator provides the CLK32KMCU output level. Additionally, it is used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The VSRTC regulator cannot be disabled. Depending on the configuration of the PUMS[4:0] pins, the VSRTC voltage will be set to 1.3 or 1.2 V. With PUMS[4:0] = (0110, 0111, 1000, or 1001) VSRTC will be set to 1.3 V in ON mode (ON, ON Standby and ON Standby Low Power modes). In OFF and Coin Cell modes the VSRTC voltage will drop to 1.2 V with the PUMS[4:0] = (0110, 0111, 1000, or 1001). With PUMS[4:0] ≠ (0110, 0111, 1000, or 1001), VSRTC will be set to 1.2 V for all modes (ON, ON Standby, LPM ON Standby, OFF, and Coin Cell). Table 16. VSRTC Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes GENERAL VSRTCIN ISRTC COSRTC Operating Input Voltage Range VINMIN to VINMAX V • Valid Coin Cell range 1.8 - 3.6 • Valid BP 1.8 - 4.5 0.0 - 50 A - 0.1 - F Operating Current Load Range ILMIN to ILMAX Bypass Capacitor Value (38) MC34708 29 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 16. VSRTC Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit 1.15 1.20 1.28 V 1.15 1.2 1.25 V 1.25 1.3 1.35 V Notes VSRTC - ACTIVE MODE - DC VSRTC Output Voltage VOUT • VINMIN < VIN < VINMAX • ILMIN < IL < ILMAX • Off and coincell mode VSRTC Output Voltage VOUT • VINMIN < VIN < VINMAX • ILMIN < IL < ILMAX • PUMS[4:0]  (0110, 0111, 1000, 1001) • On mode (On, Standby, Standby LPM) VSRTC Output Voltage VOUT • VINMIN < VIN < VINMAX • ILMIN < IL < ILMAX • PUMS[4:0] = (0110, 0111, 1000, 1001) • On mode (On, Standby, Standby LPM) ISRTCQ A Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 • VSRTC = 1.2 V - 1.7 - • VSRTC = 1.3 V - 2.7 - Notes 38. Valid for BP > 2.4 V and/or LICELL > 2.0 V. 7.3.2.2 Real Time Clock A Real Time Clock (RTC) is provided with time and day counters as well as an alarm function. The RTC utilizes the 32.768 kHz crystal oscillator for the time base and is powered by the coin cell backup supply when BP has dropped below operational range. In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1 (defaults on at power up). Time and Day Counters The 32.768 kHz clock is divided down to a 1.0 Hz time tick which drives a 17 bit Time Of Day (TOD) counter. The TOD counter counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments the 15 bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1HZI interrupt if unmasked. Time Of Day Alarm A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated. Timer Reset As long as the supply at BP is valid, the real time clock will be supplied from VCOREDIG. If BP is not valid, the real time clock can be backed up from a coin cell via the LICELL pin. When the VSRTC voltage drops to the range of 0.9 - 0.8 V, the RTCPORB reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with RTCPORB. To inform the processor the contents of the RTC are no longer valid due to the reset, a timer reset interrupt function is implemented with the RTCRSTI bit. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 30 Functional Block Description RTC Timer Calibration A clock calibration system is provided to adjust the 32.768 cycle counter that generates the 1.0 Hz timer for RTC timing registers. The general implementation relies on the system processor to measure the 32.768 kHz crystal oscillator against a higher frequency and more accurate system clock such as a TCXO. If the RTC timer needs a correction, a 5-bit 2’s complement calibration word can be sent via the SPI to compensate the RTC for inaccuracy in its reference oscillator. Table 17. RTC Calibration Settings Code in RTCCAL[4:0] Correction in Counts per 32768 Relative correction in ppm 01111 +15 +458 00011 +3 +92 00001 +1 +31 00000 0 0 11111 -1 -31 11101 -3 -92 10001 -15 -458 10000 -16 -488 The available correction range should be sufficient to ensure drift accuracy in compliance with standards for DRM time keeping. Note that the 32.768 kHz oscillator is not affected by RTCCAL settings; calibration is only applied to the RTC time base counter. Therefore, the frequency at the clock output CLK32K is not affected. The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode. Table 18. RTC Calibration Enabling RTCCALMODE Function 00 RTC Calibration disabled (default) 01 RTC Calibration enabled in all modes except coin cell only 10 Reserved for future use. Do not use. 11 RTC Calibration enabled in all modes The RTC Calibration circuitry can be automatically disabled when main battery contact is lost or if it is so deeply discharged that the RTC power draw is switched to the coin cell (configured with RTCCALMODE=01). Because of the low RTC consumption, RTC accuracy can be maintained through long periods of the application being shut down, even after the main battery has discharged. However, the calibration can only be as good as the RTCCAL data provided, so occasional refreshing is recommended to ensure any drift influencing environmental factors have not skewed the clock beyond desired tolerances. MC34708 31 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.3.3 Coin Cell Battery Backup The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. This switch over occurs for a BP below 1.8 V threshold with LICELL greater than BP. A small capacitor should be placed from LICELL to ground under all circumstances. Upon initial insertion of the coin cell, it is not immediately connected to the on chip circuitry. The cell gets connected when the IC powers on, or after enabling the coin cell charger when the IC was already on. The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit. The coin cell voltage is programmable through the VCOIN[2:0] bits. The coin cell charger voltage is programmable in the ON state where the charge current is fixed at ICOINHI. If COINCHEN=1 when the system goes into Off or User Off state, the coin cell charger will continue to charge to the predefined voltage setting but at a lower maximum current ICOINLO. This compensates for self discharge of the coin cell and ensures if and/ or when the main cell gets depleted, the coin cell will be topped off for maximum RTC retention. The coin cell charging will be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs. Table 19. Coin Cell Voltage Specifications VCOIN[2:0] Output Voltage 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 Table 20. Coin Cell Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit - 100 - mV Notes COIN CELL CHARGER VLICELLACC Voltage Accuracy ILICELLON Coin Cell Charge Current in On and Watchdog modes ICOINHI - 60 - A ILICELLOFF Coin Cell Charge Current in Off, cold start/warm start, and Low Power Off modes (User Off / Memory Hold) ICOINLO - 10 - A ILICELACC Current Accuracy - 30 - % COLICELL LICELL Bypass Capacitor - 100 - nF LICELL Bypass Capacitor as coin cell replacement - 4.7 - F MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 32 Functional Block Description 7.4 Interrupt Management 7.4.1 Control The system is informed about important events, based on interrupts. Unmasked interrupt events are signaled to the processor by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C. Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register, which will also cause the interrupt line to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high. Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking. The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. Interrupts generated by external events are debounced. Therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table later in this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly. 7.4.2 Interrupt Bit Summary Table 21 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions, refer to the related chapters. Table 21. Interrupt, Mask and Sense Bits Interrupt Mask Sense Purpose Debounce Time Trigger ADCDONEI ADCDONEM - ADC has finished requested conversions L2H 0 TSDONEI TSDONEM - Touch screen has finished conversion L2H 0 TSPENDET TSPENDETM - Touch screen pen detect Dual 1.0 ms USBOVP USBOVPM USBOVPS VBUS over-voltage Sense is 1 if above threshold. Dual Programmable SUP_OVP_DB LOWBATT LOWBATTM - Low battery detect Sense is 1 if below LOWBAT threshold H2L Programmable VBATTDB USBDET USBDETM USBDETS USB VBUS detect Sense is 1 if detected Dual Programmable VBUSDB Stuck_Key_RCV Stuck_Key_RCV_m - Stuck key has recovered L2H Stuck_Key Stuck_Key_m - Stuck key detected L2H ADC_Change ADC_Change_m ADC_STATUS ADC result changed Sense is 1 if conversion is completed, 0 if L2H in progress Unknown_Atta Unknown_Atta_m - Unknown accessory detected L2H LKR LKR_m - Remote control long key is released L2H LKP LKP_m - Remote control long key is pressed L2H KP KP_m - Remote control key is pressed L2H Detach Detach_m - Accessory detached L2H MC34708 33 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 21. Interrupt, Mask and Sense Bits Interrupt Attach Mask Attach_m Sense Purpose - Accessory attached ID_GNDS Sense is 1 if ID pin is grounded ID_FLOATS Sense is 1 if ID pin is floating ID_DET_ENDS Sense is 1 if ID resistance detection is complete Debounce Time Trigger L2H VBUS_DET_ENDS Sense is 1 if VBUS PTSI is complete SCPI SCPM - Regulator short-circuit protection tripped L2H min. 4.0 ms max 8.0 ms 1HZI 1HZM - 1.0 Hz time tick L2H 0 TODAI TODAM - Time of day alarm L2H 0 PWRON1I PWRON1M PWRON1S Power on button 1 event Sense is 1 if PWRON1 is high H2L 30 ms (39) L2H 30 ms PWRON2I PWRON2M PWRON2S Power on button 2 event Sense is 1 if PWRON2 is high H2L 30 ms (39) L2H 30 ms SYSRSTI SYSRSTM - System reset through PWRONx pins L2H 0 WDIRESETI WDIRESETM - WDI silent system restart L2H 0 PCI PCM - Power cut event L2H 0 WARMI WARMM Warm Start event L2H 0 MEMHLDI MEMHLDM Memory Hold event L2H 0 CLKI CLKM CLKS 32 kHz clock source change Sense is 1 if source is XTAL Dual 0 RTCRSTI RTCRSTM - RTC reset has occurred L2H 0 THERM110 THERM110M THERM110S Thermal 110C threshold Sense is 1 if above threshold Dual Programmable DIE_TEMP_DB THERM120 THERM120M THERM120S Thermal 120C threshold Sense is 1 if above threshold Dual Programmable DIE_TEMP_DB THERM125 THERM125M THERM125S Thermal 125C threshold Sense is 1 if above threshold Dual Programmable DIE_TEMP_DB THERM130 THERM130M THERM130S Thermal 130C threshold Sense is 1 if above threshold Dual Programmable DIE_TEMP_DB GPIOLVxI GPIOLVxM GPIOLVxS General Purpose input interrupt Programmable Programmable Notes 39. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Turn On Events for details. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 34 Functional Block Description 7.5 Power Generation The MC34708 PMIC provides reference and supply voltages for the application processor as well as peripheral devices. Six buck (step down) converters and one boost (step up) converter are included. One of the buck regulators can be configured in dual phase, single phase mode, or operate as separate independent outputs (in this case, there are six buck converters). The buck converters provide the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for the processor cores and/or other circuitry. The boost converter supplies the VUSB regulator for the USB PHY on the processor. The VUSB regulator is powered from the boost to ensure sufficient headroom for the LDO through the normal discharge range of the main battery. Linear regulators could be supplied directly from the battery or from one of the switching regulator, and provide supplies for IO and peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. Naming conventions are suggestive of typical or possible use case applications, but the switching and linear regulators may be utilized for other system power requirements within the guidelines of specified capabilities. Four general purpose I/Os are available. When configured as inputs they can be used as external interrupts. 7.5.1 Power Tree Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 22 summarizes the available power supplies. Table 22. Power Tree Summary Supply Purpose (typical application) Output Voltage (in V) Load Capability (in mA) SW1 Buck regulator for processor VDDGP domain 0.650 - 1.4375 2000 SW2 Buck regulator for processor VCC domain 0.650 - 1.4375 1000 SW3 Buck regulator for processor VDD domain and peripherals 0.650 - 1.425 500 SW4A Buck regulator for DDR memory and peripherals 1.200 – 1.85: 2.5/3.15 500 SW4B Buck regulator for DDR memory and peripherals 1.200 – 1.85: 2.5/3.15 500 SW5 Buck regulator for I/O domain 1.200 – 1.85 1000 SWBST Boost regulator for USB OTG 5.00/5.05/5.10/5.15 380 VSRTC Secure Real Time Clock supply 1.2 0.05 1.2/1.25/1.5/1.8 50 VPLL VREFDDR VDAC VUSB2 VGEN1 VGEN2 VUSB Quiet Analog supply DDR Ref supply 0.6-0.9 10 TV DAC supply, external PNP 2.5/2.6/2.7/2.775 250 VUSB/peripherals supply, internal PMOS 2.5/2.6/2.75/3.0 65 VUSB/peripherals external PNP 2.5/2.6/2.75/3.0 350 General peripherals supply #1 1.2/1.25/1.3/1.35/1.4/1.45/1.5/1.55 250 General peripherals supply #2, internal PMOS 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 50 General peripherals supply #2, external PNP 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 250 3.3 100 USB Transceiver supply MC34708 35 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.5.2 Modes of Operation The MC34708 PMIC is fully programmable via the SPI/I2C interface and associated register map. Additional communication is provided by direct logic interfacing, including interrupt, watchdog, and reset. Default startup of the device is selectable by hardwiring the Power Up Mode Select (PUMS) pins. Power cycling of the application is driven by the MC34708 PMIC. It has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures the supply of the Real Time Clock (RTC), critical internal logic, and other circuits from the coin cell, in case of brief interruptions from the main battery. A charger for the coin cell is included to ensure it is kept topped off until needed. The MC34708 PMIC provides the timekeeping, based on an integrated low power oscillator running with a standard crystal. This oscillator is used for internal clocking, the control logic, and as a reference for the switcher PLL. The timekeeping includes time of day, calendar, and alarm, and is backed up by coin cell. The clock is driven to the processor for reference and deep sleep mode clocking. From any state: Loss of Power with PCEN=0 Thermal Protection Trip, or System Reset PCT[7:0] Expired Off Unqual’d Turn On WDI Low, WDIRESET=0 Unqual’d Turn On Turn On Event Start Up States Warm Start Reset Timer Expired Reset Timer Expired Watchdog Cold Start WDI Low WDIRESET=1 and PCMAXCNT is exceeded WDI Low WDIRESET=1 and PCMAXCNT is not exceeded Watchdog Timer Expired On Turn On Event (Warm Start) Processor Request for User Off: USEROFFSPI=1 Low Power Off States Warm Start Enabled User Off Turn On Event (Warm Boot) Warm Start Not Enabled Memory Hold User Off Wait WARMEN=1 From any state: Loss of Power with Power Cuts enabled (PCEN=1) and PCMAXCNT not exceeded PCUT Timeout PCT[7:0] Expired PCUTEXPB cleared to 0 WARMEN=0 Internal MemHold Power Cut Application of Power before PCUT Timer PCT[7:0] expiration (PCEN=1 and PCMAXCNT not exceeded) Legend and Notes (refer to text for additional details) Blue Box = Steady State, no specific timer is running Green Circle = Transitional State, a specific timer is running, see text Dashed Boxes = Grouping of States for clarification WDI has influence only in the “On” state Complete loss of BP and coin cell power is not represented in the state machine Figure 6. Power Control State Machine Flow Diagram MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 36 Functional Block Description The following are text descriptions of the power states of the system for additional details of the state machine to complement the drawing in Figure 6. Note that the SPI control is only possible in the Watchdog, On and User Off Wait states and the interrupt line INT is kept low in all states except for Watchdog and On. 7.5.2.1 Coin Cell The RTC module is powered from either the battery or the coin cell, due to insufficient voltage at VALWAYS, and the IC is not in a Power Cut. No Turn On event is accepted in the Coin Cell state. Transition out (to the Off state) requires VALWAYS restoration with a threshold above UVDET. RESETB and RESETBMCU are held low in this mode. The RTC module remains active (32 kHz oscillator + RTC timers), along with VALWAYS level detection to qualify exit to the Off state. VCOREDIG is off and the VDDLP regulator is on, the rest of the system is put into its lowest power configuration. If the coin cell is depleted (VSTRC drops to 0.9 - 0.8 V while in the Coin Cell state), a complete system reset will occur. At next power application / Turn On event, the system will startup reinitialized with all SPI bits including those that reset on RTCPORB restored to their default states. 7.5.2.2 Off (with good battery) If the supply VALWAYS is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered, all other supplies are inactive. To exit the Off state, a valid turn on event is required. No specific timer is running in this state. RESETB, RESETBMCU are held low in this state. If the supply VALWAYS is below the UVDET threshold, no turn on events are accepted. If a valid coin cell is present, the core gets powered from LICELL. The only active circuitry is the RTC module and the VCORE module powering VCOREDIG at 1.5 V. 7.5.2.3 Cold Start Cold Start is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or a Silent System Restart. The first 8.0 ms is used for initialization which includes bias generation, PUMSx configuration latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see the Power Up section for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering Cold Start. The Cold Start state is exited for the Watchdog state and both RESETB and RESETBMCU become high (open drain output with external pull-ups) when the reset timer expires. The input control pins WDI, and STANDBY are ignored. 7.5.2.4 Watchdog The system is fully powered and under SPI/I2C control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBY are ignored while in the Watchdog state. 7.5.2.5 On Mode The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this state. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW5 = 1.8 V); SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration; refer to the section on Silent System Restart with WDI Event for details). 7.5.2.6 User Off Wait The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off. The Wait timer starts running when entering User Off Wait state. This leaves the processor time to suspend or terminate its tasks. When expired, the Wait state is exited for User Off state or Memory Hold state depending on warm starts being enabled or not via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low. MC34708 37 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.5.2.7 Memory Hold and User Off (Low Power Off States) As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response to an intentional turn off by the user. The only exit then will be a turn on event. To the user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in self-refresh state (Memory Hold and User Off state) as well as powering portions of the processor core for state retention (User Off only). The Switching regulator mode control bits allow selective powering of the buck regulators for optimizing the supply behavior in the low power Off states. Linear regulators and most functional blocks are disabled (the RTC module, SPI bits resetting with RTCPORB, and Turn On event detection are maintained). By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is applied to the processor’s VCC domain, SW3 supplies the processor’s internal memory/peripherals, and SW4 supplies the external memory, and SW5 supplies the I/O rail. The buck regulators are intended for direct connection to the aforementioned loads. 7.5.2.8 Memory Hold RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To ensure that SW1, SW2, SW3, and SW5 shut off in Memory Hold, appropriate mode settings should be used such as SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1. Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot. No specific timer is running in this state. Buck regulators configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when coming out of MEMHOLD and entering a Warm Boot. The switching regulators will be reconfigured for their default settings as selected by the PUMSx pins in the normal time slot affecting them. 7.5.2.9 User Off RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set. The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and/or SW3 supply domains can be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switching regulators can be shut down in User Off, its mode bits would typically be set to 0. Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used for very low frequency / low power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the system left off before the USEROFF command. Upon a Turn On event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode. 7.5.2.10 Warm Start Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see Startup Requirements for sequencing and default level details. If SW1, SW2, SW3, SW4, and/or SW5, were configured to stay on in User Off mode by their SWxUOMODE settings, they will not be turned off when coming out of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the PUMSx pins in the respective time slot defined in the sequencer selection. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 38 Functional Block Description RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high. 7.5.2.11 Internal MemHold Power Cut As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply the MC34708 core, along with the 32 kHz crystal oscillator, the RTC system, and coin cell backed up registers. All regulators will be shut down to preserve the coin cell and RTC as long as possible. Both RESETB and RESETBMCU are tripped, bringing the entire system down, along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start. If the PCT timer expires before power is re-established, the system transitions to the Off state and awaits a sufficient supply recovery. 7.5.3 7.5.3.1 Power Control Logic Power Cut Description When the supply at VALWAYS drops below the UVDET threshold, due to battery bounce or battery removal, the Internal MemHold Power Cut state is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled. The maximum duration of a power cut is determined by the PCUT timer PCT [7:0] preset via the SPI. When a PCUT occurs, the PCUT timer will be started. The contents of PCT [7:0] does not reflect the actual count down value, but will keep the programmed value, and therefore does not have to be reprogrammed after each power cut. If power is not re-established above the LOWBATT threshold before the PCUT timer expires, the state machine transitions to the Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful” PCUT. In addition the PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down. Upon re-application of power before expiration (a “successful PCUT”, defined as VALWAYS first rising above the UVDET threshold and then battery above the LOWBATT threshold before the PCUT timer expires), a Cold Start is engaged after the UVTIMER has expired. In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by software. The PCI interrupt is cleared by software or when cycling through the Off state. Because the PCUT system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current through the battery and trace impedances can once again cause the BP node to droop below UVDET. This chain of cyclic power down / power up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize the chance of a product falling into and getting stuck in ambulance mode. First, the successful recovery out of a PCUT requires the VABTT node to rise above LOBATT threshold, providing hysteretic margin from the LOBATTT (H to L) threshold. Second, the number of times the PCUT mode is entered is counted with the counter PCCOUNT [3:0], and the allowed count is limited to PCMAXCNT [3:0] set through SPI. When the contents of both become equal, then the next PCUT will not be supported and the system will go to Off mode, after the PCUT time expires. After a successful power up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor reassumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not enabled, then in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB = 1 (See Silent Restart from PCUT Event). MC34708 39 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.5.3.2 Silent Restart from PCUT Event If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent restart, so the system is reinitialized without alerting the user. This can be facilitated by setting the PCUTEXPB bit to “1” at booting or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and PCUTEXPB is still “1”, then the state machine has not transitioned through Off, which confirms the PCT timer has not expired during the PCUT event (i.e., a successful power cut). In this case, a silent restart may be appropriate. If PCUTEXPB is found to be “0” after the Cold Start where PCI is found to be “1”, then it is inferred the PCT timer has expired before power was re-established. This indicates an unsuccessful power cut or first power up, so the startup user greeting may be desirable for playback. 7.5.3.3 Silent System Restart with WDI Event A mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset, but it is desired to make the reset a silent event so as to happen without user awareness. The default response to WDI going low is for the state machine to transition to the Off state (when WDIRESET = 0). However, if WDIRESET = 1, the state machine will go to Cold Start without passing through Off mode (i.e., does not generate an OFFB signal). A WDIRESET event will generate a maskable WDIRESETI interrupt and also increment the PCCOUNT counter. This function is unrelated to PCUTs, but it shares the PCUT counter so the number of silent system restarts can be limited by the programmable PCMAXCNT counter. When PCUT support is used, the software should set the PCUTEXPB bit to “1”. Since this bit resets with RTCPORB, it will not be reset to “0” if a WDI falls and the state machine goes straight to the Cold Start state. Therefore, upon a restart, software can discern a silent system restart if there is a WDIRESETI interrupt and PCUTEXPB = 1. The application may then determine an inconspicuous restart without fanfare may be more appropriate than launching into the welcoming routine. A PCUT event does not trip the WDIRESETI bit. Note that the system response to WDI is gated by the Watchdog timer—once the timer has expired, the system will respond as programmed by WDIRESET as described above. Applications should make sure there is time for switching regulator outputs to discharge before re-asserting WDI. 7.5.3.4 Turn On Events When in Off mode, the circuit can be powered on via a Turn On event. The Turn On events are listed by the following. To indicate to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events. Masking the interrupts related to the turn on events will not prevent the part to turn on except for the time of day alarm. If the part was already on at the time of the turn on event, the interrupt is still generated. • Power Button Press: PWRON1 or PWRON2 pulled low with corresponding interrupts and sense bits PWRON1I, or PWRON2I and PWRON1S, or PWRON2S. A power on/off button is connected from PWRONx to ground. The PWRONx can be hardware debounced through a programmable debouncer PWRONxDBNC [1:0] to avoid a response upon a very short (i.e., unintentional) key press. BP should be above UVDET to allow a power up. The PWRONxI interrupt is generated for both the falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The PWRONxI interrupt is cleared by software or when cycling through the Off mode. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 40 Functional Block Description Table 23. PWRONx Hardware Debounce Bit Settings(40) Bits State Turn On Debounce (ms) Falling Edge INT Debounce (ms) Rising Edge INT Debounce (ms) PWRONxDBNC[1:0] 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 40. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin. • Battery Attach: This occurs when BP crosses the LOWBATT threshold which is equivalent to attaching a charged battery to the product. • USB Attach: VBUS pulled high with corresponding interrupt and sense bits USBDET and USBDETS. This is equivalent to plugging in a USB cable connected to a host powering the VBUS line. The battery voltage should be above LOWBATT. For details on the USB detection, see Mini/Micro USB Switch. • RTC Alarm: TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset time. BP should be above LOWBATT. For details and related interrupts, see Real Time Clock. • System Restart: System restart which may occur after a system reset as described earlier in this section. This is an optional function, see Turn Off Events. BP should be above LOWBATT. • Global System Reset: The global reset feature powers down the part, resets the SPI registers to their default value including all the RTCPORB registers (except the DRM bit, and the RTC registers), and then powers back on. To enable a global reset, the GLBRST pin needs to be pulled low for greater than GLBRSTTMR [1:0] seconds and then pulled back high (defaults to 12 s). BP should be above LOWBATT. Table 24. Global Reset Time Settings 7.5.3.5 Bits State Time (s) GLBRSTTMR[1:0] 00 INVALID 01 4 10 8 11 (default) 12 Turn Off Events • Power Button Press (via WDI): User shutdown of a product is typically done by pressing the power button connected to the PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off by the processor’s response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore, under normal circumstances, not considered as a turn off event for the state machine. However, since the button press power down is the most common turn off method for end products, it is described in this section as the product implementation for a WDI initiated Turn Off event. Note that the software can configure a user initiated power down, via a power button press for transition to a Low Power Off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state. • Power Button System Reset: A secondary application of the PWRONx pins is the option to generate a system reset. This is recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the PWRONxRSTEN bits. When enabled, a four second long press on the power button will cause the device to go to the Off mode, and as a result, the entire application will power down. An interrupt SYSRSTI is generated upon the next power up. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. • Thermal Protection: If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling sufficiently to accept a Turn On event. There are no specific interrupts related to this, other than the warning interrupts. • BP lower than VBAT_TRKL: When the voltage at BP drops below VBAT_TRKL[1:0] - 100mV, the state machine will transition to the Off mode. The SDWNB pin is used to notify the processor that the PMIC is going to immediately shutdown. The PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down. This signal will then be brought back high into the power off state. MC34708 41 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 25. Turn OFF Voltage Threshold 7.5.3.6 VBAT_TRKL[1:0] Turn off Voltage threshold 00 2.8 01 2.9 10 3.0 (default) 11 3.1 Timers The different timers as used by the state machine are listed in Table 26. This listing does not include RTC timers for timekeeping. A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous event, the duration listed below is therefore the effective minimum time period. Table 26. Timer Main Characteristics 7.5.3.6.1 Timer Duration Clock Under-voltage Timer 4.0 ms 32 k/32 Reset Timer 40 ms 32 k/32 Watchdog Timer 128 ms 32 k/32 Power Cut Timer Programmable 0 to 8 seconds in 31.25 ms steps 32 k/1024 Timing Diagrams A Turn On event timing diagrams shown in Figure 7. ow Turn On Event WDI Pulled Low Sequencer time slots System Core Active Turn On Verification Power Up Sequencer UV Masking RESETB INT WDI 8 ms 1 - Off 8 ms 20 ms 12 ms 128 ms 3 - Watchdog 2 - Cold Start Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high 4 - On 3- Watchdog 1 - Off ... or transition to Off state if WDI remains low Turn on Event is based on PWRON being pulled low = Indeterminate State Figure 7. Power Up Timing Diagram MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 42 Functional Block Description 7.5.3.7 Power Monitoring The voltage at BATT and BP are monitored by detectors as summarized in Table 27. Table 27. LOWBATT Detection Thresholds Threshold in V Bit setting(41) UVDET (V) LOWBATT1 LOWBATT0 0 0 3.1 (Rising) L to H transition (Power on)(42),(43) H to L transition (Low battery detect)(42),(43) LOWBATT LOWBATT 3.1 3.0 3.2 3.1 3.3 3.2 3.4 3.3 2.65 (Falling) 0 1 3.1 (Rising) 2.65 (Falling) 1 0 3.1 (Rising) 2.65 (Falling) 1 1 3.1 (Rising) 2.65 (Falling) Notes 41. Default setting for LOWBATT[1:0] is 11. 42. The above specified thresholds are ±50 mV accurate for the indicated transition 43. A hysteresis is applied to the detectors on the order of 100 mV The UVDET and LOWBATT thresholds are related to the power on/off events as described earlier in this chapter. The LOWBATT threshold when transitioned from low to a high is used to power on the MC34708. The LOWBATT threshold when transitioned from high to low, is used as a low battery detect warning. An interrupt LOWBAT is generated when dropping below the high to low threshold to indicate to the processor the battery is weak and a shutdown is imminent. The LOWBATT detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 28. Table 28. VBATTDB Debounce Times 7.5.3.8 7.5.3.8.1 VATTDB[1:0] Debounce Time 00 0 (default) 01 2 RTC clock cycles 10 4 RTC clock cycles 11 8 RTC clock cycles Power Saving System Standby A product may be designed to go into DSM (Deep Sleep Mode) after periods of inactivity, the STANDBY pin is provided for board level control of timing in and out of such deep sleep modes. When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the switching regulators or disabling some regulators. This can be obtained by controlling the STANDBY pin. The configuration of the regulators in standby is pre-programmed through the SPI. A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set and the STANDBY pin asserted a lower power standby will be entered. In the on Standby Low Power mode, the switching Regulators should all be programmed into PFM mode and the LDO's should be configured to Low Power mode when the STANDBY pin is asserted. The PLL is disabled in this mode so the mini USB will not be able to detect if an audio device, UART, or a USB OTG device is attached. It will require the software to wake up occasionally to allow the mini-USB to detect if a device MC34708 43 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description is attached by de-asserting the STANDBY pin and waking up for a period to see if a device is attached and then re-asserting Standby if a device has not been detected. If a device has been detected then the software can bring up the appropriate application etc. Note the STANDBY pin is programmable for Active High or Active Low polarity, and decoding of a Standby event will take into account the programmed input polarity associated with each pin. For simplicity, Standby will generally be referred to as active high throughout this document, but as defined in Table 29, active low operation can be accommodated. Finally, since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. Table 29. Standby Pin and Polarity Control STANDBY (Pin) STANDBYINV (SPI bit) STANDBY Control(44) 0 0 0 0 1 1 1 0 1 1 1 0 Notes 44. STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby The state of the STANDBY pin only has influence in On mode, and are therefore it is ignored during start up and in the Watchdog phase. This allows the system to power up without concern of the required Standby polarities since software can make adjustments accordingly as soon as it is running. A command to transition to one of the low power Off states (User Off or Memory Hold, initiated with USE-ROFFSPI=1) redefines the power tree configuration based on SWxMODE programming, and has priority over Standby (which also influences the power tree configuration). 7.5.3.8.2 Standby Delay A provision to delay the Standby response is included. This allows the processor and peripherals, some time after a Standby instruction has been received, to terminate processes to facilitate seamless Standby exiting and re-entrance into Normal operating mode. A programmable delay is provided to hold off the system response to a Standby event. When enabled (STBYDLY = 01, 10, or 11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires. Note that this delay is applied only when going into Standby, and no delay is applied when coming out of Standby. Also, an allowance should be accounted for synchronization of the asynchronous Standby event and the internal clocking edges (up to a full 32 kHz cycle of additional delay). Table 30. Delay of STANDBY- Initiated Response STBYDLY[1:0] Function 00 No Delay 01 One 32 k period (default) 10 Two 32 k periods 11 Three 32 k periods MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 44 Functional Block Description 7.5.4 Buck Switching Regulators Six buck switching regulators are provided with integrated power switches and synchronous rectification. In a typical application, SW1 and SW2 are used for supplying the application processor core power domains. Split power domains allow independent DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings. SW3 is used for powering internal processor memory as well as low voltage peripheral devices and interfaces which can run at the same voltage level. SW4A/B is used for powering external DDR memory as well as low voltage peripheral devices and interfaces, which can run at the same voltage level. SW5 is used to supply the I/O domain for the system. The buck regulators are supplied from the system supply BP, which is drawn from the main battery or the external battery charger (when present). The switching regulators can operate in different modes depending on the load conditions. These modes can be set through the SPI/I2C and include a PFM mode, an Automatic Pulse Skipping mode (APS), and a PWM mode. The previous selection is optimized to maximum battery life based on load conditions. Table 31. Buck Operating Modes Mode Description OFF The regulator is switched off and the output voltage is discharged PFM The regulator is switched on and set to PFM mode operation. In this mode, the regulator is always running in PFM mode. Useful at light loads for optimized efficiency. APS The regulator is switched on and set to Automatic Pulse Skipping. In this mode the regulator moves automatically between pulse skipping and full PWM mode depending on load conditions. PWM The regulator is switched on and set to PWM mode. In this mode the regulator is always in full PWM mode operation regardless of load conditions. Buck modes of operation are programmable for explicitly defined or load-dependent control. During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. The regulators are turned on in APS mode by default. After the start-up sequence is complete, all switching regulators should be set to PFM/PWM mode, depending on system load for best performance. Point of load feedback is intended for minimizing errors due to board level IR drops. 7.5.4.1 General Control Operational modes of the Buck regulators can be controlled by direct SPI programming, altered by the state of the STANDBY pin, by direct state machine influence (entering Off or low power Off states, for example), or by load current magnitude when so configured (APS mode). Available modes include PWM, PFM, APS and OFF. For light loading, the regulators should be put into PFM mode to optimize efficiency. Provisions are made for maintaining PFM operation in User off and Memhold modes, to support state retention for faster startup from the Low Power Off modes for Warm Start or Warm Boot. SWxMODE[3:0] bits will be reset to their default values defined by PUMSx settings by the startup sequencer. Table 32 summarizes the Buck regulators programmability for Normal and Standby modes. Table 32. Switching regulator Mode Control for Normal and Standby Operation SWxMODE[3:0] Normal Mode Standby Mode 0000 Off Off 0001 PWM Off 0010 Reserved Reserved 0011 PFM Off MC34708 45 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 32. Switching regulator Mode Control for Normal and Standby Operation SWxMODE[3:0] Normal Mode Standby Mode 0100 APS Off 0101 PWM PWM 0110 PWM APS 0111 Off Off 1000 APS APS 1001 Reserved Reserved 1010 Reserved Reserved 1011 Reserved Reserved 1100 APS PFM 1101 PWM PFM 1110 Reserved Reserved 1111 PFM PFM In addition to controlling the operating mode in Standby, the voltage setting can be changed. The transition in voltage is handled in a controlled slope manner, see Dynamic Voltage Scaling for details. Each regulator has an associated set of SPI bits for Standby mode set points. By default, the Standby settings are identical to the non-standby settings which are initially defined by PUMSx programming. The actual operating mode of the Switching regulators as a function of the STANDBY pin is not reflected through the SPI. In other words, the SPI will read back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described previously. Two tables follow for mode control in the low power Off states. Note that a low power Off activated SWx should use the Standby set point as programmed by SWxSTBY[4:0]. The activated regulator(s) will maintain settings for mode and voltage until the next startup event. When the respective time slot of the startup sequencer is reached for a given regulator, its mode and voltage settings will be updated the same as if starting out of the Off state (except switching regulators active through a low power Off mode will not be off when the startup sequencer is started). Table 33. Switching regulator Control In Memory Hold SWxMHMODE Memory Hold Operational Mode (45) 0 Off 1 PFM Notes: 45. For Memory Hold mode, an activated SWx should use the Standby set point as programmed by SWxSTBY[4:0]. Table 34. Switching regulator Control In User Off SWxUOMODE User Off Operational Mode (46) 0 Off 1 PFM Notes: 46. For User Off mode, an activated SWx should use the Standby set point as programmed by SWxSTBY[4:0]. In normal steady state operating mode, the SWxPWGD pin is high. When the SWx set point is changed to a higher or lower set point, the SWxPWGD pin will go low and will go high again when the higher/lower set point is reached. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 46 Functional Block Description 7.5.4.2 Switching Frequency A PLL generates the switching system clocking from the 32.768 kHz crystal oscillator reference. The switching frequency can be programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 35. Table 35. Buck Regulator Frequency PLLX Switching Frequency (Hz) 0 2 000 000 1 4 000 000 The clocking system provides a near instantaneous activation when the Switching regulators are enabled or when exiting PFM operation for PWM mode. The PLL can be configured for continuous operation with PLLEN = 1. 7.5.4.3 SW1 SW1 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. It can be operated in single phase/dual phase mode. The operating mode of the switching regulators is configured by the SW1CFG pin. The SW1CFG pin is sampled at startup. Table 36. SW1 Configuration SW1CFG SW1A/B Configuration Mode VCOREDIG Single Phase Mode Ground Dual Phase Mode BP SW1IN SW1 SW1ALX LSW 1A SW1AMODE ISENSE C INSW 1A Controller Driver DSW1 COSW1A SW1FAULT GNDSW1A Internal Compensation SW1FB SPI Z2 Z1 VREF EA DAC SPI Interface BP SW1BIN SW1BMODE ISENSE CINSW 1B SW1BLX GNDSW1B Controller Driver SW1BFAULT VCOREDIG SW1CFG Figure 8. SW1 Single Phase Output Mode Block Diagram MC34708 47 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description BP SW1IN SW1AMODE ISENSE CINSW1A SW1 Controller SW1ALX Driver L SW1A DSW1A COSW1A SW1FAULT GNDSW1A Internal Compensation SW1FB SPI Z2 Z1 EA SPI Interface V REF DAC BP SW1BIN SW1BMODE ISENSE CINSW1B Controller SW1BLX LSW 1B Driver DSW1B COSW 1B SW1BFAULT GNDSW1B SW1CFG Figure 9. SW1 Dual Phase Output Mode Block Diagram The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator will limit the current through cycle by cycle operation and alert the system through the SW1FAULT SPI bit and issue an SCPI interrupt via the INT pin. SW1A/B output voltage is SPI configurable in step sizes of 12.5 mV as shown in the table below. The SPI bits SW1A[5:0] set the output voltage for both SW1A and SW1B. Table 37. SW1A/B Output Voltage Programmability Set Point SW1A[5:0] SW1A/B Set Point SW1A[5:0] Output (V) SW1A/B Output (V) 0 000000 0.6500 32 100000 1.0500 1 000001 0.6625 33 100001 1.0625 2 000010 0.6750 34 100010 1.0750 3 000011 0.6875 35 100011 1.0875 4 000100 0.7000 36 100100 1.1000 5 000101 0.7125 37 100101 1.1125 6 000110 0.7250 38 100110 1.1250 7 000111 0.7375 39 100111 1.1375 8 001000 0.7500 40 101000 1.1500 9 001001 0.7625 41 101001 1.1625 10 001010 0.7750 42 101010 1.1750 11 001011 0.7875 43 101011 1.1875 12 001100 0.8000 44 101100 1.2000 MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 48 Functional Block Description Table 37. SW1A/B Output Voltage Programmability Set Point SW1A[5:0] SW1A/B Set Point SW1A[5:0] Output (V) SW1A/B Output (V) 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.3125 22 010110 0.9250 54 110110 1.3250 23 010111 0.9375 55 110111 1.3375 24 011000 0.9500 56 111000 1.3500 25 011001 0.9625 57 111001 1.3625 26 011010 0.9750 58 111010 1.3750 27 011011 0.9875 59 111011 1.3875 28 011100 1.0000 60 111100 1.4000 29 011101 1.0125 61 111101 1.4125 30 011110 1.0250 62 111110 1.4250 31 011111 1.0375 63 111111 1.4375 Table 38. SW1A/B Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.5 Unit Notes SW1A/B BUCK REGULATOR VSW1IN VSW1ACC ISW1 ISW1PEAK Operating Input Voltage Output Voltage Accuracy ISW1 VSW1OS- mV • PWM mode including ripple, load regulation, and transients Nom-25 Nom Nom+25 • PFM Mode, including ripple, load regulation, and transients Nom-25 Nom Nom+25 • PWM mode single/dual phase (parallel) - - 2000 • SW1 in PFM mode - 50 - - 4.0 - - - 1.0 Continuous Output Load Current, VINMIN < BP < 4.5 V A Transient Load Change • 100 mA/µs Start-up Overshoot, IL = 0 (47) mA Current Limiter Peak Current Detection • VIN = 3.6 V, Current through Inductor TRANSIENT V A - 25 mV START MC34708 49 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 38. SW1A/B Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol tON-SW1 Characteristic Min Typ Max - - 500 • PLLX = 0 - 2.0 - • PLLX = 1 - 4.0 - • APS MODE, IL=0 mA - 240 - • PFM MODE, IL=0 mA - 15 - Turn-on Time ISW1Q SW1 Notes µs • Enable to 90% of end value IL = 0 fSW1 Unit Switching Frequency MHz Quiescent Current Consumption µA Efficiency, % • PFM, 0.9 V, 1.0 mA - 54 - • PWM, 1.1 V, 200 mA - 75 - • PWM, 1.1 V, 800 mA - 81 - • PWM, 1.1 V, 1600 mA - 76 - (48) Notes: 47. Transient loading for load steps of ILMAX/2. 48. Efficiency numbers at VIN = 3.6 V, excludes the quiescent current 7.5.4.4 SW2 SW2 is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator. BP SW2IN CINSW 2 SW2 SW2LX LSW2 C OSW2 SW2MODE ISENSE Controller Driver D SW 2 SW2FAULT GNDSW2 Internal Compensation SW2FB SPI Interface SPI Z2 Z1 EA DAC V REF Figure 10. SW2 Block Diagram The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator will limit the current through cycle by cycle operation, alert the system through the SW2FAULT SPI bit, and issue an SCPI interrupt via the INT pin SW2 can be programmed in step sizes of 12.5 mV as shown in Table 39. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 50 Functional Block Description Table 39. SW2 Output Voltage Programmability Set Point SW2[5:0] SW2x Output (V) Set Point SW2[5:0] SW2 Output (V) 0 000000 0.6500 32 100000 1.0500 1 000001 0.6625 33 100001 1.0625 2 000010 0.6750 34 100010 1.0750 3 000011 0.6875 35 100011 1.0875 4 000100 0.7000 36 100100 1.1000 5 000101 0.7125 37 100101 1.1125 6 000110 0.7250 38 100110 1.1250 7 000111 0.7375 39 100111 1.1375 8 001000 0.7500 40 101000 1.1500 9 001001 0.7625 41 101001 1.1625 10 001010 0.7750 42 101010 1.1750 11 001011 0.7875 43 101011 1.1875 12 001100 0.8000 44 101100 1.2000 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.3125 22 010110 0.9250 54 110110 1.3250 23 010111 0.9375 55 110111 1.3375 24 011000 0.9500 56 111000 1.3500 25 011001 0.9625 57 111001 1.3625 26 011010 0.9750 58 111010 1.3750 27 011011 0.9875 59 111011 1.3875 28 011100 1.0000 60 111100 1.4000 29 011101 1.0125 61 111101 1.4125 30 011110 1.0250 62 111110 1.4250 31 011111 1.0375 63 111111 1.4375 MC34708 51 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 40. SW2 Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.5 Unit Notes SW2 BUCK REGULATOR VSW2IN VSW2ACC ISW2 ISW2PEAK Operating Input Voltage Output Voltage Accuracy ISW2 VSW2OS- mV • PWM mode including ripple, load regulation, and transients Nom-25 Nom Nom+25 • PFM Mode, including ripple, load regulation, and transients Nom-25 Nom Nom+25 • PWM mode - - 1000 • PFM mode - 50 - - 2.0 - Continuous Output Load Current, VINMIN < BP < 4.65 V A Transient Load Change • 100 mA/µs A - - 0.500 - - 25 - - 500 • PLLX = 0 - 2.0 - • PLLX = 1 - 4.0 - • APS MODE, IL = 0 mA; device not switching - 160 - • PFM MODE, IL = 0 mA; device not switching - 15 - Start-up Overshoot, IL = 0 (49) mA Current Limiter Peak Current Detection • VIN = 3.6 V Current through Inductor TRANSIENT V mV START tON-SW2 Turn-on Time • Enable to 90% of end value IL = 0 fSW2 ISW2Q SW2 µs Switching Frequency - Quiescent Current Consumption MHz µA Efficiency % • PFM, 0.9 V, 1.0 mA - 54 - • PWM, 1.2 V, 120 mA - 75 - • PWM, 1.2 V, 500 mA - 83 - • PWM, 1.2 V, 1000 mA - 78 - (50) Notes: 49. Transient loading for load steps of ILMAX/2. 50. Efficiency numbers at VIN = 3.6 V, excludes the quiescent current. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 52 Functional Block Description 7.5.4.5 SW3 SW3 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. BP SW3IN SW3MODE ISENSE CINSW 3 SW3 Controller SW3LX Driver L SW3 COSW3 DSW3 SW3FAULT GNDSW3 Internal Compensation SW3FB SPI Interface SPI Z2 Z1 EA DAC V REF Figure 11. SW3 Block Diagram The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator will limit the current through cycle by cycle operation and alert the system through the SW3FAULT SPI bit and issue an SCPI interrupt via the INT pin. SW3 can be programmed in step sizes of 25 mV as shown in Table 41. Table 41. SW3 Output Voltage Programmability Set Point SW3[4:0] SW3 Output (V) Set Point SW3[4:0] SW3 Output (V) 0 00000 0.6500 16 10000 1.0500 1 00001 0.6750 17 10001 1.0750 2 00010 0.7000 18 10010 1.1000 3 00011 0.7250 19 10011 1.1250 4 00100 0.7500 20 10100 1.1500 5 00101 0.7750 21 10101 1.1750 6 00110 0.8000 22 10110 1.2000 7 00111 0.8250 23 10111 1.2250 8 01000 0.8500 24 11000 1.2500 9 01001 0.8750 25 11001 1.2750 10 01010 0.9000 26 11010 1.3000 11 01011 0.9250 27 11011 1.3250 12 01100 0.9500 28 11100 1.3500 13 01101 0.9750 29 11101 1.3750 14 01110 1.0000 30 11110 1.4000 15 01111 1.0250 31 11111 1.4250 MC34708 53 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 42. SW3 Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.5 Unit Notes SW3 BUCK REGULATOR VSW3IN VSW3ACC ISW3 ISW3PEAK Operating Input Voltage Output Voltage Accuracy TRANSIENT VSW3OS- mV • PWM mode including ripple, load regulation, and transients Nom-3% Nom Nom+3% • PFM Mode, including ripple, load regulation, and transients Nom-3% Nom Nom+3% Continuous Output Load Current, VINMIN < BP < 4.65 V - - 500 • PFM mode - 50 - - 1.0 - - - 250 mA - - 25 mV - - 500 Current Limiter Peak Current Detection Transient Load Change (51) mA • PWM mode • VIN = 3.6 V Current through Inductor ISW3 V A • 100 mA/µs Start-up Overshoot, IL = 100 mA/µs START tON-SW3 Turn-on Time • Enable to 90% of end value IL = 0 fSW3 ISW3Q SW3 µs Switching Frequency MHz • PLLX = 0 - 2.0 - • PLLX = 1 - 4.0 - • APSMODE, IL = 0 mA; device not switching - 160 - • PFM MODE, IL = 0 mA; device not switching - 15 - Quiescent Current Consumption µA Efficiency, % • PFM, 1.2 V, 1.0 mA - 71 - • PWM, 1.2 V, 120 mA - 79 - • PWM, 1.2 V, 250 mA - 82 - • PWM, 1.2V, 500 mA - 81 - (52) Notes: 51. Transient loading for load steps of ILMAX/2 52. Efficiency numbers at VIN = 3.6 V, Excludes the quiescent current, MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 54 Functional Block Description 7.5.4.6 SW4 SW4A/B is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator. It can be operated in (single phase/ dual phase mode) or as separate independent outputs. The operating mode of the Switching regulator is configured by the SW4CFG pin. The SW4CFG pin is sampled at startup. Table 43. SW4A/B Configuration SW4CFG SW4A/B Configuration Mode Ground Separate Independent Output VCOREDIG Single Phase VCORE Dual Phase BP SWAIN SW4AMODE ISENSE CINSW 4A SW4A SW4ALX L SW4A Controller Driver DSW 4A COSW4A SW4AFAULT GNDSW4A Internal Compensation SW4AFB SPI Z2 Z1 EA VREF DAC SPI Interface BP SW4BIN SW4B SW4BLX L SW4B COSW 4B SW4BMODE ISENSE CINSW 4B Controller Driver DSW4B SW4BFAULT GNDSW4B Internal Compensation SW4BFB SPI Z2 Z1 EA DAC VREF SW4CFG Figure 12. SW4A/B Separate Output Mode Block Diagram MC34708 55 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description BP SWAIN SW4AMODE ISENSE CINSW4A SW4 SW4ALX LSW4A Controller Driver DSW4 COSW4a SW4AFAULT GNDSW4A Internal Compensation SW4AFB SPI Z2 Z1 VREF EA DAC SPI Interface BP SW4BIN SW4BMODE ISENSE CINSW4B SW4BLX Controller Driver SW4BFAULT GNDSW4B Internal Compensation SW4BFB SPI Z2 Z1 EA VCOREDIG VREF DAC SW4CFG Figure 13. SW4 Single Phase Output Mode Block Diagram MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 56 Functional Block Description BP SWAIN SW4AMODE ISENSE CINSW4A SW4 SW4ALX LSW4A Controller Driver DSW4A COSW4A SW4AFAULT GNDSW4A Internal Compensation SW4AFB SPI Z2 Z1 VREF EA DAC SPI Interface BP SW4BIN SW4BMODE ISENSE CINSW4B SW4BLX LSW4B Controller Driver DSW4B COSW4B SW4BFAULT GNDSW4B Internal Compensation SW4BFB SPI Z2 Z1 EA VCORE VREF DAC SW4CFG Figure 14. SW4 Dual Phase Output Mode Block Diagram The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator will limit the current through cycle by cycle operation and alert the system through the SW4xFAULT SPI bit and issue an SCPI interrupt via the INT pin. SW4A/B has a high output range (2.5 V, 3.15 V) and a low output range (1.2 V – 1.85 V). The SW4A/B output range is set by the PUMS configuration at start-up and cannot be changed dynamically by software. This means if the PUMS are set to allow SW4A to come up in the high output voltage range, the output can only be changed between 2.5 V or 3.15 V. It cannot be programmed in the low output range. If software sets the SW4AHI[1:0] = 00 when the PUMS is set to come up in the high voltage range, the output voltage will only go as low as the lowest setting in the high range, which is 2.5 V. If the PUMS are set to start-up in the low output voltage range, the voltage is controlled through the SW4x[4:0] bits by software, it cannot be programmed into the high voltage range. When changing the voltage in either the high or low voltage range, the regulator should be forced into PWM mode to change the voltage. Table 44. SW4A/B Output Voltage Select SW4xHI[1:0] Set point selected by Output Voltage 00 SW4x[4:0] See Table 45 01 SW4xHI[1:0] 2.5 V 10 SW4xHI[1:0] 3.15 V 11 Invalid Invalid MC34708 57 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 45. SW4A/B Output Voltage Programmability Set Point SW4x[4:0] SW4x Output (V) 0 00000 1.2000 16 10000 1.6000 1 00001 1.2250 17 10001 1.6250 2 00010 1.2500 18 10010 1.6500 3 00011 1.2750 19 10011 1.6750 4 00100 1.3000 20 10100 1.7000 5 00101 1.3250 21 10101 1.7250 6 00110 1.3500 22 10110 1.7500 7 00111 1.3750 23 10111 1.7750 8 01000 1.4000 24 11000 1.8000 9 01001 1.4250 25 11001 1.8250 10 01010 1.4500 26 11010 1.8500 11 01011 1.4750 - - - 12 01100 1.5000 - - - 13 01101 1.5250 - - - 14 01110 1.5500 - - - 15 01111 1.5750 - - - Set Point SW4x[4:0] SW4x Output (V) Table 46. SW4A/B Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes V (54) mV (53) SW4A/B Buck Regulator VSW4IN VSW4ACC ISW4 ISW4PEAK iSW4 TRANSIENT VSW4OS- Operating Input Voltage • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.5 Output Voltage Accuracy • PWM mode including ripple, load regulation, and transients Nom-3% Nom Nom+3% • PFM Mode, including ripple, load regulation, and transients Nom-3% Nom Nom+3% • PWM mode (separate) - - 500 • PWM mode single/dual phase - - 1000 • PFM mode - 50 - • VIN = 3.6 V Current through Inductor (separate) - 1.0 - • Current through Inductor - 2.0 - • Single/Dual Phase - - 500 • Separate - - 250 - - 25 Continuous Output Load Current, VINMIN < BP < 4.5 V mA Current Limiter Peak Current Detection A Transient Load Change, 100 mA/µs Start-up Overshoot, IL = 100 mA/µs mA mV START MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 58 Functional Block Description Table 46. SW4A/B Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol tON-SW4 Characteristic Min Typ Max - - 500 • PLLX = 0 - 2.0 - • PLLX = 1 - 4.0 - • APS MODE, IL = 0 mA; High output voltage range (VSW4x = 3.15 V or 2.5 V) device not switching - 500 - • APS MODE, IL = 0 mA; Low output voltage range (VSW4x = 1.3 V). device not switching - 260 - • PFM MODE, IL = 0 mA; device not switching - 15 - Turn-on Time • Enable to 90% of end value IL = 0 fSW4 ISW4Q SW4 Unit Notes µs Switching Frequency MHz µA Quiescent Current Consumption Efficiency % • PFM, 3.15 V, 10 mA (A) - 79 - • PWM, 3.15 V, 50 mA (A) - 93 - • PWM, 3.15 V, 250 mA (A) - 92 - • PWM, 3.15 V, 500 mA (A) - 82 - • PFM, 1.2 V, 10 mA (B) - 72 - • PWM, 1.2 V, 50 mA (B) - 71 - • PWM, 1.2 V, 250 mA (B) - 81 - • PWM 1.2 V, 500 mA (B) - 78 - (55) Notes: 53. Transient loading for load steps of ILMAX / 2. 54. 55. When SW4A/B is set to 3.0 V and above the regulator may drop out of regulation when BP nears the output voltage. Efficiency numbers at VIN = 3.6 V, excludes the quiescent current. MC34708 59 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.5.4.7 SW5 SW5 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. BP SW5IN SW5MODE ISENSE CINSW5 SW5 Controller SW5LX Driver LSW5 COSW5 DSW5 SW5FAULT GNDSW5 Internal Compensation SW5FB SPI Interface SPI Z2 Z1 VREF EA DAC Figure 15. SW5 Block Diagram The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator will limit the current through cycle by cycle operation and alert the system through the SW5FAULT SPI bit and issue an SCPI interrupt via the INT pin. SW5 can be programmed in step sizes of 25 mV as shown in Table 47. If the software wants to change the output voltage, after power up the regulator should be forced into PWM mode to change the voltage. Table 47. SW5 Output Voltage Programmability Set Point SW5[4:0] SW5 Set Point Output (V) SW5[4:0] SW5 Output (V) 0 00000 1.2000 16 10000 1.6000 1 00001 1.2250 17 10001 1.6250 2 00010 1.2500 18 10010 1.6500 3 00011 1.2750 19 10011 1.6750 4 00100 1.3000 20 10100 1.7000 5 00101 1.3250 21 10101 1.7250 6 00110 1.3500 22 10110 1.7500 7 00111 1.3750 23 10111 1.7750 8 01000 1.4000 24 11000 1.8000 9 01001 1.4250 25 11001 1.8250 10 01010 1.4500 26 11010 1.8500 11 01011 1.4750 - - - 12 01100 1.5000 - - - 13 01101 1.5250 - - - 14 01110 1.5500 - - - 15 01111 1.5750 - - - MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 60 Functional Block Description Table 48. SW5 Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.5 Unit Notes SW5 BUCK REGULATOR VSW5IN VSW5ACC ISW5 ISW5PEAK Operating Input Voltage Output Voltage Accuracy TRANSIENT VSW5 mV • PWM mode including ripple, load regulation, and transients Nom-3% Nom Nom+3% • PFM Mode, including ripple, load regulation, and transients Nom-3% Nom Nom+3% Continuous Output Load Current, VINMIN < BP < 4.5 V - - 1000 • PFM mode - 50 - - 1.0 - - - 500 - - 25 - - 500 Current Limiter Peak Current Detection A Transient Load Change • 100 mA/µs Start-up Overshoot, IL = 0 (56) mA • PWM mode • VIN = 3.6 V Current through Inductor ISW5 V mA mV OS-START tON-SW5 Turn-on Time • Enable to 90% of end value IL = 0 fSW5 ISW5Q SW5 µs Switching Frequency MHz • PLLX = 0 - 2.0 - • PLLX = 1 - 4.0 - • APS MODE, IL = 0 mA; device not switching - 160 - • PFM MODE, IL = 0 mA; device not switching - 15 - Quiescent Current Consumption µA Efficiency % • PFM, 1.8 V, 1.0 mA - 80 - • PWM, 1.8 V, 50 mA - 79 - • PWM, 1.8 V, 500 mA - 86 - • PWM, 1.8 V, 1000 mA - 82 - (57) Notes 56. Transient Loading for load Steps of ILMAX/2 57. Efficiency numbers at VIN = 3.6 V, Excludes the quiescent current. MC34708 61 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.5.4.8 Dynamic Voltage Scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes, which could cause logic disruptions on their loads. Preset operating points for SW1A/B and SW2 can be set up for: • Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are governed by the DVS stepping rate shown in the following tables. • Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by Standby are governed by the SWxDVSSPEED[1:0] SPI bits shown in Table 49. The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2. Table 49. DVS Control Logic Table for SW1A/B and SW2 STANDBY Set Point Selected by 0 SWx[4:0] 1 SWxSTBY[4:0] Table 50. DVS Speed Selection SWxDVSSPEED[1:0] Function 00 12.5 mV step each 2.0 s 01 (default) 12.5 mV step each 4.0 s 10 12.5 mV step each 8.0 s 11 12.5 mV step each 16.0 s The regulators have a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined by the regulator in PWM mode, however, if the regulators are programmed in PFM or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0 s, SW4A/B will step in increments of 25 mV per 8.0 s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 s when SW4xHI[1:0]=00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability. The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby control. SW1 and SW2 also contain power good outputs to the application processor. The power good signal is an active high signal. When SWxPWGD is high, it means the regulator’s output has reached its programmed voltage. The SWxPWGD voltage outputs will be low during the DVS period and if the current limit is reached on the switching regulator. During the DVS period, the overcurrent condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period, the SWxPWGD pin will stay low until the current limit condition is removed. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 62 Functional Block Description Request ed Set Point   Output Voltage wit h light Load Internally Cont rolled Steps Example Actual Output Voltage Output Voltage Init ial Set Point Actual Output Voltage Internally Controlled St eps Request for Higher Voltage Voltage Change Request Possible Output Voltage Window Request for Lower Voltage I nit iated by SPI Programming, Standby Control SWxP WGD Figure 16. Voltage Stepping with DVS 7.5.5 Boost Switching Regulator SWBST is a boost switching regulator with a programmable output, which defaults to 5.0 V on power up, operating at 2.0 MHz. SWBST supplies the VUSB regulator for the USB PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator will cause the output voltage and SWBSTFB to sit at a Schottky drop below the battery voltage whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky diode, inductor, and capacitor are required. VIN CINBST VOBST LBST SWBSTIN DBST SWBSTMODE SWBSTLX Driver GNDSWBST OC RSENSE VREFSC Controller SWBSTFAULT SPI/I2C Interface SC VREFUV UV SWBSTFB COSWBST Internal Compensation Z2 Z1 EA VREF Figure 17. Boost Regulator Architecture SWBST output voltage programmable via the SWBST[1:0] SPI bits as shown in Table 51. MC34708 63 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description Table 51. SWBST Voltage Programming Parameter Voltage SWBST Output Voltage SWBST[1:0] 00 5.000 (default) 01 5.050 10 5.100 11 5.150 SWBST can be controlled by SPI programming in PFM, APS, and Auto mode. Auto mode transitions between PFM and APS mode based on the load current. By default SWBST is powered up in Auto mode. Table 52. SWBST Mode Control Parameter Voltage SWBST Mode SWBSTMODE[1:0] 00 Off SWBSTSTBYMODE[1:0] 01 PFM 10 Auto (default) 11 APS Table 53. SWBST Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes V (58) SWITCH MODE SUPPLY SWBST VSWBST Average Output Voltage • 3.0 V < VIN < 4.5 V, 0 < IL < ILMAX VSWBSTACC Output Ripple • 3.0 V < VIN < 4.5 V 0 < IL < ILMAX, excluding reverse recovery of Schottky diode SWBSTACC Average Load Regulation • VIN = 3.6 V, 0 < IL < ILMAX VSWBST LINEAREG ISWBST Nom-4% VNOM Nom+3% - - 120 mV - 0.5 - - 50 - Vp-p mV/mA Average Line Regulation • 3.0 V < VIN < 4.5 V IL = ILMAX mV Continuous Load Current • 3.0 V < VIN < 4.5 V, VOUT = 5.0 V mA - 380 - ISWBSTPEAK Peak Current Limit • At SWBSTIN, VIN = 3.6 V - 1800 - VSWBSTOS- - - 500 - - 2.0 - 2.0 - - - 300 Start-up Overshoot, IL = 0 mA mA mV START tON-SWBST Turn-on Time • Enable to 90% of VOUT IL = 0 fSWBST Switching Frequency VSWBST Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs TRANSIENT • Maximum transient Amplitude ms MHz mV MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 64 Functional Block Description Table 53. SWBST Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol VSWBST TRANSIENT VSWBST TRANSIENT VSWBST TRANSIENT SWBST ISWBSTBIAS Characteristic Min Typ Max - - 300 - - 500 Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs • Maximum transient Amplitude µs Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs • Time to settle 80% of transient Efficiency, IL = ILMAX ms - - 20 65 80 - - 35 - - 1.0 6.0 Bias Current Consumption • PFM or Auto mode ILEAK-SWBST NMOS Off Leakage • SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 0 Notes mV Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs • Time to settle 80% of transient Unit % µA µA Notes: 58. VIN is the low side of the inductor connected to BP. 7.5.6 Linear Regulators (LDOs) This section describes the linear regulators provided. For convenience, these regulators are named to indicate their typical or possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regulator capabilities. A low power standby mode controlled by STANDBY is provided for the regulators with an external pass device in which the bias current is aggressively reduced. This mode is useful for deep sleep operation, where certain supplies cannot be disabled, but active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited in this mode. 7.5.6.1 General Guidelines The following applies to all linear regulators, unless otherwise specified. • Parametric specifications assume the use of low ESR X5R/X7R ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider temperature variation may require a larger room temperature nominal capacitance value, to meet performance specs over temperature. Capacitor derating as a function of DC bias voltage requires special attention. Minimum bypass capacitor guidelines are provided for stability and transient performance. However, larger values may be applied, but performance metrics may be altered and generally improved and should be confirmed in system applications. • Regulators with an external PNP transistor require an equivalent resistance (including the ESR) in series with the output capacitor, as noted in the specific regulator sections. • Output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static line regulation, and static load regulation. • In the Low-power mode, the output performance is degraded. Only those parameters listed in the Low-power mode section are guaranteed. In this mode, the output current is limited to much lower levels than in the active mode. • When a regulator gets disabled, the output will be pulled to ground by an internal pull-down. The pull-down is also activated when RESETB goes low. MC34708 65 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Description 7.5.6.2 LDO Regulator Control The regulators with embedded pass devices (VPLL, VGEN1, and VUSB) have an adaptive biasing scheme thus, there are no distinct operating modes such as a Normal mode and a Low Power mode. Therefore, no specific control is required to put these regulators in a Low Power mode. The external pass regulator (VDAC) can also operate in a normal and low power mode. However, since a load current detection cannot be performed for this regulator, the transition between both modes is not automatic and is controlled by setting the corresponding mode bits for the operational behavior desired. The regulators VUSB2, and VGEN2 can be configured for using the internal pass device or external pass device as explained in Supplies. For both configurations, the transition between both modes is controlled by setting the VxMODE bit for the specific regulator. Therefore, depending on the configuration selected, the automatic Low Power mode determines availability. The regulators can be disabled and the general purpose outputs can be forced low when going into Standby (note that the Standby response timing can be altered with the STBYDLY function, as described in the previous section). Each regulator has an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The actual operating mode of the regulators as a function of STANDBY is not reflected through SPI. In other words, the SPI will read back what is programmed, not the actual state. Table 54. LDO Regulator Control (external pass device LDOs) VxEN VxMODE VxSTBY STANDBY(59) Regulator Vx 0 X X X Off 1 0 0 X On 1 1 0 X Low Power 1 X 1 0 On 1 0 1 1 Off 1 1 1 1 Low Power Notes 59. STANDBY refers to a Standby event as described earlier For regulators with internal pass devices, the previous table can be simplified by elimination of the VxMODE column. Table 55. LDO Regulator Control (internal pass device LDOs) VxEN VxSTBY STANDBY (60) Regulator Vx 0 X X Off 1 0 X On 1 1 0 On 1 1 1 Off Notes 60. STANDBY refers to a Standby event as described earlier 7.5.6.3 Transient Response Waveforms The transient load and line response are specified with the waveforms as depicted in Figure 18. Note that where the transient load response refers to the overshoot only, so excluding the DC shift itself, the transient line response refers to the sum of both overshoot and DC shift. This is also valid for the mode transition response. MC34708 Analog Integrated Circuit Device Data Freescale Semiconductor 66 Functional Block Description   VNOM + 0.8V  VIN IMAX   ILOAD VNOM + 0.3V   0 mA  10us  10us  1us  VIN Stimulus for Transient Line Response IL = 0 mA  1us ILOAD Stimulus for Transient Load Response IL = IMAX   Overshoot  VOUT Overshoot  VOUT for Transient Load Response Active Mode Active Mode Low Power Mode Overshoot  VOUT Mode Transition  Time Overshoot  IL