MC88LV926DWR2

MOTOROLA Order this document by MC88LV926/D SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL 68060 Clock Driver The MC88LV926 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040/060 microprocessor family. To support the 68060 processor, the 88LV926 operates from a 3.3V as well as a 5.0V supply. MC88LV926 LOW SKEW CMOS PLL 68060 CLOCK DRIVER The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. • 2X_Q Output Meets All Requirements of the 50 and 66MHz 68060 Microprocessor PCLK Input Specifications • • • • Low Voltage 3.3V VCC • • • • SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 20 1 Three Outputs (Q0–Q2) With Output–Output Skew 1500 V DC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)4 Symbol Parameter VCC Guaranteed Limits Unit VIH Minimum High Level Input Voltage4 3.0 3.3 2.0 2.0 V VOUT = 0.1V or VCC – 0.1V VIL Minimum Low Level Input Voltage 3.0 3.3 0.8 0.8 V VOUT = 0.1V or VCC – 0.1V VOH Minimum High Level Output Voltage 3.0 3.3 2.2 2.5 V VIN = VIH or VIL IOH –24mA –24mA VOL Minimum Low Level Output Voltage 3.0 3.3 0.55 0.55 V VIN = VIH or VIL IOH +24mA1 +24mA IIN Maximum Input Leakage Current 3.3 ±1.0 µA VI = VCC, GND mA VI = VCC – 2.1V ICCT Maximum ICC/Input 3.3 2.0 2 IOLD Minimum Dynamic3 Output Current 3.3 50 mA VOLD = 1.25V Max 3.3 –50 mA VOHD = 2.35 Min 3.3 750 µA VI = VCC, GND IOHD ICC 1. 2. 3. 4. Condition Maximum Quiescent Supply Current IOL is +12mA for the RST_OUT output. The PLL_EN input pin is not guaranteed to meet this specification. Maximum test duration 2.0ms, one output loaded at a time. The MC88LV926 can also be operated from a 5.0V supply. VOH output levels will vary 1:1 with VCC, input levels and current specs will be unchanged, except VIH; when VCC > 4.0 volts, VIH minimum level is 2.7 volts. TIMING SOLUTIONS 3 MOTOROLA MC88LV926 RST_OUT RST_IN LOCK INDICATOR RESET_OUT Q 2X_Q Q Q0 Q Q1 Q Q2 Q Q3 ÷2 R SYNC1 CH PUMP PFD VCO ÷4 R PLL_EN 0 1 ÷4 R ÷8 ÷4 R ÷4 R POWER–ON RESET DELAY CLKEN ÷4 R MR Figure 1. MC88LV926 Logic Block Diagram SYNC INPUT TIMING REQUIREMENTS Symbol Parameter tRISE/FALL SYNC Input Rise/Fall Time, SYNC Input From 0.8V to 2.0V tCYCLE, SYNC Input Input Clock Period SYNC Input1 Duty Cycle Duty Cycle, SYNC Input Minimum Maximum Unit — 5.0 ns 1 f2X_Qń4 2001 ns 50% ± 25% 1. When VCC > 4.0 volts, Maximum SYNC Input Period is 125ns. FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V or 5.0V ±5%) Symbol Parameter Guaranteed Minimum Unit Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 66 MHz Fmax (‘Q’) Maximum Operating Frequency, Q0–Q3 Outputs 33 MHz Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition. MOTOROLA 4 TIMING SOLUTIONS MC88LV926 AC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V or 5.0V ±5%) Symbol Parameter Mimimum Maximum Unit Condition tRISE/FALL All Outputs Rise/Fall Time, into 50Ω Load 0.3 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V tRISE/FALL 2X_Q Output Rise/Fall Time into a 50Ω Load 0.5 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V tpulse width(a)1 (Q0, Q1, Q2, Q3) Output Pulse Width Q0, Q1, Q2, Q3 at 1.65V 0.5tcycle – 0.5 0.5tcycle + 0.5 ns 50Ω Load Terminated to VCC/2 (See Application Note 3) tpulse width(b)1 (2X_Q Output) Output Pulse Width 2X_Q at 1.65V 0.5tcycle – 0.5 0.5tcycle + 0.5 ns 50Ω Load Terminated to VCC/2 (See Application Note 3) tSKEWr2 (Rising) Output–to–Output Skew Between Outputs Q0–Q2 (Rising Edge Only) — 500 ps Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 5.) tSKEWf2 (Falling) Output–to–Output Skew Between Outputs Q0–Q2 (Falling Edge Only) — 1.0 ns Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 5.) tSKEWall2 Output–to–Output Skew 2X_Q, Q0–Q2, Q3 — 750 ps Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 5.) tSKEW QCLKEN1,2 Output–to–Output Skew 2X_Q = 50MHz QCLKEN to 2X_Q 2X_Q = 66MHz ns 9.76 7.06 — Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 5.) tLOCK3 Phase–Lock Acquisition Time, All Outputs to SYNC Input 1 10 ms tPHL MR – Q1 Propagation Delay, MR to Any Output (High–Low) 1.5 13.5 ns tREC, MR to SYNC5, 1 Reset Recovery Time rising MR edge to falling SYNC edge 9 — ns tW, MR LOW5, 1 Minimum Pulse Width, MR input Low 5 — ns tW, RST_IN LOW1 tPZL1 Minimum Pulse Width, RST_IN Low 10 — ns When in Phase–Lock Output Enable Time RST_IN Low to RST_OUT Low 1.5 16.5 ns See Application Note 5 tPLZ1 Output Enable Time RST_IN High to RST_OUT High Z 1016 ‘Q’ Cycles (508 Q/2 Cycles) 1024 ‘Q’ Cycles (512 Q/2 Cycles) ns See Application Note 5 Into a 50Ω Load Terminated to VCC/2 1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this methodology. 2. Under equally loaded conditions and at a fixed temperature and voltage. 3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1µF; tLOCK Min is with C1 = 0.01µF. 4. See Application Note 4 for the distribution in time of each output referenced to SYNC. 5. Specification is valid only when the PLL_EN pin is low. 6. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060. TIMING SOLUTIONS 5 MOTOROLA MC88LV926 Application Notes 2. A 470KΩ resistor tied to either Analog VCC or Analog GND, as shown in Figure 2., is required to ensure no jitter is present on the MC88LV926 outputs. This technique causes a phase offset between the SYNC input and the Q0 output, measured at the pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were arrived at by measuring the phase relationship for the 14 lots described in note 1 while the part was in phase–locked operation. The actual measurements were made with a 10MHz SYNC input (1.0ns edge rate from 0.8V to 2.0V). The phase measurements were made at 1.5V. See Figure 2. for a graphical description. 1. Several specifications can only be measured when the MC88LV926 is in phase–locked operation. It is not possible to have the part in phase–lock on ATE (automated test equipment). Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88LV926 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. Response Surface Modeling (RSM) techniques were used to relate IC performance to the CMOS transistor properties over operation voltage and temperature. IC performance to each specification and fab variation were used in conjunction with Yield Surface Modeling (YSM) methodology to set performance limits of ATE testable specifications within those which are to be guaranteed by statistical characterization. In this way, all units passing the ATE test will meet or exceed the non–tested specifications limits. 3. Two specs (tRISE/FALL and tPULSE Width 2X_Q output, see AC Specifications) guarantee that the MC88LV926 meets the 33MHz and 66MHz 68060 P–Clock input specification. RC1 EXTERNAL LOOP FILTER 330Ω 0.1µF ANALOG VCC 470K REFERENCE RESISTOR R2 C1 470K REFERENCE RESISTOR RC1 330Ω 0.1µF ANALOG GND R2 C1 ANALOG GND WITH THE 470KΩ RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: WITH THE 470KΩ RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: tPD = 2.25ns ± 1.0ns (TYPICAL VALUES) 3V tPD = –0.80ns ± 0.30ns 3V SYNC INPUT SYNC INPUT 2.25ns OFFSET –0.8ns OFFSET 5V 5V Q0 OUTPUT Q0 OUTPUT Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present When a 470KΩ Resistor Is Tied to VCC or Ground MOTOROLA 6 TIMING SOLUTIONS MC88LV926 RST_OUT PIN VCC 1K INTERNAL LOGIC CL ANALOG GND Figure 3. RST_OUT Test Circuit 2X_Q 12.5MHz CRYSTAL OSCILLATOR Q0 Q1 Q2 SYNC MR PLL_EN RST_IN Q3 QCLKEN RST_OUT 66MHz P–CLOCK OUTPUT 33MHz B–CLOCK AND SYSTEM OUTPUTS DELAY 33MHz CLKEN OUTPUT Figure 4. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships SYNC Input tCYCLE SYNC Input tSKEWall tSKEWf tSKEWr tSKEWf tSKEWr Q0–Q3 Outputs tCYCLE ‘Q’ Outputs 2X_Q Output QCLKEN tSKEWQCLKEN tSKEWQCLKEN Figure 5. Output/Input Switching Waveforms and Timing Relationships Timing Notes 1. The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as ‘windows’, not as a ± deviation around a center point. TIMING SOLUTIONS 7 MOTOROLA MC88LV926 5. The RST_OUT pin is an open drain N–Channel output. Therefore an external pull–up resistor must be provide to pull up the RST_OUT pin when it goes into the high impedance state (after the MC88LV926 is phase–locked to the reference input with RST_IN held high or 1024 ‘Q’ cycles after the RST_IN pin goes high when the part is locked). In the tPLZ and tPZL specifications, a 1KΩ resistor is used as a pull–up as shown in Figure 3. The tPD spec includes the full temperature range from 0°C to 70°C and the full VCC range from 3.0V to 3.3V. If the ∆T and ∆VCC is a given system are less than the specification limits, the tPD spec window will be reduced. The tPD window for a given ∆T and ∆VCC is given by the following regression formula: TBD Notes Concerning Loop Filter and Board Layout Issues 1. Figure 6. shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter–free operation: purpose of the bypass filtering scheme shown in Figure 6. is to give the 88LV926 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1c. There are no special requirements set forth for the loop filter resistors (470K and 330Ω). The loop filter capacitor (0.1uF) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 1b. The 47Ω resistors, the 10µF low frequency bypass capacitor, and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will make the 88LV926 PLL insensitive to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100ps phase deviation on the 88LV926 outputs. A 250mV step deviation on VCC using the recommended filter values will cause no more than a 250ps phase deviation; if a 25µF bypass capacitor is used (instead of 10µF) a 250mV VCC step will cause no more than a 100ps phase deviation. 1d. The 470K reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead–band. If the VCO (2X_Q output) is running above 40MHz, the 470K resistor provides the correct amount of current injection into the charge pump (2–3µA). If the VCO is running below 40MHz, a 1MΩ reference resistor should be used (instead of 470K). 2. In addition to the bypass capacitors used in the analog filter of Figure 6., there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88LV926 outputs, in addition to reducing potential for noise in the ‘analog’ section of the chip. These bypass capacitors should also be tied as close to the 88LV926 package as possible. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88LV926’s digital VCC supply. The BOARD VCC NOTE: FURTHER LOOP OPTIMIZATION MAY OCCUR 47Ω 470K 10µF LOW FREQ BIAS 5 ANALOG VCC 6 RC1 7 ANALOG GND 330Ω 0.1µF HIGH FREQ BIAS 0.1µF (LOOP FILTER CAP) ANALOG LOOP FILTER/VCO SECTION OF THE MC88LV926 20–PIN SOIC PACKAGE (NOT DRAWN TO SCALE) 47Ω BOARD GND A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES IS ALL THAT IS NECESSARY TO USE THE MC88LV926 IN A NORMAL DIGITAL ENVIRONMENT. Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926 MOTOROLA 8 TIMING SOLUTIONS MC88LV926 MC68060 16.67MHz X–TAL OSCILLATOR SYNC SYSTEM RESET RST_IN 2X_Q QCLKEN Q0 Q1 Q2 Q3 66MHz ASIC PCLK CLKEN RESET ASIC 33MHz RST_OUT MEMORY MODULE Figure 7. Typical MC88LV926/MC68060 System Configuration TIMING SOLUTIONS 9 MOTOROLA MC88LV926 OUTLINE DIMENSIONS DW SUFFIX SOIC PACKAGE CASE 751D-06 ISSUE G D A 20 10X 0.25 M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 H M B E M 1 10 h 20X B 0.25 X 45 _ B M T A B A 18X MOTOROLA e A1 L SEATING PLANE q C T 10 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.40 1.00 0_ 7_ TIMING SOLUTIONS MC88LV926 NOTES TIMING SOLUTIONS 11 MOTOROLA MC88LV926 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Technical Information Center: 1–800–521–6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ 12 TIMING SOLUTIONS MC88LV926/D