Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806: Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
Package Description
Original (gold wire)
Current (copper wire)
package document number package document number
48 QFN
98ARH99048A
98ASA00466D
MC9RS08LA8
48 QFN
98ARL10606D
98ASA00466D
MC9S08GT16A
32 QFN
98ARH99035A
98ASA00473D
MC9S908QE32
32 QFN
98ARE10566D
98ASA00473D
MC9S908QE8
32 QFN
98ASA00071D
98ASA00736D
MC9S08JS16
24 QFN
98ARL10608D
98ASA00734D
MC9S08QG8
24 QFN
98ARL10605D
98ASA00474D
MC9S08SH8
24 QFN
98ARE10714D
98ASA00474D
MC9RS08KB12
24 QFN
98ASA00087D
98ASA00602D
MC9S08QG8
16 QFN
98ARE10614D
98ASA00671D
MC9RS08KB12
8 DFN
98ARL10557D
98ASA00672D
6 DFN
98ARL10602D
98ASA00735D
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9S08QB8
MC9S08QG8
MC9RS08KA2
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
MC9S08AC60
MC9S08AC48
MC9S08AC32
Data Sheet
HCS08
Microcontrollers
MC9S08AC60
Rev. 3
8/2011
freescale.com
MC9S08AC60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
•
•
•
40-MHz HCS08 CPU (central processor unit)
20-MHz internal bus frequency
HC08 instruction set with added BGND instruction
Peripherals
•
•
Development Support
•
•
•
•
Background debugging system
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
On-chip in-circuit emulator (ICE) Debug module
containing two comparators and nine trigger
modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data.
Supports both tag and force breakpoints.
Support for up to 32 interrupt/reset sources
•
•
•
Memory Options
•
•
Up to 60 KB of on-chip FLASH memory with
security options
Up to 2 KB of on-chip RAM
Clock Source Options
•
Clock source options include crystal, resonator,
external clock, or internally generated clock with
precision NVM trimming using ICG module
System Protection
•
•
•
•
Optional watchdog computer operating properly
(COP) reset with option to run from independent
1kHz internal clock source or bus clock
Low-voltage detection with reset or interrupt
Illegal opcode detection with reset
Cyclic Redundancy Check (CRC) Module to
support fast cyclic redundancy checks on
memory.
Power-Saving Modes
•
Wait plus two stops
•
•
ADC — Up to 16-channel, 10-bit analog-to-digital
converter with automatic compare function
SCI — Two serial communications interface
modules with optional 13-bit break. supports LIN
2.0 Protocol and SAE J2602; Master extended
break generation; Slave extended break detection
SPI — Serial peripheral interface module
IIC — Inter-integrated circuit bus module to
operate at up to 100 kbps with maximum bus
loading; capable of higher baudrates with reduced
loading. 10-bit address extension option.
Timers — Up to two 2-channel and one 6-channel
16-bit timer/pulse-width modulator (TPM) module:
Selectable input capture, output compare, and
edge-aligned PWM capability on each channel.
Each timer module may be configured for
buffered, centered PWM (CPWM) on all channels
KBI — Up to 8-pin keyboard interrupt module
CRC - Hardware CRC generation using a 16-bit
shift register
Input/Output
•
•
•
•
•
•
Up to 54 general-purpose input/output (I/O) pins
Software selectable pullups on ports when used
as inputs
Software selectable slew rate control on ports
when used as outputs
Software selectable drive strength on ports when
used as outputs
Master reset pin and power-on reset (POR)
Internal pullup on RESET, IRQ, and BKGD/MS
pins to reduce customer system cost
Package Options
•
•
•
•
•
64-pin quad flat package (QFP)
64-pin low-profile quad flat package (LQFP)
48-pin quad flat pack no lead package (QFN)
44-pin low-profile quad flat package (LQFP)
32-pin low-profile quad flat package (LQFP)
MC9S08AC60 Series Data Sheet
Covers MC9S08AC60
MC9S08AC48
MC9S08AC32
MC9S08AC60 Series
Rev. 3
8/2011
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision
Number
Revision
Date
1
2/2008
Preliminary customer release.
2
3/2008
Market Launch Release.
8/2011
Added VBG and IIC in the Table A-6.
Added two figures of Figure 4-2 and Figure 4-3 to replace the old figure of “FLASH
Program and Erase Flowchart”.
Updated Table 15-8.
Updated RIDD in the Table A-7.
Updated tRTI in the Table A-12.
3
Description of Changes
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2008-2011. All rights reserved.
MC9S08AC60 Series Data Sheet, Rev. 3
6
Freescale Semiconductor
List of Chapters
Chapter
Title
Page
Chapter 1
Introduction.............................................................................. 19
Chapter 2
Pins and Connections ............................................................. 25
Chapter 3
Modes of Operation ................................................................. 35
Chapter 4
Memory ..................................................................................... 41
Chapter 5
Resets, Interrupts, and System Configuration ..................... 67
Chapter 6
Parallel Input/Output ............................................................... 85
Chapter 7
Central Processor Unit (S08CPUV2) .................................... 109
Chapter 8
Cyclic Redundancy Check (S08CRCV1).............................. 129
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)........................ 137
Chapter 10
Internal Clock Generator (S08ICGV4) .................................. 165
Chapter 11
Inter-Integrated Circuit (S08IICV2) ....................................... 193
Chapter 12
Keyboard Interrupt (S08KBIV1) ............................................ 211
Chapter 13
Serial Communications Interface (S08SCIV4)..................... 217
Chapter 14
Serial Peripheral Interface (S08SPIV3) ................................ 237
Chapter 15
Timer/PWM (S08TPMV3) ....................................................... 253
Chapter 16
Development Support ........................................................... 283
Appendix A
Electrical Characteristics and Timing Specifications ....... 305
Appendix B
Ordering Information and Mechanical Drawings............... 333
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
7
Contents
Section Number
Title
Page
Chapter 1
Introduction
1.1
1.2
1.3
Overview .........................................................................................................................................19
MCU Block Diagrams .....................................................................................................................20
System Clock Distribution ..............................................................................................................22
Chapter 2
Pins and Connections
2.1
2.2
2.3
Introduction .....................................................................................................................................25
Device Pin Assignment ...................................................................................................................25
Recommended System Connections ...............................................................................................29
2.3.1 Power (VDD, VSS, VDDAD, VSSAD) .................................................................................31
2.3.2 Oscillator (XTAL, EXTAL) ..............................................................................................31
2.3.3 RESET Pin ........................................................................................................................31
2.3.4 Background/Mode Select (BKGD/MS) ............................................................................32
2.3.5 ADC Reference Pins (VREFH, VREFL) .............................................................................32
2.3.6 External Interrupt Pin (IRQ) .............................................................................................32
2.3.7 General-Purpose I/O and Peripheral Ports ........................................................................33
Chapter 3
Modes of Operation
3.1
3.2
3.3
3.4
3.5
3.6
Introduction .....................................................................................................................................35
Features ...........................................................................................................................................35
Run Mode ........................................................................................................................................35
Active Background Mode ...............................................................................................................35
Wait Mode .......................................................................................................................................36
Stop Modes ......................................................................................................................................36
3.6.1 Stop2 Mode .......................................................................................................................37
3.6.2 Stop3 Mode .......................................................................................................................38
3.6.3 Active BDM Enabled in Stop Mode .................................................................................38
3.6.4 LVD Enabled in Stop Mode ..............................................................................................39
3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................39
Chapter 4
Memory
4.1
MC9S08AC60 Series Memory Map ...............................................................................................41
4.1.1 Reset and Interrupt Vector Assignments ...........................................................................43
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
9
Section Number
4.2
4.3
4.4
4.5
4.6
Title
Page
Register Addresses and Bit Assignments ........................................................................................44
RAM ................................................................................................................................................50
FLASH ............................................................................................................................................51
4.4.1 Features .............................................................................................................................51
4.4.2 Program and Erase Times .................................................................................................51
4.4.3 Program and Erase Command Execution .........................................................................52
4.4.4 Burst Program Execution ..................................................................................................54
4.4.5 Access Errors ....................................................................................................................57
4.4.6 FLASH Block Protection ..................................................................................................57
4.4.7 Vector Redirection ............................................................................................................58
Security ............................................................................................................................................58
FLASH Registers and Control Bits .................................................................................................59
4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................59
4.6.2 FLASH Options Register (FOPT and NVOPT) ................................................................61
4.6.3 FLASH Configuration Register (FCNFG) .......................................................................61
4.6.4 FLASH Protection Register (FPROT and NVPROT) ......................................................63
4.6.5 FLASH Status Register (FSTAT) ......................................................................................63
4.6.6 FLASH Command Register (FCMD) ...............................................................................64
Chapter 5
Resets, Interrupts, and System Configuration
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Introduction .....................................................................................................................................67
Features ...........................................................................................................................................67
MCU Reset ......................................................................................................................................67
Computer Operating Properly (COP) Watchdog .............................................................................68
Interrupts .........................................................................................................................................69
5.5.1 Interrupt Stack Frame .......................................................................................................70
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................70
5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................71
Low-Voltage Detect (LVD) System ................................................................................................73
5.6.1 Power-On Reset Operation ...............................................................................................73
5.6.2 LVD Reset Operation ........................................................................................................73
5.6.3 LVD Interrupt Operation ...................................................................................................73
5.6.4 Low-Voltage Warning (LVW) ...........................................................................................73
Real-Time Interrupt (RTI) ...............................................................................................................73
MCLK Output .................................................................................................................................74
Reset, Interrupt, and System Control Registers and Control Bits ...................................................74
5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................75
5.9.2 System Reset Status Register (SRS) .................................................................................76
5.9.3 System Background Debug Force Reset Register (SBDFR) ............................................77
5.9.4 System Options Register (SOPT) .....................................................................................77
5.9.5 System MCLK Control Register (SMCLK) .....................................................................78
MC9S08AC60 Series Data Sheet, Rev. 3
10
Freescale Semiconductor
Section Number
5.9.6
5.9.7
5.9.8
5.9.9
5.9.10
Title
Page
System Device Identification Register (SDIDH, SDIDL) ................................................79
System Real-Time Interrupt Status and Control Register (SRTISC) ................................80
System Power Management Status and Control 1 Register (SPMSC1) ...........................81
System Power Management Status and Control 2 Register (SPMSC2) ...........................82
System Options Register 2 (SOPT2) ................................................................................83
Chapter 6
Parallel Input/Output
6.1
6.2
6.3
6.4
6.5
6.6
Introduction .....................................................................................................................................85
Pin Descriptions ..............................................................................................................................85
Parallel I/O Control .........................................................................................................................85
Pin Control ......................................................................................................................................86
6.4.1 Internal Pullup Enable ......................................................................................................87
6.4.2 Output Slew Rate Control Enable .....................................................................................87
6.4.3 Output Drive Strength Select ............................................................................................87
Pin Behavior in Stop Modes ............................................................................................................88
Parallel I/O and Pin Control Registers ............................................................................................88
6.6.1 Port A I/O Registers (PTAD and PTADD) ........................................................................88
6.6.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) .................................................89
6.6.3 Port B I/O Registers (PTBD and PTBDD) ........................................................................91
6.6.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) .................................................92
6.6.5 Port C I/O Registers (PTCD and PTCDD) ........................................................................94
6.6.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) .................................................95
6.6.7 Port D I/O Registers (PTDD and PTDDD) .......................................................................97
6.6.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) ................................................98
6.6.9 Port E I/O Registers (PTED and PTEDD) ......................................................................100
6.6.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) ................................................101
6.6.11 Port F I/O Registers (PTFD and PTFDD) .......................................................................103
6.6.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) .................................................104
6.6.13 Port G I/O Registers (PTGD and PTGDD) .....................................................................106
6.6.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ..............................................107
Chapter 7
Central Processor Unit (S08CPUV2)
7.1
7.2
Introduction ...................................................................................................................................109
7.1.1 Features ...........................................................................................................................109
Programmer’s Model and CPU Registers .....................................................................................110
7.2.1 Accumulator (A) .............................................................................................................110
7.2.2 Index Register (H:X) ......................................................................................................110
7.2.3 Stack Pointer (SP) ........................................................................................................... 111
7.2.4 Program Counter (PC) .................................................................................................... 111
7.2.5 Condition Code Register (CCR) .....................................................................................111
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
11
Section Number
7.3
7.4
7.5
Title
Page
Addressing Modes .........................................................................................................................112
7.3.1 Inherent Addressing Mode (INH) ...................................................................................113
7.3.2 Relative Addressing Mode (REL) ..................................................................................113
7.3.3 Immediate Addressing Mode (IMM) ..............................................................................113
7.3.4 Direct Addressing Mode (DIR) ......................................................................................113
7.3.5 Extended Addressing Mode (EXT) ................................................................................113
7.3.6 Indexed Addressing Mode ..............................................................................................113
Special Operations .........................................................................................................................114
7.4.1 Reset Sequence ...............................................................................................................115
7.4.2 Interrupt Sequence ..........................................................................................................115
7.4.3 Wait Mode Operation ......................................................................................................116
7.4.4 Stop Mode Operation ......................................................................................................116
7.4.5 BGND Instruction ...........................................................................................................116
HCS08 Instruction Set Summary ..................................................................................................117
Chapter 8
Cyclic Redundancy Check (S08CRCV1)
8.1
8.2
8.3
8.4
8.5
Introduction ...................................................................................................................................129
8.1.1 Features ...........................................................................................................................129
8.1.2 Modes of Operation ........................................................................................................131
8.1.3 Block Diagram ................................................................................................................131
External Signal Description ..........................................................................................................131
Register Definition .......................................................................................................................132
8.3.1 Memory Map ..................................................................................................................132
8.3.2 Register Descriptions ......................................................................................................132
Functional Description ..................................................................................................................133
8.4.1 ITU-T (CCITT) recommendations & expected CRC results ..........................................134
Initialization Information ..............................................................................................................134
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)
9.1
9.2
9.3
Overview .......................................................................................................................................137
Channel Assignments ....................................................................................................................137
9.2.1 Alternate Clock ...............................................................................................................138
9.2.2 Hardware Trigger ............................................................................................................138
9.2.3 Temperature Sensor ........................................................................................................139
9.2.4 Features ...........................................................................................................................141
9.2.5 Block Diagram ................................................................................................................141
External Signal Description ..........................................................................................................142
9.3.1 Analog Power (VDDAD) ..................................................................................................143
9.3.2 Analog Ground (VSSAD) .................................................................................................143
9.3.3 Voltage Reference High (VREFH) ...................................................................................143
MC9S08AC60 Series Data Sheet, Rev. 3
12
Freescale Semiconductor
Section Number
9.4
9.5
9.6
9.7
Title
Page
9.3.4 Voltage Reference Low (VREFL) ....................................................................................143
9.3.5 Analog Channel Inputs (ADx) ........................................................................................143
Register Definition ........................................................................................................................143
9.4.1 Status and Control Register 1 (ADCSC1) ......................................................................143
9.4.2 Status and Control Register 2 (ADCSC2) ......................................................................145
9.4.3 Data Result High Register (ADCRH) .............................................................................146
9.4.4 Data Result Low Register (ADCRL) ..............................................................................146
9.4.5 Compare Value High Register (ADCCVH) ....................................................................147
9.4.6 Compare Value Low Register (ADCCVL) .....................................................................147
9.4.7 Configuration Register (ADCCFG) ................................................................................147
9.4.8 Pin Control 1 Register (APCTL1) ..................................................................................149
9.4.9 Pin Control 2 Register (APCTL2) ..................................................................................150
9.4.10 Pin Control 3 Register (APCTL3) ..................................................................................151
Functional Description ..................................................................................................................152
9.5.1 Clock Select and Divide Control ....................................................................................152
9.5.2 Input Select and Pin Control ...........................................................................................153
9.5.3 Hardware Trigger ............................................................................................................153
9.5.4 Conversion Control .........................................................................................................153
9.5.5 Automatic Compare Function .........................................................................................156
9.5.6 MCU Wait Mode Operation ............................................................................................156
9.5.7 MCU Stop3 Mode Operation ..........................................................................................156
9.5.8 MCU Stop1 and Stop2 Mode Operation .........................................................................157
Initialization Information ..............................................................................................................157
9.6.1 ADC Module Initialization Example .............................................................................157
Application Information ................................................................................................................159
9.7.1 External Pins and Routing ..............................................................................................159
9.7.2 Sources of Error ..............................................................................................................161
Chapter 10
Internal Clock Generator (S08ICGV4)
10.1 Introduction ...................................................................................................................................165
10.1.1 Features ...........................................................................................................................168
10.1.2 Modes of Operation ........................................................................................................168
10.1.3 Block Diagram ................................................................................................................169
10.2 External Signal Description ..........................................................................................................170
10.2.1 EXTAL — External Reference Clock / Oscillator Input ................................................170
10.2.2 XTAL — Oscillator Output ............................................................................................170
10.2.3 External Clock Connections ...........................................................................................170
10.2.4 External Crystal/Resonator Connections ........................................................................170
10.3 Register Definition ........................................................................................................................171
10.3.1 ICG Control Register 1 (ICGC1) ....................................................................................171
10.3.2 ICG Control Register 2 (ICGC2) ....................................................................................173
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
13
Section Number
Title
Page
10.3.3 ICG Status Register 1 (ICGS1) .......................................................................................174
10.3.4 ICG Status Register 2 (ICGS2) .......................................................................................175
10.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................175
10.3.6 ICG Trim Register (ICGTRM) ........................................................................................176
10.4 Functional Description ..................................................................................................................176
10.4.1 Off Mode (Off) ................................................................................................................177
10.4.2 Self-Clocked Mode (SCM) .............................................................................................177
10.4.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................178
10.4.4 FLL Engaged Internal Unlocked ....................................................................................179
10.4.5 FLL Engaged Internal Locked ........................................................................................179
10.4.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................179
10.4.7 FLL Engaged, External Clock (FEE) Mode ...................................................................179
10.4.8 FLL Lock and Loss-of-Lock Detection ..........................................................................180
10.4.9 FLL Loss-of-Clock Detection .........................................................................................181
10.4.10Clock Mode Requirements .............................................................................................182
10.4.11Fixed Frequency Clock ...................................................................................................183
10.4.12High Gain Oscillator .......................................................................................................183
10.5 Initialization/Application Information ..........................................................................................183
10.5.1 Introduction .....................................................................................................................183
10.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................185
10.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................187
10.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................189
10.5.5 Example #4: Internal Clock Generator Trim ..................................................................191
Chapter 11
Inter-Integrated Circuit (S08IICV2)
11.1 Introduction ...................................................................................................................................193
11.1.1 Features ...........................................................................................................................195
11.1.2 Modes of Operation ........................................................................................................195
11.1.3 Block Diagram ................................................................................................................195
11.2 External Signal Description ..........................................................................................................196
11.2.1 SCL — Serial Clock Line ...............................................................................................196
11.2.2 SDA — Serial Data Line ................................................................................................196
11.3 Register Definition ........................................................................................................................196
11.3.1 IIC Address Register (IICA) ...........................................................................................197
11.3.2 IIC Frequency Divider Register (IICF) ..........................................................................197
11.3.3 IIC Control Register (IICC1) ..........................................................................................200
11.3.4 IIC Status Register (IICS) ...............................................................................................200
11.3.5 IIC Data I/O Register (IICD) ..........................................................................................201
11.3.6 IIC Control Register 2 (IICC2) .......................................................................................202
11.4 Functional Description ..................................................................................................................203
11.4.1 IIC Protocol .....................................................................................................................203
MC9S08AC60 Series Data Sheet, Rev. 3
14
Freescale Semiconductor
Section Number
Title
Page
11.4.2 10-bit Address .................................................................................................................206
11.4.3 General Call Address ......................................................................................................207
11.5 Resets ............................................................................................................................................207
11.6 Interrupts .......................................................................................................................................207
11.6.1 Byte Transfer Interrupt ....................................................................................................207
11.6.2 Address Detect Interrupt .................................................................................................208
11.6.3 Arbitration Lost Interrupt ................................................................................................208
11.7 Initialization/Application Information ..........................................................................................209
Chapter 12
Keyboard Interrupt (S08KBIV1)
12.1 Introduction ...................................................................................................................................211
12.1.1 Features ...........................................................................................................................211
12.1.2 KBI Block Diagram ........................................................................................................213
12.2 Register Definition ........................................................................................................................213
12.2.1 KBI Status and Control Register (KBISC) .....................................................................214
12.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................215
12.3 Functional Description ..................................................................................................................215
12.3.1 Pin Enables .....................................................................................................................215
12.3.2 Edge and Level Sensitivity .............................................................................................215
12.3.3 KBI Interrupt Controls ....................................................................................................216
Chapter 13
Serial Communications Interface (S08SCIV4)
13.1 Introduction ...................................................................................................................................217
13.1.1 Features ...........................................................................................................................219
13.1.2 Modes of Operation ........................................................................................................219
13.1.3 Block Diagram ................................................................................................................220
13.2 Register Definition ........................................................................................................................222
13.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................222
13.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................223
13.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................224
13.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................225
13.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................227
13.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................228
13.2.7 SCI Data Register (SCIxD) .............................................................................................229
13.3 Functional Description ..................................................................................................................229
13.3.1 Baud Rate Generation .....................................................................................................229
13.3.2 Transmitter Functional Description ................................................................................230
13.3.3 Receiver Functional Description ....................................................................................231
13.3.4 Interrupts and Status Flags ..............................................................................................233
13.3.5 Additional SCI Functions ...............................................................................................234
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
15
Section Number
Title
Page
Chapter 14
Serial Peripheral Interface (S08SPIV3)
14.1 Introduction ...................................................................................................................................237
14.1.1 Features ...........................................................................................................................239
14.1.2 Block Diagrams ..............................................................................................................239
14.1.3 SPI Baud Rate Generation ..............................................................................................241
14.2 External Signal Description ..........................................................................................................242
14.2.1 SPSCK — SPI Serial Clock ............................................................................................242
14.2.2 MOSI — Master Data Out, Slave Data In ......................................................................242
14.2.3 MISO — Master Data In, Slave Data Out ......................................................................242
14.2.4 SS — Slave Select ..........................................................................................................242
14.3 Modes of Operation .......................................................................................................................243
14.3.1 SPI in Stop Modes ..........................................................................................................243
14.4 Register Definition ........................................................................................................................243
14.4.1 SPI Control Register 1 (SPIC1) ......................................................................................243
14.4.2 SPI Control Register 2 (SPIC2) ......................................................................................244
14.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................245
14.4.4 SPI Status Register (SPIS) ..............................................................................................246
14.4.5 SPI Data Register (SPID) ...............................................................................................247
14.5 Functional Description ..................................................................................................................248
14.5.1 SPI Clock Formats ..........................................................................................................248
14.5.2 SPI Interrupts ..................................................................................................................251
14.5.3 Mode Fault Detection .....................................................................................................251
Chapter 15
Timer/PWM (S08TPMV3)
15.1 Introduction ...................................................................................................................................253
15.2 Features .........................................................................................................................................253
15.3 TPMV3 Differences from Previous Versions ................................................................................255
15.3.1 Migrating from TPMV1 ..................................................................................................257
15.3.2 Features ...........................................................................................................................258
15.3.3 Modes of Operation ........................................................................................................258
15.3.4 Block Diagram ................................................................................................................259
15.4 Signal Description .........................................................................................................................261
15.4.1 Detailed Signal Descriptions ..........................................................................................261
15.5 Register Definition ........................................................................................................................265
15.5.1 TPM Status and Control Register (TPMxSC) ................................................................265
15.5.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................266
15.5.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................267
15.5.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................268
15.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................270
15.6 Functional Description ..................................................................................................................271
MC9S08AC60 Series Data Sheet, Rev. 3
16
Freescale Semiconductor
Section Number
Title
Page
15.6.1 Counter ............................................................................................................................271
15.6.2 Channel Mode Selection .................................................................................................274
15.7 Reset Overview .............................................................................................................................277
15.7.1 General ............................................................................................................................277
15.7.2 Description of Reset Operation .......................................................................................277
15.8 Interrupts .......................................................................................................................................277
15.8.1 General ............................................................................................................................277
15.8.2 Description of Interrupt Operation .................................................................................278
15.9 The Differences from TPM v2 to TPM v3 ....................................................................................279
Chapter 16
Development Support
16.1 Introduction ...................................................................................................................................283
16.1.1 Features ...........................................................................................................................284
16.2 Background Debug Controller (BDC) ..........................................................................................284
16.2.1 BKGD Pin Description ...................................................................................................285
16.2.2 Communication Details ..................................................................................................286
16.2.3 BDC Commands .............................................................................................................290
16.2.4 BDC Hardware Breakpoint .............................................................................................292
16.3 On-Chip Debug System (DBG) ....................................................................................................293
16.3.1 Comparators A and B .....................................................................................................293
16.3.2 Bus Capture Information and FIFO Operation ...............................................................293
16.3.3 Change-of-Flow Information ..........................................................................................294
16.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................294
16.3.5 Trigger Modes .................................................................................................................295
16.3.6 Hardware Breakpoints ....................................................................................................297
16.4 Register Definition ........................................................................................................................297
16.4.1 BDC Registers and Control Bits .....................................................................................297
16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................299
16.4.3 DBG Registers and Control Bits .....................................................................................300
Appendix A
Electrical Characteristics and Timing Specifications
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
Introduction ....................................................................................................................................305
Parameter Classification.................................................................................................................305
Absolute Maximum Ratings...........................................................................................................306
Thermal Characteristics..................................................................................................................307
ESD Protection and Latch-Up Immunity .......................................................................................308
DC Characteristics..........................................................................................................................310
Supply Current Characteristics.......................................................................................................314
ADC Characteristics.......................................................................................................................317
Internal Clock Generation Module Characteristics ........................................................................320
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
17
Section Number
Title
Page
A.9.1 ICG Frequency Specifications .........................................................................................321
A.10 AC Characteristics..........................................................................................................................323
A.10.1 Control Timing ................................................................................................................323
A.10.2 Timer/PWM (TPM) Module Timing ...............................................................................324
A.11 SPI Characteristics .........................................................................................................................326
A.12 FLASH Specifications....................................................................................................................329
A.13 EMC Performance..........................................................................................................................330
A.13.1 Conducted Transient Susceptibility .................................................................................330
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information .....................................................................................................................333
B.2 Orderable Part Numbering System ................................................................................................333
B.3 Mechanical Drawings.....................................................................................................................333
MC9S08AC60 Series Data Sheet, Rev. 3
18
Freescale Semiconductor
Chapter 1
Introduction
1.1
Overview
The MC9S08AC60 Series are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for
memory sizes and package types.
Table 1-1. Devices in the MC9S08AC60 Series
Device
MC9S08AC60
FLASH
RAM
Package
2048
64 QFP
64 LQFP
48 QFN
44 LQFP
32 LQFP
64 QFP
64 LQFP
48 QFN
44 LQFP
32 LQFP
64 QFP
64 LQFP
48 QFN
44 LQFP
32 LQFP
63,280
49,152
MC9S08AC48
32,768
MC9S08AC32
Table 1-2 summarizes the feature set available in the MC9S08AC60 Series of MCUs.
Table 1-2. MC9S08AC60 Series Peripherals Available per Package Type
MC9S08AC60/48/32
Feature
CRC
ADC
IIC
IRQ
KBI1
SCI1
64-pin
48-pin
yes
8-ch
yes
yes
16-ch
8
44-pin
7
32-pin
6-ch
6
4
yes
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
19
Chapter 1 Introduction
Table 1-2. MC9S08AC60 Series Peripherals Available per Package Type
MC9S08AC60/48/32
Feature
64-pin
SCI2
SPI1
TPM1
TPM1CLK1
TPM2
TPM2CLK1
TPM3
TPMCLK 1
I/O pins
1
1.2
48-pin
44-pin
yes
no
yes
4-ch
6-ch
yes
32-pin
2-ch
no
2-ch
yes
no
2-ch
yes
54
38
34
22
TPMCLK, TPM1CLK, and TPM2CLK options are configured via software using the TPMCCFG bit; out of
reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively.
Reference the TPM chapter for a functional description of the TPMxCLK signal.
MCU Block Diagrams
The block diagram shows the structure of the MC9S08AC60 Series MCU.
MC9S08AC60 Series Data Sheet, Rev. 3
20
Freescale Semiconductor
Chapter 1 Introduction
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
IRQ
LVD
IIC MODULE (IIC1)
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC1)
USER FLASH
63,280 BYTES
49,152 BYTES
32,768 BYTES
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
6-CHANNEL TIMER/PWM
MODULE (TPM1)
USER RAM
2048 BYTES
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
INTERNAL CLOCK
GENERATOR (ICG)
LOW-POWER OSCILLATOR
VDD
VSS
VOLTAGE
REGULATOR
TxD2
SDA1
TPMCLK
VDDAD
VSSAD
VREFL
VREFH
2-CHANNEL TIMER/PWM
MODULE (TPM2)
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
PORT B
RxD2
SCL1
PTA[7:0]
6
PTB[7:2]/AD1P[7:2]
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
8 AD1P[7:0]
8 AD1P[15:8]
SPSCK1
MOSI1
MISO1
SS1
TPM1CH1
TPM1CH0
TPM1CLK
TPM1CH[5:2]
RxD1
TxD1
TPM2CH1
TPM2CH0
TPM2CLK
3
KBI1P[7:5]
5
KBI1P[4:0]
EXTAL
XTAL
PTC6
PTC5/RxD2
PTC4
PTC3/TxD2
PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
PORT D
COP
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
TPM3CH1
TPM3CH0
PORT C
2-CHANNEL TIMER/PWM
MODULE (TPM3)
HCS08 SYSTEM CONTROL
RTI
8
CYCLIC REDUNDANCY
CHECK MODULE (CRC)
PORT E
IRQ/TPMCLK
CPU
PTD7/KBI1P7/AD1P15
PTD6/TPM1CLK/AD1P14
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
PTD1/AD1P9
PTD0/AD1P8
PTE7/SPSCK1
PTE6/MOSI1
PTE5/MISO1
PTE4/SS1
PTE3/TPM1CH1
PTE2/TPM1CH0
PTE1/RxD1
PTE0/TxD1
PORT F
RESET
BDC
PORT G
BKGD/MS
PORT A
ICE DEBUG
MODULE (DBG)
HCS08 CORE
PTF[7:6]
PTF5/TPM2CH1
PTF4/TPM2CH0
PTF3/TPM1CH5
PTF2/TPM1CH4
PTF1/TPM1CH3
PTF0/TPM1CH2
PTG6/EXTAL
PTG5/XTAL
PTG4/KBI1P4
PTG3/KBI1P3
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
Notes:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ is enabled
(IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1)
3. Pin contains integrated pullup device.
4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled
(KBIPEn = 1) and rising edge is selected (KBEDGn = 1).
5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and
TPMCLK are available to TPM1, TPM2, and TPM3 respectively.
Figure 1-1. MC9S08AC60 Series Block Diagram
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
21
Chapter 1 Introduction
Table 1 lists the functional versions of the on-chip modules.
Table 1. Versions of On-Chip Modules
Module
Version
Cyclic Redundancy Check Generator
(CRC)
1
Analog-to-Digital Converter
(ADC)
1
(ICG)
4
(IIC)
2
Internal Clock Generator
Inter-Integrated Circuit
Keyboard Interrupt
(KBI)
1
Serial Communications Interface
(SCI)
4
Serial Peripheral Interface
(SPI)
3
(TPM)
3
Timer Pulse-Width Modulator
1.3
Central Processing Unit
(CPU)
2
Debug Module
(DBG)
2
System Clock Distribution
ICGERCLK
SYSTEM
CONTROL
LOGIC
TPM1CLK
TPM2CLK
TPM1
TPM2
IIC1
SCI1
SCI2
SPI1
RTI
FFE
2
ICG
XCLK**
1 kHz
ICGOUT
2
BUSCLK
ICGLCLK*
CPU
COP
BDC
TPM3
ADC1
RAM
TPMCLK
FLASH
CRC
* ICGLCLK is the alternate BDC clock source for the MC9S08AC60 Series.
** Fixed frequency clock.
Figure 1-2. System Clock Distribution Diagram
Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock
connection diagram. The ICG supplies the clock sources:
• ICGOUT is an output of the ICG module. It is one of the following:
— The external crystal oscillator
MC9S08AC60 Series Data Sheet, Rev. 3
22
Freescale Semiconductor
Chapter 1 Introduction
•
•
•
— An external clock source
— The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop
sub-module
— Control bits inside the ICG determine which source is connected.
FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 the frequency
of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2.
Otherwise the fixed-frequency clock will be BUSCLK.
ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed
up BDC communications in systems where the bus clock is slow.
ICGERCLK — External reference clock can be selected as the real-time interrupt clock source.
Can also be used as the ALTCLK input to the ADC module.
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
23
Chapter 1 Introduction
MC9S08AC60 Series Data Sheet, Rev. 3
24
Freescale Semiconductor
Chapter 2
Pins and Connections
2.1
Introduction
This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
2.2
Device Pin Assignment
Figure 2-1. shows the 64-pin package assignments for the MC9S08AC60 Series devices.
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
25
PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
VSS
PTG6/EXTAL
PTG5/XTAL
BKGD/MS
VREFL
VREFH
PTD7/KBI1P7/AD1P15
PTD6/TPM1CLK/AD1P14
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
63
62
61
60
59
58
57
56
55
54
53
52
51
50
64
PTC4 1
PTG4/KBI1P4
PTC3/TxD2
PTC5/RxD2
Chapter 2 Pins and Connections
49
48
PTG3/KBI1P3
IRQ/TPMCLK
2
47
PTD3/KBI1P6/AD1P11
RESET
3
46
PTD2/KBI1P5/AD1P10
PTF0/TPM1CH2
4
45
VSSAD
PTF1/TPM1CH3
5
44
VDDAD
PTF2/TPM1CH4
6
43
PTD1/AD1P9
PTF3/TPM1CH5
7
42
PTD0/AD1P8
PTF4/TPM2CH0
8
41
PTB7/AD1P7
PTC6
9
40
PTB6/AD1P6
PTF7
10
39
PTB5/AD1P5
PTF5/TPM2CH1
11
38
PTB4/AD1P4
PTF6
12
37
PTB3/AD1P3
PTE0/TxD1
13
36
PTB2/AD1P2
PTE1/RxD1
14
35
PTB1/TPM3CH1/AD1P1
PTE2/TPM1CH0
15
34
PTB0/TPM3CH0/AD1P0
64-Pin QFP
64-Pin LQFP
18
19
20
21
22
23
24
25
26
27
28
29
30
32
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/SPSCK1
PTE6/MOSI1
PTE5/MISO1
17
PTE4/SS1
33 PTA7
31
PTA6
PTE3/TPM1CH1 16
Figure 2-1. MC9S08AC60 Series in 64-Pin QFP or LQFP Package
MC9S08AC60 Series Data Sheet, Rev. 3
26
Freescale Semiconductor
Chapter 2 Pins and Connections
37 PTG4/KB1IP4
38 VREFH
39 VREFL
40 BKGD/MS
41 PTG5/XTAL
42 PTG6/EXTAL
43 VSS
44 PTC0/SCL1
45 PTC1/SDA1
46 PTC2/MCLK
PTC4 1
47 PTC3/TxD2
48 PTC5/RxD2
Figure 2-2 shows the 48-pin QFN pin assignments for the MC9S08AC60 Series device.
36 PTG3/KBI1P3
IRQ/TPMCLK 2
35 PTD3/KBI1P6/AD1P11
RESET 3
34 PTD2/KBI1P5/AD1P10
PTF0/TPM1CH2 4
33 VSSAD
PTF1/TPM1CH3 5
32 VDDAD
PTF4/TPM2CH0 6
31 PTD1/AD1P9
48-Pin QFN
PTA2 24
25 PTA7
PTA1 23
PTE3/TPM1CH1 12
PTA0 22
26 PTB0/TPM3CH0/AD1P0
PTG2/KBI1P2 21
PTE2/TPM1CH0 11
PTG1/KBI1P1 20
27 PTB1/TPM3CH1/AD1P1
PTG0/KBI1P0 19
PTE1/RxD1 10
VDD 18
28 PTB2/AD1P2
VSS 17
PTE0/TxD1 9
PTE7/SPSCK1 16
29 PTB3/AD1P3
PTE6/MOSI1 15
PTF6 8
PTE5/MISO1 14
30 PTD0/AD1P8
PTE4/SS1 13
PTF5/TPM2CH1 7
Figure 2-2. MC9S08AC60 Series in 48-Pin QFN Package
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
27
Chapter 2 Pins and Connections
PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
VSS
PTG6/EXTAL
PTG5/XTAL
BKGD/MS
VREFL
43
42
41
40
39
38
37
36
35
34
44
PTC4 1
VREFH
PTC3/TxD2
PTC5/RxD2
Figure 2-3. shows the 44-pin LQFP pin assignments for the MC9S08AC60 Series device.
33 PTG3/KBI1P3
IRQ/TPMCLK
2
32
PTD3/KBI1P6/AD1P11
RESET
3
31
PTD2/KBI1P5/AD1P10
PTF0/TPM1CH2
4
30
VSSAD
PTF1/TPM1CH3
5
29
VDDAD
28
PTD1/AD1P9
44-Pin LQFP
PTF4/TPM2CH0
6
PTF5/TPM2CH1
7
27
PTD0/AD1P8
PTE0/TxD1
8
26
PTB3/AD1P3
PTE1/RxD1
9
25
PTB2/AD1P2
PTE2/TPM1CH0
10
24
PTB1/TPM3CH1/AD1P1
PTE3/TPM1CH1 11
13
14
15
16
17
18
19
20
PTA0
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/SPSCK1
PTE6/MOSI1
PTE5/MISO1
PTA1
22
12
PTE4/SS1
23 PTB0/TPM3CH0/AD1P0
21
Figure 2-3. MC9S08AC60 Series in 44-Pin LQFP Package
MC9S08AC60 Series Data Sheet, Rev. 3
28
Freescale Semiconductor
Chapter 2 Pins and Connections
PTC0/SCL1
VSS
PTG6/EXTAL
PTG5/XTAL
BKGD/MS
VREFL
VREFH
PTC1/SDA1
Figure 2-4. shows the 32-pin LQFP pin assignments for the MC9S08AC60 Series device.
31
30
29
28
27
26
25
32
IRQ/TPMCLK 1
24 PTD3/KBI1P6/AD1P11
RESET
2
23
PTD2/KBI1P5/AD1P10
PTF4/TPM2CH0
3
22
VSSAD
PTF5/TPM2CH1
4
21
VDDAD
PTE0/TxD1
5
20
PTB3/AD1P3
PTE1/RxD1
6
19
PTB2/AD1P2
PTE2/TPM1CH0
7
18
PTB1/TPM3CH1/AD1P1
PTE3/TPM1CH1
8
17
PTB0/TPM3CH0/AD1P0
10
11
12
13
14
15
16
PTE5/MISO1
PTE6/MOSI1
PTE7/SPSCK1
VSS
VDD
PTG0/KBI1P0
PTG1/KBI1P1
32-Pin LQFP
PTE4/SS1
9
Figure 2-4. MC9S08AC60 Series in 32-Pin LQFP Package
2.3
Recommended System Connections
Figure 2-5 shows pin connections that are common to almost all MC9S08AC60 Series application
systems.
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
29
Chapter 2 Pins and Connections
VREFH
CBYAD
0.1 F
PTA0
VSSAD
VREFL
VDD
VDD
SYSTEM
POWER
+
5V
MC9S08AC60
VDDAD
CBLK +
10 F
CBY
0.1 F
PTA1
PTA2
PORT
A
PTA3
PTA4
PTA5
VSS (x2)
PTA6
PTA7
NOTE 1
RF
C1
PTB0/AD1P0
RS
XTAL
NOTE 2
C2
X1
EXTAL
NOTE 2
PTB1/AD1P1
PTB2/AD1P2
PORT
B
1
BKGD/MS
VDD
4.7 k–10 k
4.7 k–
10 k
ASYNCHRONOUS
INTERRUPT
INPUT
0.1F
PTB6/AD1P6
I/O AND
PTB7/AD1P7
PERIPHERAL
PTC0/SCL1
INTERFACE TO
PTC1/SDA1
APPLICATION
PTC2/MCLK
RESET
0.1F VDD
OPTIONAL
MANUAL
RESET
PTB4/AD1P4
PTB5/AD1P5
BACKGROUND HEADER
VDD
PTB3/AD1P3
PORT
C
PTC3/TxD2
SYSTEM
PTC4
PTC5/RxD2
PTC6
IRQ
NOTE 1
PTD0/AD1P8
PTD1/AD1P9
PTG0/KBI1P0
PTD2/KBI1P5/AD1P10
PTG1/KBI1P1
PTG2/KBI1P2
PTG3/KBI1P3
NOTES:
1. Not required if
using the internal
clock option.
2. These are the
same pins as
PTG5 and PTG6
3. RC filters on
RESET and IRQ
are recommended
for EMC-sensitive
applications.
PORT
G
PORT
D
PTD3/KBI1P6/AD1P11
PTD4/TPM2CLK/AD1P12
PTG4/KBI1P4
PTG5/XTAL
PTD5/AD1P13
PTG6/EXTAL
PTD7/KBI1P7/AD1P15
PTD6/TPM1CLK/AD1P14
PTF0/TPM1CH2
PTE0/TxD1
PTF1/TPM1CH3
PTE1/RxD1
PTF2/TPM1CH4
PTE2/TPM1CH0
PTF3/TPM1CH5
PTF4/TPM2CH0
PORT
F
PORT
E
PTF5/TPM2CH1
PTF6
PTF7
PTE3/TPM1CH1
PTE4/SS1
PTE5/MISO1
PTE6/MOSI1
PTE7/SPSCK1
Figure 2-5. Basic System Connections
MC9S08AC60 Series Data Sheet, Rev. 3
30
Freescale Semiconductor
Chapter 2 Pins and Connections
2.3.1
Power (VDD, VSS, VDDAD, VSSAD)
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-F tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-F ceramic bypass capacitor located as near to the paired VDD and VSS
power pins as practical to suppress high-frequency noise. The MC9S08AC60 has a second VSS pin. This
pin should be connected to the system ground plane or to the primary VSS pin through a low-impedance
connection.
VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to
the ADC module. A 0.1-F ceramic bypass capacitor should be located as near to the analog power pins
as practical to suppress high-frequency noise.
2.3.2
Oscillator (XTAL, EXTAL)
Out of reset the MCU uses an internally generated clock (self-clocked mode — fSelf_reset) equivalent to
about 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the
clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains
a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information
on the ICG, see Chapter 10, “Internal Clock Generator (S08ICGV4).”
The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in
either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or
ceramic resonator, an external oscillator can be connected to the EXTAL input pin.
Refer to Figure 2-5 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
value is not generally critical. Typical systems use 1 M to 10 M. Higher values are sensitive to
humidity and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C1 and C2 which are usually the same size. As a first-order approximation,
use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and
XTAL).
2.3.3
RESET Pin
RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
31
Chapter 2 Pins and Connections
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 cycles of fSelf_reset. The reset circuitry decodes the cause of reset and
records it by setting a corresponding bit in the system control reset status register (SRS).
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-5 for
an example.
2.3.4
Background/Mode Select (BKGD/MS)
While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin
functions as the background pin and can be used for background debug communication. While functioning
as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, and no output
slew rate control. When the pin functions as a background pin, it includes a high current output driver.
When the pin functions as a mode select pin it is input only, and therefore does not include a standard
output driver.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5
ADC Reference Pins (VREFH, VREFL)
The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs respectively
for the ADC module.
2.3.6
External Interrupt Pin (IRQ)
The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions.
If the IRQ function is not enabled, this pin can still be configured as the TPMCLK (see the TPM chapter).
In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for
an example.
MC9S08AC60 Series Data Sheet, Rev. 3
32
Freescale Semiconductor
Chapter 2 Pins and Connections
2.3.7
General-Purpose I/O and Peripheral Ports
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers
and serial I/O systems. Immediately after reset, all of these pins are configured as high-impedance
general-purpose inputs with internal pullup devices disabled.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unconnected pins to outputs so the pins
do not float.
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.”
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See the Chapter 6, “Parallel Input/Output” chapter for more details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTD7, PTD3,
PTD2, and PTG4 pins are controlled by the KBI module and are configured for rising-edge/high-level
sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. Similarly,
when IRQ is configured as the IRQ input and is set to detect rising edges, the pullup enable control bit
enables a pulldown device rather than a pullup device.
NOTE
When an alternative function is first enabled it is possible to get a spurious
edge to the module, user software should clear out any associated flags
before interrupts are enabled. Table 2-1 illustrates the priority if multiple
modules are enabled. The highest priority module will have control over the
pin. Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module. It is
recommended that all modules that share a pin be disabled before enabling
another module.
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
33
Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count
Pin Number
Highest
Alt 1
Alt 2
Highest
Alt 1
Alt 2
33 25 — — PTA7
— PTC4
1 IRQ
Pin Number
1
TPMCLK
34 26 23 17 PTB0
TPM3CH0 AD1P0
35 27 24 18 PTB1
TPM3CH1 AD1P1
3
3
3
2 RESET
4
4
4
— PTF0
TPM1CH2
36 28 25 19 PTB2
AD1P2
5
5
5
— PTF1
TPM1CH3
37 29 26 20 PTB3
AD1P3
6
— — — PTF2
TPM1CH4
38 — — — PTB4
AD1P4
AD1P5
7
— — — PTF3
TPM1CH5
39 — — — PTB5
8
6
TPM2CH0
40 — — — PTB6
AD1P6
9
— — — PTC6
41 — — — PTB7
AD1P7
10 — — — PTF7
42 30 27 — PTD0
AD1P8
11
7
7
43 31 28 — PTD1
AD1P9
12
8
— — PTF6
13
9
8
5 PTE0
TxD1
45 33 30 22 VSSAD
14 10
9
6 PTE1
RxD1
46 34 31 23 PTD2
KBI1P5
AD1P10
KBI1P6
AD1P11
6
3 PTF4
4 PTF5
TPM2CH1
44 32 29 21 VDDAD
15 11 10
7 PTE2
TPM1CH0
47 35 32 24 PTD3
16 12 11
8 PTE3
TPM1CH1
48 36 33 — PTG3
KBI1P3
17 13 12
9 PTE4
SS1
49 37 — — PTG4
KBI1P4
MISO1
50 — — — PTD4
TPM2CLK AD1P12
19 15 14 11 PTE6
MOSI1
51 — — — PTD5
AD1P13
20 16 15 12 PTE7
SPSCK1
52 — — — PTD6
TPM1CLK AD1P14
21 17 16 13 VSS
53 — — — PTD7
KBI1P7
22 18 17 14 VDD
54 38 34 25 VREFH
18 14 13 10 PTE5
23 19 18 15 PTG0
KBI1P0
55 39 35 26 VREFL
24 20 19 16 PTG1
KBI1P1
56 40 36 27 BKGD
MS
25 21 20 — PTG2
KBI1P2
57 41 37 28 PTG5
XTAL
26 22 21 — PTA0
58 42 38 29 PTG6
EXTAL
27 23 22 — PTA1
59 43 39 30 VSS
28 24 — — PTA2
60 44 40 31 PTC0
SCL1
29 — — — PTA3
61 45 41 32 PTC1
SDA1
30 — — — PTA4
62 46 42 — PTC2
MCLK
31 — — — PTA5
63 47 43 — PTC3
TxD2
32 — — — PTA6
64 48 44 — PTC5
RxD2
AD1P15
1. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK
are available to TPM1, TPM2, and TPM3 respectively.
MC9S08AC60 Series Data Sheet, Rev. 3
34
Freescale Semiconductor
Chapter 3
Modes of Operation
3.1
Introduction
The operating modes of the MC9S08AC60 Series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2
•
•
•
3.3
Features
Active background mode for code development
Wait mode:
— CPU shuts down to conserve power
— System clocks running
— Full voltage regulation maintained
Stop modes:
— System clocks stopped; voltage regulator in standby
— Stop2 — Partial power down of internal circuits, RAM contents retained
— Stop3 — All internal circuits powered for fast recovery
Run Mode
This is the normal operating mode for the MC9S08AC60 Series. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.4
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip ICE debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low at the rising edge of reset
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
35
Chapter 3 Modes of Operation
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user’s application program.
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user’s application program (GO)
3.5
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.6
Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system
option register is set. In both stop modes, all internal clocks are halted. If the STOPE bit is not set when
the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Some HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode.
The MC9S08AC60 Series of devices operates at 2.7 V to 5.5 V and does not include stop1 mode.
MC9S08AC60 Series Data Sheet, Rev. 3
36
Freescale Semiconductor
Chapter 3 Modes of Operation
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
Table 3-1. Stop Mode Behavior
1
Mode
PPDC
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ADC
Regulator
I/O Pins
RTI
Stop2
1
Off
Standby
Off
Disabled
Standby
States held
Optionally on
Stop3
0
Standby
Standby
Off1
Optionally on
Standby
States held
Optionally on
Crystal oscillator can be configured to run in stop3. Please see the ICG registers.
3.6.1
Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and
the current state of all of the I/O pins. To enter stop2, the user must execute a STOP instruction with stop2
selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to
operate in stop (LVDSE = LVDE = 1). If the LVD is enabled in stop, then the MCU enters stop3 upon the
execution of the STOP instruction regardless of the state of PPDC.
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit
of stop2, these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ADC. Upon entry
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a logic 1 is written to PPDACK in SPMSC2.
Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt.
IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before
entering stop2.
Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is
written to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
37
Chapter 3 Modes of Operation
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
A separate self-clocked source (1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
3.6.2
Stop3 Mode
To enter stop3, the user must execute a STOP instruction with stop3 selected (PPDC = 0) and stop mode
enabled (STOPE = 1). Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator
itself, are halted. The ICG enters its standby state, as does the voltage regulator and the ADC. The states
of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are
not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic
driving the pins being maintained.
Exit from stop3 is done by asserting RESET, an asynchronous interrupt pin, or through the real-time
interrupt (RTI). The asynchronous interrupt pins are the IRQ or KBI pins. Exit from stop3 can also
facilitated by the SCI reciever interrupt, the ADC, and LVI.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
3.6.3
Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in Chapter 16, “Development Support” of this data sheet. If ENBDM is set when
the CPU executes a STOP instruction, the system clocks to the background debug logic remain active
when the MCU enters stop mode so background debug communication is still possible. In addition, the
voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the
user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the
background debug mode is enabled.
MC9S08AC60 Series Data Sheet, Rev. 3
38
Freescale Semiconductor
Chapter 3 Modes of Operation
Table 3-2. BDM Enabled Stop Mode Behavior
Mode
PPDC
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ADC
Regulator
I/O Pins
RTI
Stop3
x
Standby
Standby
Active
Optionally on
Active
States held
Optionally on
3.6.4
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the
LVD is enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
Mode
PPDC
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ADC
Regulator
I/O Pins
RTI
Stop3
x
Standby
Standby
Off
Optionally on
Active
States held
Optionally on
3.6.5
On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2
Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes.
Table 3-4. Stop Mode Behavior
Mode
Peripheral
Stop2
Stop3
CPU
Off
Standby
RAM
Standby
Standby
FLASH
Off
Standby
Parallel Port Registers
Off
Standby
ADC
Off
Optionally On1
ICG
Off
Optionally On2
IIC
Off
RTI
Optionally
Standby
on3
Optionally on3
SCI
Off
Standby
SPI
Off
Standby
TPM
Off
Standby
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
39
Chapter 3 Modes of Operation
Table 3-4. Stop Mode Behavior (continued)
Mode
Peripheral
System Voltage Regulator
I/O Pins
Stop2
Stop3
Standby
Standby
States Held
States Held
1
Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
OSCSTEN set in ICGC1, else in standby.
3
RTIS[2:0] in SRTISC does not equal 0 before entering stop, else off.
2
MC9S08AC60 Series Data Sheet, Rev. 3
40
Freescale Semiconductor
Chapter 4
Memory
4.1
MC9S08AC60 Series Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08AC60 Series series of MCUs consists of RAM,
FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers
are divided into three groups:
• Direct-page registers ($0000 through $006F)
• High-page registers ($1800 through $185F)
• Nonvolatile registers ($FFB0 through $FFBF)
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
41
Chapter 4 Memory
$0000
$006F
$0070
DIRECT PAGE REGISTERS
RAM
$0000
$006F
$0070
$17FF
$1800
FLASH
3984 BYTES
$086F
$0870
$17FF
$1800
$006F
$0070
RESERVED
3984 BYTES
DIRECT PAGE REGISTERS
RAM
2048 BYTES
$086F
$0870
$17FF
$1800
RESERVED
3984 BYTES
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
$185F
$1860
RAM
$0000
2048 BYTES
2048 BYTES
$086F
$0870
DIRECT PAGE REGISTERS
$185F
$1860
$185F
$1860
RESERVED
RESERVED
10,144 BYTES
26,528 BYTES
$3FFF
$4000
$7FFF
$8000
FLASH
59,296 BYTES
FLASH
FLASH
49,152 BYTES
32,768 BYTES
$FFFF
$FFFF
$FFFF
MC9S08AC60
MC9S08AC48
Figure 4-1. MC9S08AC60
MC9S08AC32
Series Memory Map
MC9S08AC60 Series Data Sheet, Rev. 3
42
Freescale Semiconductor
Chapter 4 Memory
4.1.1
Reset and Interrupt Vector Assignments
Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale-provided equate file for the MC9S08AC60 Series. For more details
about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets,
Interrupts, and System Configuration.”
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low)
Vector
Vector Name
0xFFC0:FFC1
through
0xFFC4:FFC5
Unused Vector Space
(available for user program)
—
0xFFC6:FFC7
TPM3 overflow
Vtpm3ovf
0xFFC8:FFC9
TPM3 channel 1
Vtpm3ch1
0xFFCA:FFCB
TPM3 channel 0
Vtpm3ch0
0xFFCC:FFCD
RTI
Vrti
0xFFCE:FFCF
IIC1
Viic1
0xFFD0:FFD1
ADC1 conversion
Vadc1
0xFFD2:FFD3
KBI1
Vkeyboard1
0xFFD4:FFD5
SCI2 transmit
Vsci2tx
0xFFD6:FFD7
SCI2 receive
Vsci2rx
0xFFD8:FFD9
SCI2 error
Vsci2err
0xFFDA:FFDB
SCI1 transmit
Vsci1tx
0xFFDC:FFDD
SCI1 receive
Vsci1rx
0xFFDE:FFDF
SCI1 error
Vsci1err
0xFFE0:FFE1
SPI1
Vspi1
0xFFE2:FFE3
TPM2 overflow
Vtpm2ovf
0xFFE4:FFE5
TPM2 channel 1
Vtpm2ch1
0xFFE6:FFE7
TPM2 channel 0
Vtpm2ch0
0xFFE8:FFE9
TPM1 overflow
Vtpm1ovf
0xFFEA:FFEB
TPM1 channel 5
Vtpm1ch5
0xFFEC:FFED
TPM1 channel 4
Vtpm1ch4
0xFFEE:FFEF
TPM1 channel 3
Vtpm1ch3
0xFFF0:FFF1
TPM1 channel 2
Vtpm1ch2
0xFFF2:FFF3
TPM1 channel 1
Vtpm1ch1
0xFFF4:FFF5
TPM1 channel 0
Vtpm1ch0
0xFFF6:FFF7
ICG
Vicg
0xFFF8:FFF9
Low voltage detect
Vlvd
0xFFFA:FFFB
IRQ
Virq
0xFFFC:FFFD
SWI
Vswi
0xFFFE:FFFF
Reset
Vreset
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
43
Chapter 4 Memory
4.2
Register Addresses and Bit Assignments
The registers in the MC9S08AC60 Series are divided into these three groups:
• Direct-page registers are located in the first 112 locations in the memory map, so they are
accessible with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at
$FFB0–$FFBF.
Nonvolatile register locations include:
— Three values which are loaded into working registers at reset
— An 8-byte backdoor comparison key which optionally allows a user to gain controlled access
to secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only
requires the lower byte of the address. Because of this, the lower byte of the address in column one is
shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In
Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart
from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with
a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
MC9S08AC60 Series Data Sheet, Rev. 3
44
Freescale Semiconductor
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address
Register Name
0x0000
PTAD
0x0001
PTADD
0x0002
PTBD
0x0003
PTBDD
0x0004
Bit 7
6
5
4
3
2
1
Bit 0
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
PTADD7
PTADD6
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
PTADD0
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
PTCD
0
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
PTCD0
0x0005
PTCDD
0
PTCDD6
PTCDD5
PTCDD4
PTCDD3
PTCDD2
PTCDD1
PTCDD0
0x0006
PTDD
0x0007
PTDDD
0x0008
PTED
0x0009
PTEDD
0x000A
PTFD
PTFD7
PTFD6
PTFD5
PTFD4
PTFD3
PTFD2
PTFD1
PTFD0
0x000B
PTFDD
PTFDD7
PTFDD6
PTFDD5
PTFDD4
PTFDD3
PTFDD2
PTFDD1
PTFDD0
0x000C
PTGD
0
PTGD6
PTGD5
PTGD4
PTGD3
PTGD2
PTGD1
PTGD0
0x000D
PTGDD
0
PTGDD6
PTGDD5
PTGDD4
PTGDD3
PTGDD2
PTGDD1
PTGDD0
0x000E–
0x000F
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0010
ADC1SC1
COCO
AIEN
ADCO
0x0011
ADC1SC2
ADACT
ADTRG
ACFE
ACFGT
0
0
R
R
0x0012
ADC1RH
0
0
0
0
0
0
ADR9
ADR8
0x0013
ADC1RL
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
0x0014
ADC1CVH
0
0
0
0
0
0
ADCV9
ADCV8
0x0015
ADC1CVL
ADCV7
ADCV6
ADCV5
ADCV4
ADCV3
ADCV2
ADCV1
ADCV0
0x0016
ADC1CFG
ADLPC
0x0017
APCTL1
ADPC7
ADPC6
ADPC5
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
0x0018
APCTL2
ADPC15
ADPC14
ADPC13
ADPC12
ADPC11
ADPC10
ADPC9
ADPC8
0x0019–
0x001B
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x001C
IRQSC
0
IRQPDD
IRQEDG
IRQPE
IRQF
IRQACK
IRQIE
IRQMOD
PTDD7
PTDD6
PTDD5
PTDD4
PTDD3
PTDD2
PTDD1
PTDD0
PTDDD7
PTDDD6
PTDDD5
PTDDD4
PTDDD3
PTDDD2
PTDDD1
PTDDD0
PTED7
PTED6
PTED5
PTED4
PTED3
PTED2
PTED1
PTED0
PTEDD7
PTEDD6
PTEDD5
PTEDD4
PTEDD3
PTEDD2
PTEDD1
PTEDD0
ADIV
ADCH
ADLSMP
MODE
ADICLK
0x001D
Reserved
—
—
—
—
—
—
—
—
0x001E
KBISC
KBEDG7
KBEDG6
KBEDG5
KBEDG4
KBF
KBACK
KBIE
KBIMOD
0x001F
KBIPE
KBIPE7
KBIPE6
KBIPE5
KBIPE4
KBIPE3
KBIPE2
KBIPE1
KBIPE0
0x0020
TPM1SC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0x0021
TPM1CNTH
Bit 15
14
13
12
11
10
9
Bit 8
0x0022
TPM1CNTL
Bit 7
6
5
4
3
2
1
Bit 0
0x0023
TPM1MODH
Bit 15
14
13
12
11
10
9
Bit 8
0x0024
TPM1MODL
Bit 7
6
5
4
3
2
1
Bit 0
0x0025
TPM1C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x0026
TPM1C0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0027
TPM1C0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0028
TPM1C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
45
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0029
TPM1C1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x002A
TPM1C1VL
Bit 7
6
5
4
3
2
1
Bit 0
0x002B
TPM1C2SC
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
0
0
0x002C
TPM1C2VH
Bit 15
14
13
12
11
10
9
Bit 8
0x002D
TPM1C2VL
Bit 7
6
5
4
3
2
1
Bit 0
0x002E
TPM1C3SC
CH3F
CH3IE
MS3B
MS3A
ELS3B
ELS3A
0
0
0x002F
TPM1C3VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0030
TPM1C3VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0031
TPM1C4SC
CH4F
CH4IE
MS4B
MS4A
ELS4B
ELS4A
0
0
0x0032
TPM1C4VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0033
TPM1C4VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0034
TPM1C5SC
CH3F
CH5IE
MS5B
MS5A
ELS5B
ELS5A
0
0
0x0035
TPM1C5VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0036
TPM1C5VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0037
Reserved
—
—
—
—
—
—
—
—
0x0038
SCI1BDH
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
0x0039
SCI1BDL
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0x003A
SCI1C1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0x003B
SCI1C2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0x003C
SCI1S1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0x003D
SCI1S2
LBKDIF
RXEDGIF
0
RXINV
RWUID
BRK13
LBKDE
RAF
0x003E
SCI1C3
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
0x003F
SCI1D
Bit 7
6
5
4
3
2
1
Bit 0
0x0040
SCI2BDH
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
0x0041
SCI2BDL
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0x0042
SCI2C1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0x0043
SCI2C2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0x0044
SCI2S1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0x0045
SCI2S2
LBKDIF
RXEDGIF
0
RXINV
RWUID
BRK13
LBKDE
RAF
0x0046
SCI2C3
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
4
3
2
1
Bit 0
OSCSTEN
LOCD
0
0x0047
SCI2D
Bit 7
6
5
0x0048
ICGC1
HGO
RANGE
REFS
0x0049
ICGC2
LOLRE
0x004A
ICGS1
CLKS
MFD
CLKST
LOCRE
RFD
REFST
LOLS
LOCK
LOCS
0
0
0x004B
ICGS2
0
0
0
0
0x004C
ICGFLTU
0
0
0
0
0x004D
ICGFLTL
FLT
0x004E
ICGTRM
TRIM
0x004F
Reserved
0x0050
SPI1C1
ERCS
ICGIF
0
DCOS
FLT
—
—
—
—
—
—
—
—
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
MC9S08AC60 Series Data Sheet, Rev. 3
46
Freescale Semiconductor
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0051
SPI1C2
0
0
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
0x0052
SPI1BR
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
0x0053
SPI1S
SPRF
0
SPTEF
MODF
0
0
0
0
0x0054
Reserved
0
0
0
0
0
0
0
0
0x0055
SPI1D
Bit 7
6
5
4
3
2
1
Bit 0
0x0056
CRCH
Bit 15
14
13
12
11
10
9
Bit 8
0x0057
CRCL
Bit 7
6
5
4
3
2
1
Bit 0
0x0058
IIC1A
0x0059
IIC1F
0x005A
IIC1C1
IICEN
IICIE
MST
TX
0x005B
IIC1S
TCF
IAAS
BUSY
ARBL
0x005C
IIC1D
0x005D
IIC1C2
0x005E–
0x005F
Reserved
0x0060
TPM2SC
0x0061
TPM2CNTH
0x0062
TPM2CNTL
0x0063
TPM2MODH
ADDR
0
MULT
ICR
TXAK
RSTA
0
0
0
SRW
IICIF
RXAK
DATA
GCAEN
ADEXT
0
0
0
AD10
AD9
AD8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0x0064
TPM2MODL
Bit 7
6
5
4
3
2
1
Bit 0
0x0065
TPM2C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x0066
TPM2C0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0067
TPM2C0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0068
TPM2C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
0x0069
TPM2C1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x006A
TPM2C1VL
Bit 7
6
5
4
3
2
1
Bit 0
0x006B–
0x006F
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Table 4-3. High-Page Register Summary (Sheet 1 of 3)
Address
Register Name
0x1800
SRS
0x1801
SBDFR
0x1802
SOPT
0x1803
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
0
ICG
LVD
0
0
0
0
0
0
0
0
BDFR
COPE
COPT
STOPE
—
0
0
—
—
SMCLK
0
0
0
MPE
0
0x1804 –
0x1805
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1806
SDIDH
REV3
REV2
REV1
REV0
ID11
ID10
ID9
ID8
MCSEL
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
47
Chapter 4 Memory
Table 4-3. High-Page Register Summary (Sheet 2 of 3)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTIF
RTIACK
RTICLKS
RTIE
0
RTIS2
RTIS1
RTIS0
0x1807
SDIDL
0x1808
SRTISC
0x1809
SPMSC1
LVDF
LVDACK
LVDIE
LVDRE
LVDSE
0x180A
SPMSC2
LVWF
LVWACK
LVDV
LVWV
PPDF
0x180B
Reserved
—
—
—
—
0x180C
SOPT2
COPCLKS
—
—
0x180D–
0x180F
Reserved
—
—
—
—
0x1810
DBGCAH
Bit 15
0x1811
DBGCAL
0x1812
DBGCBH
LVDE
1
0
BGBE
PPDACK
—
PPDC
—
—
—
—
—
TPMCCFG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0x1813
DBGCBL
Bit 7
6
5
4
3
2
1
Bit 0
0x1814
DBGFH
Bit 15
14
13
12
11
10
9
Bit 8
0x1815
DBGFL
Bit 7
6
5
4
3
2
1
Bit 0
0x1816
DBGC
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
0x1817
DBGT
TRGSEL
BEGIN
0
0
TRG3
TRG2
TRG1
TRG0
0x1818
DBGS
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
0x1819–
0x181F
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1820
FCDIV
DIVLD
PRDIV8
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
0x1821
FOPT
KEYEN
FNORED
0
0
0
0
SEC01
SEC00
0x1822
Reserved
—
—
—
—
—
—
—
—
0x1823
FCNFG
0
0
KEYACC
0
0
0
0
0
0x1824
FPROT
FPS7
FPS6
FPS5
FPS4
FPS3
FPS2
FPS1
FPDIS
0x1825
FSTAT
FCBEF
FCCF
FPVIOL
FACCERR
0
FBLANK
0
0
0x1826
FCMD
FCMD7
FCMD6
FCMD5
FCMD4
FCMD3
FCMD2
FCMD1
FCMD0
0x1827–
0x182F
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1830
TPM3SC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0x1831
TPM3CNTH
Bit 15
14
13
12
11
10
9
Bit 8
0x1832
TPM3CNTL
Bit 7
6
5
4
3
2
1
Bit 0
0x1833
TPM3MODH
Bit 15
14
13
12
11
10
9
Bit 8
0x1834
TPM3MODL
Bit 7
6
5
4
3
2
1
Bit 0
0x1835
TPM3C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x1836
TPM3C0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x1837
TPM3C0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x1838
TPM3C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
0x1839
TPM3C1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x183A
TPM3C1VL
Bit 7
6
5
4
3
2
1
Bit 0
MC9S08AC60 Series Data Sheet, Rev. 3
48
Freescale Semiconductor
Chapter 4 Memory
Table 4-3. High-Page Register Summary (Sheet 3 of 3)
Address
Register Name
0x183B
0x183F
Reserved
0x1840
PTAPE
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTAPE7
PTAPE6
PTAPE5
PTAPE4
PTAPE3
PTAPE2
PTAPE1
PTAPE0
0x1841
PTASE
PTASE7
PTASE6
PTASE5
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
0x1842
PTADS
PTADS7
PTADS6
PTADS5
PTADS4
PTADS3
PTADS2
PTADS1
PTADS0
0x1843
Reserved
—
—
—
—
—
—
—
—
0x1844
PTBPE
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
0x1845
PTBSE
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
0x1846
PTBDS
PTBDS7
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
0x1847
Reserved
—
—
—
—
—
—
—
—
0x1848
PTCPE
0
PTCPE6
PTCPE5
PTCPE4
PTCPE3
PTCPE2
PTCPE1
PTCPE0
0x1849
PTCSE
0
PTCSE6
PTCSE5
PTCSE4
PTCSE3
PTCSE2
PTCSE1
PTCSE0
0x184A
PTCDS
0
PTCDS6
PTCDS5
PTCDS4
PTCDS3
PTCDS2
PTCDS1
PTCDS0
0x184B
Reserved
—
—
—
—
—
—
—
—
0x184C
PTDPE
PTDPE7
PTDPE6
PTDPE5
PTDPE4
PTDPE3
PTDPE2
PTDPE1
PTDPE0
0x184D
PTDSE
PTDSE7
PTDSE6
PTDSE5
PTDSE4
PTDSE3
PTDSE2
PTDSE1
PTDSE0
0x184E
PTDDS
PTDDS7
PTDDS6
PTDDS5
PTDDS4
PTDDS3
PTDDS2
PTDDS1
PTDDS0
0x184F
Reserved
—
—
—
—
—
—
—
—
0x1850
PTEPE
PTEPE7
PTEPE6
PTEPE5
PTEPE4
PTEPE3
PTEPE2
PTEPE1
PTEPE0
0x1851
PTESE
PTESE7
PTESE6
PTESE5
PTESE4
PTESE3
PTESE2
PTESE1
PTESE0
0x1852
PTEDS
PTEDS7
PTEDS6
PTEDS5
PTEDS4
PTEDS3
PTEDS2
PTEDS1
PTEDS0
0x1853
Reserved
—
—
—
—
—
—
—
—
0x1854
PTFPE
PTFPE7
PTFPE6
PTFPE5
PTFPE4
PTFPE3
PTFPE2
PTFPE1
PTFPE0
0x1855
PTFSE
PTFSE7
PTFSE6
PTFSE5
PTFSE4
PTFSE3
PTFSE2
PTFSE1
PTFSE0
0x1856
PTFDS
PTFDS7
PTFDS6
PTFDS5
PTFDS4
PTFDS3
PTFDS2
PTFDS1
PTFDS0
0x1857
Reserved
—
—
—
—
—
—
—
—
0x1858
PTGPE
0
PTGPE6
PTGPE5
PTGPE4
PTGPE3
PTGPE2
PTGPE1
PTGPE0
0x1859
PTGSE
0
PTGSE6
PTGSE5
PTGSE4
PTGSE3
PTGSE2
PTGSE1
PTGSE0
0x185A
PTGDS
0
PTGDS6
PTGDS5
PTGDS4
PTGDS3
PTGDS2
PTGDS1
PTGDS0
0x185B–
0x185F
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
This reserved bit must always be written to 0.
Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers
include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
49
Chapter 4 Memory
Table 4-4. Nonvolatile Register Summary
Address
Register Name
$FFB0 –
$FFB7
NVBACKKEY
$FFB8 –
$FFBB
Reserved
$FFBC
Reserved for storage of 250 kHz
ICGTRM value
$FFBD
NVPROT
$FFBE
Reserved for storage of 243 kHz
ICGTRM value
$FFBF
NVOPT
Bit 7
6
5
4
3
2
1
Bit 0
8-Byte Comparison Key
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FPS7
FPS6
FPS5
FPS4
FPS3
FPS2
FPS1
FPDIS
—
—
—
—
—
—
—
—
KEYEN
FNORED
0
0
0
0
SEC01
SEC00
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.3
RAM
The MC9S08AC60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on, the
contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage
does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08AC60 Series, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale-provided equate file).
LDHX
TXS
#RamLast+1
;point one past RAM
;SP
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