Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806: Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
Package Description
Original (gold wire)
Current (copper wire)
package document number package document number
48 QFN
98ARH99048A
98ASA00466D
MC9RS08LA8
48 QFN
98ARL10606D
98ASA00466D
MC9S08GT16A
32 QFN
98ARH99035A
98ASA00473D
MC9S908QE32
32 QFN
98ARE10566D
98ASA00473D
MC9S908QE8
32 QFN
98ASA00071D
98ASA00736D
MC9S08JS16
24 QFN
98ARL10608D
98ASA00734D
MC9S08QG8
24 QFN
98ARL10605D
98ASA00474D
MC9S08SH8
24 QFN
98ARE10714D
98ASA00474D
MC9RS08KB12
24 QFN
98ASA00087D
98ASA00602D
MC9S08QG8
16 QFN
98ARE10614D
98ASA00671D
MC9RS08KB12
8 DFN
98ARL10557D
98ASA00672D
6 DFN
98ARL10602D
98ASA00735D
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9S08QB8
MC9S08QG8
MC9RS08KA2
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08QE32
Rev. 7, 9/2011
An Energy Efficient Solution by Freescale
MC9S08QE32 Series
Covers: MC9S08QE32 and
MC9S08QE16
Features
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 50.33 MHz HCS08 CPU at 3.6 V to 2.4 V, 40 MHz CPU at 2.4
V to 2.1 V and 20 MHz CPU at 2.1 V to 1.8 V across temperature
range of –40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Flash read/program/erase over full operating voltage and
temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and flash
contents
• Power-Saving Modes
– Two very low power stop modes
– Reduced power wait mode
– Peripheral clock enable register can disable clocks to unused
modules, thereby reducing currents; allows clocks to remain enabled
to specific peripherals in stop3 mode.
– Very low power external oscillator that can be used in run, wait, and
stop modes to provide accurate clock source to real time counter.
– 6 s typical wakeup time from stop3 mode
• Clock Source Options
– Oscillator (XOSCVLP) — Loop-control Pierce oscillator; crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16
MHz
– Internal clock source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference; precision trimming of internal reference allows
0.2% resolution and 2% deviation over temperature and voltage;
supports CPU frequencies from
4 kHz to 50.33 MHz.
• System Protection
– Watchdog computer operating properly (COP) reset with option to
run from dedicated 1 kHz internal clock source or bus clock.
– Low-voltage warning with interrupt.
– Low-voltage detection with reset or interrupt
– Selectable trip points.
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus three breakpoints in on-chip debug
module)
MC9S08QE32
48-QFN
Case 1314
7 mm 7 mm
44-LQFP
Case 824D
10 mm 10 mm
32-LQFP
Case 873A
7 mm 7 mm
28-SOIC
Case 751F
32-QFN
Case 1582
5 mm 5 mm
– On-chip in-circuit emulator (ICE) debug module containing three
comparators and nine trigger modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data. Debug module
supports both tag and force breakpoints
• Peripherals
– ADC — 10-channel, 12-bit resolution; 2.5s conversion time;
automatic compare function; 1.7 mV/C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V
– ACMPx — Two analog comparators with selectable interrupt on
rising, falling, or either edge of comparator output; compare option
to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
– SCIx — Two serial communications interface modules with
optional 13-bit break. Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave extended break
detection; wake on active edge.
– SPI— One serial peripheral interface; full-duplex or single-wire
bidirectional; double-buffered transmit and receive; master or
slave mode; MSB-first or LSB-first shifting
– IIC — One IIC; up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address; interrupt
driven byte-by-byte data transfer; supports broadcast mode and
10-bit addressing
– TPMx — One 6-channel (TPM3) and two 3-channel (TPM1 and
TPM2); selectable input capture, output compare, or buffered
edge- or center-aligned PWM on each channel;
– RTC — (Real-time counter) 8-bit modulus counter with binary or
decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
• Input/Output
– 40 GPIOs, including 1 output-only pin and 1 input-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull up device on all input pins;
Configurable slew rate and drive strength on all output pins.
• Package Options
– 48-pin QFN, 44-pin LQFP, 32-pin LQFP/QFN, 28-pin SOIC
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2011. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 10
3.5 ESD Protection and Latch-Up Immunity . . . . . . 12
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Supply Current Characteristics . . . . . . . . . . . . . 16
3.8 External Oscillator (XOSCVLP) Characteristics 18
4
5
3.9 Internal Clock Source (ICS) Characteristics . . .
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . .
3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . .
3.10.2TPM Module Timing . . . . . . . . . . . . . . . .
3.10.3SPI Timing. . . . . . . . . . . . . . . . . . . . . . . .
3.11 Analog Comparator (ACMP) Electricals . . . . . .
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .
3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . .
19
20
20
21
22
26
26
29
30
30
30
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Date
Description of Changes
1
7/2/2008
Initial public released.
2
10/7/2008
Updated the Stop2 and Stop3 mode supply current, and RIDD in FEI mode with all modules
on at 25.165 MHz in the Table 8 Supply Current Characteristics.
Replaced the stop mode adders section from Table 8 with an individual Table 9 Stop Mode
Adders with new specifications.
3
11/4/2008
Updated operating voltage in Table 7.
4
5/4/2009
Added 1010 mm information to 44 LQFP in the front page.
In Table 7, added |IOZTOT|.
In Table 11, updated typicals and Max. for tIRST.
In Table 16, removed the Rev. Voltage High item.
Updated Table 17.
5
8/27/2009
Updated fint_t and fint_ut in the Table 11.
6
10/13/2009
Corrected the package size descriptions on the cover
7
9/16/2011
Added new package of 32-pin QFN.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08QE32RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9S08QE32 MCU.
PORT A
VSS
VOLTAGE REGULATOR
VREFL
VREFH
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI1)
RxD1
TxD1
3-CHANNEL TIMER/PWM
MODULE (TPM1)
(MC9S08QE16 = 1024 BYTES)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSCVLP)
SDA
SERIAL PERIPHERAL
INTERFACE MODULE(SPI)
USER RAM
(MC9S08QE32 = 2048 BYTES)
50.33 MHz INTERNAL CLOCK
SOURCE (ICS)
IIC MODULE (IIC)
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI2)
(MC9S08QE16 = 16384 BYTES)
VSSAD/VREFL
VDDAD/VREFH
PORT B
LVD
USER FLASH
(MC9S08QE32 = 32768 BYTES)
VDD
PORT C
IRQ
PTC7/TxD2/ACMP2–
PTC6/RxD2/ACMP2+
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4
PTC3/TPM3CH3
PTC2/TPM3CH2
PTC1/TPM3CH1
PTC0/TPM3CH0
PTD7/KBI2P7
PTD6/KBI2P6
PTD5/KBI2P5
PTD4/KBI2P4
PTD3/KBI2P3
PTD2/KBI2P2
PTD1/KBI2P1
PTD0/KBI2P0
PTE7/TPM3CLK
PTE6
PTE5
PTE4
PTE3/SS
PTE2/MISO
PTE1/MOSI
PTE0/TPM2CLK/SPSCK
SCL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
PORT D
REAL-TIME COUNTER
(RTC)
HCS08 SYSTEM CONTROL
IRQ
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/KBI1P7/MOSI/ADP7
PTB2/KBI1P6/SPSCK/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
DEBUG MODULE (DBG)
BDC
CPU
PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA3/KBI1P3/SCL/ADP3
PTA2/KBI1P2/SDA/ADP2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1–
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PORT E
BKGD/MS
HCS08 CORE
3-CHANNEL TIMER/PWM
MODULE (TPM2)
EXTAL
6-CHANNEL TIMER/PWM
MODULE (TPM3)
XTAL
RxD2
TxD2
SS
MISO
MOSI
SPSCK
TPM1CLK
TPM1CH2–TPM1CH0
TPM2CLK
TPM2CH2–TPM2CH0
TPM3CLK
TPM3CH5–TPM3CH0
VSSAD
VDDAD
ANALOG COMPARATOR
(ACMP1)
ACMP1O
ACMP1–
ACMP1+
VSSAD
VDDAD
ANALOG COMPARATOR
(ACMP2)
ACMP2O
ACMP2–
ACMP2+
10-CHANNEL, 12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC12)
ADP9–ADP0
KEYBOARD INTERRUPT
MODULE (KBI1)
KBI1P7–KBI1P0
KEYBOARD INTERRUPT
MODULE (KBI2)
KBI2P7–KBI2P0
pins not available on 28-pin packages
pins not available on 28-pin or 32-pin packages
pins not available on 28-pin, 32-pin, or 44-pin packages
Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.
When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 28-pin packages, VSSAD/VREFL and VDDAD/VREFH are double bonded to VSS and VDD respectively.
The 48-pin package is the only package with the option of having the SPI pins (SS, MISO, MOSI, and SPSCK) available on PTE3-0 pins.
Figure 1. MC9S08QE32 Series Block Diagram
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
3
Pin Assignments
2
Pin Assignments
PTA1/KBI1P1/TPM2CH0/AD
37 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1–
38 PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
39 PTC7/TxD2/ACMP2–
40 PTC6/RxD2/ACMP2+
41 PTE3/SS
42 PTE2/MISO
43 PTE1/MOSI
44 PTE0/TPM2CLK/SPSCK
45 PTC5/TPM3CH5/ACMP2O
46 PTC4/TPM3CH4
47 PTA5/IRQ/TPM1CLK/RESET
48 PTA4/ACMP1O/BKGD/MS
This section shows the pin assignments for the MC9S08QE32 series devices.
PTD1/KBI2P1 1
36 PTA2/KBI1P2/SDA/ADP2
PTD0/KBI2P0 2
35 PTA3/KBI1P3/SCL/ADP3
PTE7/TPM3CLK 3
34 PTD2/KBI2P2
VDD 4
33 PTD3/KBI2P3
VDDAD 5
32 PTD4/KBI2P4
VREFH 6
31 VSS
VREFL 7
30 VDD
VSSAD 8
29 PTE4
VSS 9
28 PTA6/TPM1CH2/ADP8
PTB7/SCL/EXTAL 10
27 PTA7/TPM2CH2/ADP9
PTB2/KBI1P6/SPSCK/ADP6 24
PTB3/KBI1P7/MOSI/ADP7 23
PTC0/TPM3CH0 22
PTC1/TPM3CH1 21
PTD5/KBI2P5 20
PTD6/KBI2P6 19
PTD7/KBI2P7 18
PTC2/TPM3CH2 17
PTC3/TPM3CH3 16
25 PTB1/KBI1P5/TxD1/ADP5
PTB4/TPM2CH1/MISO 15
PTE6 12
PTB5/TPM1CH1/SS 14
26 PTB0/KBI1P4/RxD1/ADP4
PTE5 13
PTB6/SDA/XTAL 11
Pins in bold are lost in the next lower pin count package.
Figure 2. 48-Pin QFN
MC9S08QE32 Series MCU Data Sheet, Rev. 7
4
Freescale Semiconductor
PTA4/ACMP1O/BKGD/MS
PTA5/IRQ/TPM1CLK/RESET
PTC4/TPM3CH4
PTC5/TPM3CH5/ACMP2O
PTE0/TPM2CLK
PTE1
PTE2
PTC6/RxD2/ACMP2+
PTC7/TxD2/ACMP2–
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP
44
43
42
41
40
39
38
37
36
35
34
Pin Assignments
7
27
VDD
VSSAD
8
26
PTA6/TPM1CH2/ADP8
VSS
9
25
PTA7/TPM2CH2/ADP9
10
24
PTB0/KBI1P4/RxD1/ADP4
23
PTB1/KBI1P5/TxD1/ADP5
PTB7/SCL/EXTAL
PTB6/SDA/XTAL 11
22
VREFL
PTB2/KBI1P6/SPSCK/ADP6
VSS
21
28
PTB3/KBI1P7/MOSI/ADP7
6
20
VREFH
PTC0/TPM3CH0
PTD4/KBI2P4
19
29
PTC1/TPM3CH1
5
18
VDDAD
PTD5/KBI2P5
PTD3/KBI2P3
17
30
PTD6/KBI2P6
4
16
VDD
PTD7/KBI2P7
PTD2/KBI2P2
15
31
PTC2/TPM3CH2
3
14
PTE7/TPM3CLK
PTC3/TPM3CH3
PTA3/KBI1P3/SCL/ADP3
13
32
PTB4/TPM2CH1/MISO
2
PTD0/KBI2P0
12
PTA2/KBI1P2/SDA/ADP2
1
PTB5/TPM1CH1/SS
33
PTD1/KBI2P1
Pins in bold are lost in the next lower pin count package.
Figure 3. 44-Pin LQFP
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
5
PTC5/TPM3CH5/ACMP2O
PTC6/RxD2/ACMP2+
PTC7/TxD2/ACMP2–
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1–
PTD0/KBI2P0
PTC4/TPM3CH4
1
PTA5/IRQ/TPM1CLK/RESET
PTD1/KBI2P1
PTA4/ACMP1O/BKGD/MS
Pin Assignments
32
31
30
29
28
27
26
25
4
21
VSSAD/VREFL
5
20
PTA6/TPM1CH2/ADP8
VSS
6
19
PTA7/TPM2CH2/ADP9
PTB7/SCL/EXTAL
7
18
PTB0/KBIP4/RxD1/ADP4
PTB6/SDA/XTAL
8
17
PTB1/KBIP5/TxD1/ADP5
9
10
11
12
13
14
15
16
PTB2/KBI1P6/SPSCK/ADP6
PTD2/KBI2P2
PTB3/KBI1P7/MOSI/ADP7
22
VDDAD/VREFH
PTC0/TPM3CH0
3
PTC1/TPM3CH1
PTA3/KBI1P3/SCL/ADP3
VDD
PTC2/TPM3CH2
23
PTC3/TPM3CH3
2
PTB4/TPM2CH1/MISO
PTA2/KBI1P2/SDA/ADP2
PTB5/TPM1CH1/SS
24
PTD3/KBI2P3
Pins in bold are lost in the next lower pin count package.
Figure 4. 32-Pin LQFP/QFN
MC9S08QE32 Series MCU Data Sheet, Rev. 7
6
Freescale Semiconductor
Pin Assignments
PTC5/TPM3CH5/ACMP2O
1
28
PTC6/RxD2/ACMP2+
PTC4/TPM3CH4
2
27
PTC7/TxD2/ACMP2–
PTA5/IRQ/TPM1CLK/RESET
3
26
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA4/ACMP1O/BKGD/MS
4
25
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1–
VDD
5
24
PTA2/KBI1P2/SDA/ADP2
VDDAD/VREFH
6
23
PTA3/KBI1P3/SCL/ADP3
VSSAD/VREFL
7
22
PTA6/TPM1CH2/ADP8
VSS
8
21
PTA7/TPM2CH2/ADP9
PTB7/SCL/EXTAL
9
20
PTB0/KBI1P4/RxD1/ADP4
PTB6/SDA/XTAL
10
19
PTB1/KBI1P5/TxD1/ADP5
PTB5/TPM1CH1/SS
11
18
PTB2/KBI1P6/SPSCK/ADP6
PTB4/TPM2CH1/MISO
12
17
PTB3/KBI1P7/MOSI/ADP7
PTC3/TPM3CH3
13
16
PTC0/TPM3CH0
PTC2/TPM3CH2
14
15
PTC1/TPM3CH1
Figure 5. 28-Pin SOIC
Table 1. MC9S08QE32 Series Pin Assignment by Package and Pin Sharing Priority
Pin Number
Port Pin
Highest
Alt 1
Alt 2
Alt 3
48
44
32
28
1
1
1
—
PTD1
KBI2P1
2
2
2
—
PTD0
KBI2P0
3
3
—
—
PTE7
TPM3CLK
Alt 4
4
4
3
5
VDD
5
5
4
6
VDDAD
6
6
7
7
5
7
8
8
9
9
6
8
VREFH
VREFL
VSSAD
VSS
10
10
7
9
PTB7
SCL1
11
11
8
10
PTB6
SDA1
12
—
—
—
PTE6
13
—
—
—
PTE5
14
12
9
11
PTB5
TPM1CH1 SS2
15
13
10
12
PTB4
TPM2CH1 MISO2
16
14
11
13
PTC3
TPM3CH3
17
15
12
14
PTC2
TPM3CH2
18
16
—
—
PTD7
KBI2P7
EXTAL
XTAL
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
7
Pin Assignments
Table 1. MC9S08QE32 Series Pin Assignment by Package and Pin Sharing Priority (continued)
Pin Number
48
44
32
28
Port Pin
19
17
—
—
PTD6
Highest
Alt 1
Alt 2
Alt 3
Alt 4
KBI2P6
20
18
—
—
PTD5
KBI2P5
21
19
13
15
PTC1
TPM3CH1
22
20
14
16
PTC0
TPM3CH0
23
21
15
17
PTB3
KBI1P7
MOSI2
ADP7
ADP6
24
22
16
18
PTB2
KBI1P6
SPSCK2
25
23
17
19
PTB1
KBI1P5
TxD1
ADP5
RxD1
ADP4
26
24
18
20
PTB0
KBI1P4
27
25
19
21
PTA7
TPM2CH2
ADP9
28
26
20
22
PTA6
TPM1CH2
ADP8
29
—
—
—
PTE4
30
27
—
—
VDD
31
28
—
—
VSS
32
29
—
—
PTD4
KBI2P4
33
30
21
—
PTD3
KBI2P3
34
31
22
—
PTD2
KBI2P2
35
32
23
23
PTA3
KBI1P3
SCL1
ADP3
ADP2
36
33
24
24
PTA2
KBI1P2
SDA1
37
34
25
25
PTA1
KBI1P1
TPM2CH0 ADP13
ACMP1–3
ADP03
ACMP1+3
38
35
26
26
PTA0
KBI1P0
TPM1CH0
39
36
27
27
PTC7
TxD2
ACMP2–
40
37
28
28
PTC6
RxD2
ACMP2+
41
—
—
—
PTE3
SS2
42
38
—
—
PTE2
MISO2
43
39
—
—
PTE1
MOSI2
44
40
—
—
PTE0
TPM2CLK SPSCK2
45
41
29
1
PTC5
TPM3CH5
46
42
30
2
PTC4
TPM3CH4
47
43
31
3
PTA5
IRQ
TPM1CLK RESET
48
44
32
4
PTA4
ACMP1O
BKGD
ACMP2O
MS
1
IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2; default reset
locations are PTA3 and PTA2.
2 SPI pins (SS, MISO, MOSI, and SPSCK) can be repositioned using SPIPS in SOPT2.
Default locations are PTB5, PTB4, PTB3, and PTB2.
3 If ADC and ACMP1 are enabled, both modules will have access to the pin.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
8
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08QE32 series of microcontrollers
available at the time of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
9
Electrical Characteristics
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
25
mA
Tstg
–55 to 150
C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
10
Freescale Semiconductor
Electrical Characteristics
Table 4. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Maximum junction temperature
Symbol
Value
Unit
TA
TL to TH
–40 to 85
C
TJM
95
C
Thermal resistance
Single-layer board
48-pin QFN
81
44-pin LQFP
68
JA
32-pin LQFP
66
32-pin QFN
92
28-pin SOIC
57
C/W
Thermal resistance
Four-layer board
48-pin QFN
26
44-pin LQFP
46
JA
32-pin LQFP
54
32-pin QFN
33
28-pin SOIC
42
C/W
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)
Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
11
Electrical Characteristics
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table 5. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Latch-up
Description
Symbol
Value
Unit
Series resistance
R1
1500
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
Series resistance
R1
0
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
Table 6. ESD and Latch-Up Protection Characteristics
No.
1
3.6
Rating1
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
2000
—
V
2
Machine model (MM)
VMM
200
—
V
3
Charge device model (CDM)
VCDM
500
—
V
4
Latch-up current at TA = 85C
ILAT
100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
12
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics
Num C
Characteristic
Symbol
Min
Typical1
Max
Unit
2.0
1.8
—
3.6
V
VDD – 0.5
—
—
2.7 V, ILoad = –10 mA VDD – 0.5
2.3 V, ILoad = –6 mA VDD – 0.5
—
—
—
—
VDD – 0.5
—
—
—
—
100
1.8 V, ILoad = 2 mA
—
—
0.5
2.7 V, ILoad = 10 mA
—
—
0.5
2.3 V, ILoad = 6 mA
—
—
0.5
1.8 V, ILoad = 3 mA
—
—
0.5
—
—
100
VDD 2.3 V
0.70 x VDD
—
—
VDD 1.8 V
0.85 x VDD
—
—
VDD 2.7 V
—
—
0.35 x VDD
VDD 1.8 V
—
—
0.30 x VDD
0.06 x VDD
—
—
mV
Condition
Operating Voltage
1
VDD rising
VDD falling
C
2
All I/O pins,
low-drive strength
Output high
voltage2
P
All I/O pins,
high-drive strength
T
1.8 V, ILoad = –2 mA
VOH
1.8V, ILoad = –3 mA
C
3
D
Output high
current
Max total IOH for all ports
All I/O pins,
low-drive strength
C
4
IOHT
P Output low
voltage
T
All I/O pins,
high-drive strength
VOL
C
Output low
current
6
P Input high
C voltage
7
P Input low
C voltage
all digital inputs
VIL
8
Input
C
hysteresis
all digital inputs
Vhys
9
Input
P leakage
current
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
—
—
1
A
10
Hi-Z
(off-state)
P
leakage
current
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
—
1
A
11
Total
leakage
combined
C
for all inputs
and Hi-Z
pins
VIn = VDD or VSS
—
—
2
A
11
Pullup,
P Pulldown
resistors
17.5
—
52.5
k
–0.2
—
0.2
mA
–5
—
5
mA
CIn
—
—
8
pF
VRAM
—
0.6
1.0
V
VPOR
0.9
1.4
2.0
V
5
all digital inputs
VIH
V
D
DC injection
D current 3, 4,
IOLT
mA
5
12
Max total IOL for all ports
V
All input only and I/O |IOZTOT|
all digital inputs, when
enabled
Single pin limit
Total MCU limit, includes
sum of all stressed pins
13
C Input Capacitance, all pins
14
C RAM retention voltage
15
RPU,
RPD
6
C POR re-arm voltage
IIC
VIN < VSS, VIN > VDD
mA
V
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
13
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
2
3
4
5
6
7
Symbol
Condition
tPOR
Min
Typical1
Max
Unit
10
—
—
s
16
D POR re-arm time
17
P
Low-voltage detection threshold —
high range
VLVDH
VDD falling
VDD rising
2.11
2.16
2.16
2.21
2.22
2.27
V
18
P
Low-voltage detection threshold —
low range
VLVDL
VDD falling
VDD rising
1.80
1.88
1.82
1.90
1.91
1.99
V
19
P
Low-voltage warning threshold —
high range
VLVWH
VDD falling
VDD rising
2.36
2.36
2.46
2.46
2.56
2.56
V
20
P
Low-voltage warning threshold —
low range
VLVWL
VDD falling
VDD rising
2.11
2.16
2.16
2.21
2.22
2.27
V
21
C
Low-voltage inhibit reset/recover
hysteresis
Vhys
—
80
—
mV
22
P Bandgap Voltage Reference7
VBG
1.15
1.17
1.18
V
Typical values are measured at 25 C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or
if clock rate is very low (which would reduce overall power consumption).
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 3.0 V, Temp = 25 C
PULLUP RESISTOR TYPICALS
PULL-UP RESISTOR (k)
40
85C
25C
–40C
35
30
25
20
1.8
2
2.2
2.4
2.6 2.8
VDD (V)
3
3.2
3.4
3.6
PULLDOWN RESISTANCE (k)
1
Characteristic
PULLDOWN RESISTOR TYPICALS
40
85C
25C
–40C
35
30
25
20
1.8
2.3
2.8
VDD (V)
3.3
3.6
Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
MC9S08QE32 Series MCU Data Sheet, Rev. 7
14
Freescale Semiconductor
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.0 V
1.2
85C
25C
–40C
1
0.15
VOL (V)
0.8
VOL (V)
TYPICAL VOL VS VDD
0.2
0.6
0.4
0.2
0.1
85C, IOL = 2 mA
25C, IOL = 2 mA
–40C, IOL = 2 mA
0.05
0
0
0
5
10
IOL (mA)
15
1
20
2
3
VDD (V)
4
Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
85C
25C
–40C
0.8
85C
25C
–40C
0.3
VOL (V)
VOL (V)
0.6
0.4
0.2
0.2
IOL = 10 mA
IOL = 6 mA
0.1
0
IOL = 3 mA
0
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
1.2
85C, IOH = 2 mA
25C, IOH = 2 mA
–40C, IOH = 2 mA
0.2
VDD – VOH (V)
VDD – VOH (V)
1
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.25
85C
25C
–40C
0.8
0.6
0.4
0.15
0.1
0.05
0.2
0
0
0
–5
–10
IOH (mA))
–15
–20
1
2
VDD (V)
3
4
Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
15
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.4
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
0.3
85C
25C
–40C
0.6
VDD – VOH (V)
VDD – VOH (V)
0.8
0.4
0.2
0
0
–5
–10
–15
–20
IOH (mA)
85C
25C
–40C
–25
0.2
IOH = –10 mA
IOH = –6 mA
0.1
–30
IOH = –3 mA
0
1
2
3
4
VDD (V)
Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Num
C
Parameter
Symbol
Bus
Freq
VDD
(V)
P
Temp
(C)
Typical1
Max
13
14
–40 to 25
14
15
85
13.75
—
Unit
25.165 MHz
P
1
T
Run supply current
FEI mode, all modules on
RIDD
20 MHz
3
T
8 MHz
5.59
—
T
1 MHz
1.03
—
C
25.165 MHz
11.5
12.3
9.5
—
8 MHz
4.6
—
1 MHz
1.0
—
152
—
115
—
T
2
T
Run supply current
FEI mode, all modules off
20 MHz
RIDD
T
T
3
T
Run supply current
LPRS = 0, all modules off
T
Run supply current
LPRS = 1, all modules off,
running from Flash
T
Run supply current
LPRS = 1, all modules off,
running from RAM
4
16 kHz FBILP
RIDD
T
T
T
3
16 kHz FBELP
mA
–40 to 85
A
–40 to 85
A
–40 to 85
mA
–-40 to 85
—
RIDD
16 kHz FBELP
3
7.3
—
25.165 MHz
Wait mode supply current
FEI mode, all modules off
–40 to 85
21.9
C
5
3
mA
5.74
6.00
4.57
—
8 MHz
2
—
1 MHz
0.73
—
20 MHz
WIDD
3
MC9S08QE32 Series MCU Data Sheet, Rev. 7
16
Freescale Semiconductor
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num
Parameter
C
Symbol
0.35
0.65
–40 to 25C
0.8
1.0
70
—
2.0
4.5
—
0.25
0.50
–40 to 25
0.65
0.85
70
C
—
Stop2 mode supply current
S2IDD
C
Temp
(C)
Max
—
P
VDD
(V)
Typical1
P
6
3
A
85
—
C
—
1.5
3.5
85
P
—
0.45
1.00
–40 to 25
C
—
1.5
2.3
70
—
4
8
—
0.35
0.70
–40 to 25
1
2
70
85
P
C
Stop3 mode supply current
no clocks active
S3IDD
2
Unit
C
7
1
Bus
Freq
3
C
—
2
C
—
3.5
6.0
A
8
T
EREFSTEN=1
32 kHz
500
—
nA
9
T
IREFSTEN=1
32 kHz
70
—
A
10
T
TPM PWM
100 Hz
12
—
A
11
T
15
—
A
200
—
nA
SCI, SPI, or IIC
Low power
mode adders:
300 bps
3
RTC using LPO
1 kHz
T
RTC using
ICSERCLK
32 kHz
1
—
A
14
T
LVD
n/a
100
—
A
15
T
ACMP
n/a
20
—
A
12
T
13
85
–40 to 85
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
Table 9. Stop Mode Adders
Temperature
Num
C
Parameter
Condition
Units
–40C
25C
70C
85C
50
75
100
150
nA
1000
1000
1100
1500
nA
1
T
LPO
—
2
T
ERREFSTEN
RANGE = HGO = 0
3
T
IREFSTEN1
—
63
70
77
81
A
4
T
RTC
Does not include clock source
current
50
75
100
150
nA
5
T
LVD1
LVDSE = 1
90
100
110
115
A
6
7
T
ACMP
Not using the bandgap (BGBE = 0)
18
20
22
23
A
T
ADC1
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
95
106
114
120
A
1
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
17
Electrical Characteristics
1
Not available in stop2 mode.
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 11 and Figure 12 for crystal or resonator circuits.
Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85C Ambient)
Num
1
2
Symbol
Min
Typical1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
Load capacitors
Low range (RANGE=0), low power (HGO=0)
D
Other oscillator settings
C1
C2
C
Characteristic
3
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
D
Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
4
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
8 MHz
4 MHz
1 MHz
5
6
Crystal start-up time 4
Low range, low power
Low range, high power
C
High range, low power
High range, high power
RF
RS
t
CSTL
t
CSTH
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
D
FBE or FBELP mode
fextal
See Note 2
See Note 3
—
—
—
—
10
1
—
—
—
—
—
—
—
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
200
400
5
15
—
—
—
—
0.03125
0
—
—
40
40
M
k
ms
MHz
MHz
Data in Typical column is characterized at 3.0 V, 25 C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
3 See crystal or resonator manufacturer’s recommendation.
4
Proper PC board layout procedures must be followed to achieve specifications.
1
2
MC9S08QE32 Series MCU Data Sheet, Rev. 7
18
Freescale Semiconductor
Electrical Characteristics
XOSCVLP
EXTAL
XTAL
RF
RS
Crystal or Resonator
C1
C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient)
Symbol
Min
Typical1
Max
Unit
fint_t
—
32.768
—
kHz
fint_ut
31.25
—
39.06
kHz
tIRST
—
5
10
s
16
—
20
32
—
40
High range (DFR = 10)
48
—
60
Low range (DFR = 00)
—
19.92
—
—
39.85
—
—
59.77
—
Num
C
Characteristic
1
P
2
C Average internal reference frequency — untrimmed
3
T
Average internal reference frequency — factory trimmed
Internal reference start-up time
Low range (DFR = 00)
P
4
P
DCO output frequency
trimmed2
P
P
5
P
P
DCO output frequency2
reference = 32768 Hz
and
DMX32 = 1
Mid range (DFR = 01)
Mid range (DFR = 01)
fdco_u
fdco_DMX32
High range (DFR = 10)
MHz
MHz
6
C
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (using FTRIM)
fdco_res_t
—
0.1
0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (not using FTRIM)
fdco_res_t
—
0.2
0.4
%fdco
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
19
Electrical Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
8
C
Total deviation of trimmed DCO output frequency over voltage
and temperature
fdco_t
—
0.5
–1.0
2
%fdco
9
C
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0 C to 70 C
fdco_t
—
0.5
1
%fdco
10
C FLL acquisition time3
tAcquire
—
—
1
ms
11
C
CJitter
—
0.02
0.2
%fdco
Long term jitter of DCO output clock (averaged over 2-ms
interval)4
Data in Typical column is characterized at 3.0 V, 25 C or is typical recommended value.
The resulting bus clock frequency must not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
1
2
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Control Timing
Table 12. Control Timing
Num
C
Rating
Bus frequency (tcyc = 1/fBus)
VDD 2.1V
2.1 2.4Vs
Symbol
Min
Typical1
fBus
DC
—
Max
10
20
25.165
Unit
1
D
2
D
Internal low power oscillator period
tLPO
700
—
1300
s
3
D
External reset pulse width2
textrst
100
—
—
ns
4
D
Reset low drive
trstdrv
34 tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
s
7
D
100
1.5 tcyc
—
—
—
—
ns
MHz
IRQ pulse width
Asynchronous path2 tILIH, tIHIL
Synchronous path4
MC9S08QE32 Series MCU Data Sheet, Rev. 7
20
Freescale Semiconductor
Electrical Characteristics
Table 12. Control Timing (continued)
Num
C
8
D
Min
Typical1
Max
Unit
100
1.5 tcyc
—
—
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
tRise, tFall
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
—
—
8
31
—
—
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
,t
t
Slew rate control disabled (PTxSE = 0) Rise Fall
Slew rate control enabled (PTxSE = 1)
—
—
7
24
—
—
Voltage regulator recovery time
—
4
—
Rating
Symbol
Keyboard interrupt pulse width
Asynchronous path2 tILIH, tIHIL
Synchronous path5
9
10
C
C
tVRR
ns
ns
s
Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 C to 85 C.
1
2
textrst
RESET PIN
Figure 13. Reset Timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 14. IRQ/KBIPx Timing
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
21
Electrical Characteristics
Table 13. TPM Input Timing
No.
C
1
D
2
Function
Symbol
Min
Max
Unit
External clock frequency
fTCLK
0
fBus/4
Hz
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 15. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 16. Timer Input Capture Pulse
3.10.3
SPI Timing
Table 14 and Figure 17 through Figure 20 describe the timing requirements for the SPI system.
Table 14. SPI Timing
No.
C
Function
Symbol
Min
Max
Unit
—
D
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/21
fBus/4
Hz
1
D
SPSCK period
Master
Slave
tSPSCK
2
4
2048
—
tcyc
tcyc
2
D
Enable lead time
Master
Slave
tLead
12
1
—
—
tSPSCK
tcyc
3
D
Enable lag time
Master
Slave
tLag
12
1
—
—
tSPSCK
tcyc
MC9S08QE32 Series MCU Data Sheet, Rev. 7
22
Freescale Semiconductor
Electrical Characteristics
Table 14. SPI Timing (continued)
1
No.
C
Function
Symbol
Min
Max
Unit
4
D
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
5
D
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
6
D
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
D
Slave access time
ta
—
1
tcyc
8
D
Slave MISO disable time
tdis
—
1
tcyc
9
D
Data valid (after SPSCK edge)
Master
Slave
tv
—
—
25
25
ns
ns
10
D
Data hold time (outputs)
Master
Slave
tHO
0
0
—
—
ns
ns
11
D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
Max operating frequency limited to 8 MHz when input filter disabled and high output drive strength enabled. Max
operating frequency limited to 5 MHz when input filter enabled and high output drive strength disabled.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
23
Electrical Characteristics
SS1
(OUTPUT)
11
1
2
SPSCK
(CPOL = 0)
(OUTPUT)
3
4
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
9
LSB IN
10
9
MOSI
(OUTPUT)
BIT 6 . . . 1
MSB OUT2
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN(2)
LSB IN
10
9
MOSI
(OUTPUT) PORT DATA
BIT 6 . . . 1
MASTER MSB OUT(2)
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA = 1)
MC9S08QE32 Series MCU Data Sheet, Rev. 7
24
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
MSB OUT
SLAVE
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
6
5
MOSI
(INPUT)
10
10
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 19. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
12
11
11
12
SPSCK
(CPOL = 0)
(INPUT)
4
4
SPSCK
(CPOL = 1)
(INPUT)
10
9
MISO
(OUTPUT)
SEE
NOTE
7
MOSI
(INPUT)
SLAVE
MSB OUT
5
BIT 6 . . . 1
8
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 20. SPI Slave Timing (CPHA = 1)
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
25
Electrical Characteristics
3.11
Analog Comparator (ACMP) Electricals
Table 15. Analog Comparator Electrical Specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
VDD
1.8
—
3.6
V
D
Supply voltage
P
Supply current (active)
IDDAC
—
20
35
A
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
P
Analog input offset voltage
VAIO
—
20
40
mV
C
Analog comparator hysteresis
VH
3.0
9.0
15.0
mV
P
Analog input leakage current
IALKG
—
—
1.0
A
C
Analog comparator initialization delay
tAINIT
—
—
1.0
s
3.12
ADC Characteristics
Table 16. 12-Bit ADC Operating Conditions
C
Supply voltage
D
D
Symb
Min
Typical1
Max
Unit
Comment
Absolute
VDDAD
1.8
—
3.6
V
—
Delta to VDD (VDD –
VDDAD)2
VDDAD
–100
0
100
mV
—
VSSAD
–100
0
100
mV
—
Characteristic
Conditions
Ground voltage
Delta to VSS (VSS –
VSSAD)2
D
Input voltage
—
VADIN
VREFL
—
VREFH
V
—
C
Input
capacitance
—
CADIN
—
4.5
5.5
pF
—
C
Input
resistance
—
RADIN
—
5
7
k
—
—
—
—
—
2
5
k
External to
MCU
MHz
—
Analog source
resistance
12-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
10-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
C
RAS
8-bit mode (all valid fADCK)
D
ADC
conversion
clock freq.
High speed (ADLPC = 0)
Low power (ADLPC = 1)
fADCK
—
—
—
—
5
10
—
—
10
0.4
—
8.0
0.4
—
4.0
Typical values assume VDDAD = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.
1
MC9S08QE32 Series MCU Data Sheet, Rev. 7
26
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
–
CAS
+
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 21. ADC Input Impedance Equivalency Diagram
Table 17. ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Symbol
Min
Typ1
Max
Unit
T
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
IDDAD
—
120
—
A
T
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
IDDAD
—
202
—
A
T
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
IDDAD
—
288
—
A
P
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
IDDAD
—
0.532
1
mA
ADC
asynchronous
clock source
2
3.3
5
P
C
Characteristic
Conditions
High speed (ADLPC = 0)
Low power (ADLPC = 1)
fADACK
MHz
1.25
2
3.3
Comment
tADACK =
1/fADACK
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
27
Electrical Characteristics
Table 17. ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Min
Typ1
Max
—
20
—
—
40
—
—
3.5
—
—
23.5
—
—
1.646
—
—
1.769
—
—
701.2
—
—
–1 to 3
–2.5 to 5.5
—
–1 to 3
–3.0 to 6.5
10-bit mode
—
1
2.5
P
8-bit mode
—
0.5
1.0
T
12-bit mode
—
1.0
–1.5 to 2.0
—
0.5
1.0
C
Characteristic
P
Conversion
time (including
sample time)
Conditions
Symbol
Short sample (ADLSMP = 0)
Long sample (ADLSMP = 1)
tADC
Short sample (ADLSMP = 0)
P
Sample time
Long sample (ADLSMP = 1)
D
D
Temp sensor
slope
Temp sensor
voltage
T
T
P
P
tADS
–40 C– 25 C
m
25 C– 85 C
25 C
VTEMP25
12-bit mode, 3.6> VDDAD > 2.7
Total
unadjusted
error
Differential
non-linearity
12-bit mode, 2.7> VDDAD >
1.8V
10-bit mode3
P
8-bit mode3
—
0.3
0.5
T
12-bit mode
—
1.5
–2.5 to
2.75
—
0.5
1.0
8-bit mode
—
0.3
0.5
12-bit mode
—
1.5
2.5
—
0.5
1.5
T
Integral
non-linearity
T
T
P
Zero-scale
error
10-bit mode
10-bit mode
INL
EZS
P
8-bit mode
—
0.5
0.5
T
12-bit mode
—
1.0
–3.5 to 1.0
—
0.5
1
8-bit mode
—
0.5
0.5
12-bit mode
—
–1 to 0
—
—
—
0.5
8-bit mode
—
—
0.5
12-bit mode
—
2
—
—
0.2
4
—
0.1
1.2
P
Full-scale error
P
D
D
Quantization
error
Input leakage
error
10-bit mode
10-bit mode
10-bit mode
8-bit mode
EFS
EQ
EIL
Comment
ADCK
cycles
See
reference
manual for
conversion
time
variances
ADCK
cycles
mV/C
ETUE
DNL
Unit
mV
LSB2
Includes
quantization
LSB2
LSB2
LSB2
VADIN =
VSSAD
LSB2
VADIN =
VDDAD
LSB2
LSB2
Pad
leakage4 *
RAS
MC9S08QE32 Series MCU Data Sheet, Rev. 7
28
Freescale Semiconductor
Electrical Characteristics
Typical values assume VDDAD = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (VREFH – VREFL)/2N
3
Monotonicity and No-missing-codes guaranteed in 10-bit and 8-bit modes
4
Based on input pad leakage current. Refer to pad electricals.
1
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see MC9S08QE32 Series Reference
Manual Chapter 4 Memory.
Table 18. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage for program/erase
–40 C to 85 C
Vprog/erase
1.8
—
3.6
V
D
Supply voltage for read operation
VRead
1.8
—
3.6
V
fFCLK
150
—
200
kHz
tFcyc
5
—
6.67
s
frequency1
D
Internal FCLK
D
Internal FCLK period (1/FCLK)
P
P
P
P
Byte program time (random
Byte program time (burst
location)(2)
mode)(2)
tprog
9
tFcyc
tBurst
4
tFcyc
Page erase
time2
tPage
4000
tFcyc
Mass erase
time(2)
tMass
20,000
tFcyc
Byte program
Page erase
current3
current3
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
10,000
—
100,000
—
—
cycles
15
100
—
years
endurance4
C
Program/erase
TL to TH = –40 C to 85 C
T = 25 C
C
Data retention5
tD_ret
1
The frequency of this clock is controlled by software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information is
supplied for calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
2
MC9S08QE32 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
29
Ordering Information
4
Ordering Information
This section contains ordering information for the MC9S08QE32 series of MCUs.
Example of the device numbering system:
MC 9 S08 QE 32
C XX
Status
(MC = Fully Qualified)
Package designator (see Table 19)
Temperature range
(C = –40 C to 85 C)
Memory
(9 = Flash-based)
Core
Approximate flash size in kbytes
Family
5
Package Information
Table 19. Package Descriptions
Pin Count
5.1
Package Type
Abbreviation
Designator
Case No.
Document No.
48
Quad Flat No-Leads
QFN
FT
1314
98ARH99048A
44
Low Quad Flat Package
LQFP
LD
824D
98ASS23225W
32
Low Quad Flat Package
LQFP
LC
873A
98ASH70029A
32
Quad Flat No-Leads
QFN
FM
1582
98ARE10566D
28
Small Outline Integrated Circuit
SOIC
WL
751F
98ASB42345B
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 19. For the latest
available drawings please visit our web site (http://www.freescale.com) and enter the package’s document
number into the keyword search box.
MC9S08QE32 Series MCU Data Sheet, Rev. 7
30
Freescale Semiconductor
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personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of
Freescale Semiconductor, Inc. All other product or service names
are the property of their respective owners.
© Freescale Semiconductor, Inc. 2008-2011. All rights reserved.
MC9S08QE32
Rev. 7
9/2011
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