0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
MCF54415CMJ250

MCF54415CMJ250

  • 厂商:

    NXP(恩智浦)

  • 封装:

    LBGA256

  • 描述:

    IC MCU 32BIT 256MAPBGA

  • 数据手册
  • 价格&库存
MCF54415CMJ250 数据手册
Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF54418 Rev. 8, 06/2012 MCF5441x MAPBGA–256 17mm x 17mm MAPBGA–196 12 mm x 12 mm MCF5441x ColdFire Microprocessor Data Sheet • • • • • • • • • • • • • • • Version 4 ColdFire Core with EMAC and MMU Up to 385 Dhrystone 2.1 MIPS @ 250 MHz 8 KB instruction cache and 8 KB data cache 64 KB internal SRAM dual-ported to processor local bus and other crossbar switch masters System boot from NOR, NAND, SPI flash, EEPROM, or FRAM Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters 64-channel DMA controller SDRAM controller supporting full-speed operation from a single x8 DDR2 component up to 250 MHz 32-bit FlexBus external memory interface for RAM, ROM, MRAM, and programmable logic USB 2.0 host controller USB 2.0 host/device/On-the-Go controller 8-bit single data rate ULPI port usable by the dedicated USB host module or the USB host/device/OTG module Dual 10/100 Ethernet MACs with hardware CRC checking/generation, IEEE 1588-2002 support, and optional Ethernet switch CPU direct-attached hardware accelerator for DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms Random number generator • • • • • • • • • • • • • • • • • • Enhanced Secure Digital host controller for SD, SDHC, SDIO, MMC, and MMCplus cards Two ISO7816 smart card interfaces Two FlexCAN modules Six I2C bus interfaces with DMA support in master mode Two synchronous serial interfaces Four 32-bit timers with DMA support Four programmable interrupt timers 8-channel, 16-bit motor control PWM timer Dual 12-bit ADCs with shared input channels and multiple conversion trigger sources Dual 12-bit DACs with DMA support 1-wire module with DMA support NAND flash controller Real-time clock with 32-kHz oscillator, 2 KB standby SRAM, and battery backup supply input Up to four DMA-supported serial peripheral interfaces (DSPI) Up to ten UARTs with single-wire mode support Up to five external IRQ interrupts and 2 external DMA request/acknowledge pairs Up to 16 processor local bus Rapid GPIO pins Up to 87 standard GPIO pins This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2011-2012. All rights reserved. Table of Contents 1 2 3 4 MCF5441x family comparison . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5 2.1 Power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2 Supply voltage sequencing . . . . . . . . . . . . . . . . . . . . . . .7 2.2.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . .8 2.2.2 Power-down sequence . . . . . . . . . . . . . . . . . . . .8 2.3 Power consumption specifications . . . . . . . . . . . . . . . . .8 Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .9 3.1 Signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .20 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21 4.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .22 4.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.4 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .23 4.6 Output pad loading and slew rate . . . . . . . . . . . . . . . . .25 4.7 DDR pad drive strengths. . . . . . . . . . . . . . . . . . . . . . . .26 4.8 Oscillator and PLL electrical characteristics . . . . . . . . .26 4.9 Reset timing specifications . . . . . . . . . . . . . . . . . . . . . .28 4.10 FlexBus timing specifications . . . . . . . . . . . . . . . . . . . .28 4.11 NAND flash controller (NFC) timing specifications . . . .30 4.12 DDR SDRAM controller timing specifications . . . . . . . .33 4.13 USB transceiver timing specifications . . . . . . . . . . . . . .35 4.14 ULPI timing specifications. . . . . . . . . . . . . . . . . . . . . . .35 4.15 eSDHC timing specifications. . . . . . . . . . . . . . . . . . . . .36 4.15.1 eSDHC timing specifications . . . . . . . . . . . . . . .37 5 6 7 4.15.2 eSDHC electrical DC characteristics . . . . . . . . 4.16 SIM timing specifications . . . . . . . . . . . . . . . . . . . . . . . 4.16.1 General timing requirements . . . . . . . . . . . . . . 4.16.2 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . 4.16.3 Power-down sequence . . . . . . . . . . . . . . . . . . . 4.17 SSI timing specifications . . . . . . . . . . . . . . . . . . . . . . . 4.18 12-bit ADC specifications . . . . . . . . . . . . . . . . . . . . . . 4.19 12-bit DAC timing specifications . . . . . . . . . . . . . . . . . 4.20 mcPWM timing specifications . . . . . . . . . . . . . . . . . . . 4.21 I2C timing specifications . . . . . . . . . . . . . . . . . . . . . . . 4.22 Ethernet assembly timing specifications . . . . . . . . . . . 4.22.1 Receive signal timing specifications. . . . . . . . . 4.22.2 Transmit signal timing specifications . . . . . . . . 4.22.3 Asynchronous input signal timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22.4 MDIO serial management timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 32-bit timer module timing specifications. . . . . . . . . . . 4.24 DSPI timing specifications . . . . . . . . . . . . . . . . . . . . . . 4.25 SBF timing specifications . . . . . . . . . . . . . . . . . . . . . . 4.26 1-Wire timing specifications. . . . . . . . . . . . . . . . . . . . . 4.27 General purpose I/O timing specifications. . . . . . . . . . 4.28 Rapid general purpose I/O timing specifications . . . . . 4.29 JTAG and boundary scan timing specifications . . . . . . 4.30 Debug AC timing specifications . . . . . . . . . . . . . . . . . . Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 39 39 40 41 43 44 45 45 46 47 47 48 48 49 49 52 53 53 53 54 56 57 57 58 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 2 Freescale Semiconductor MCF5441x JTAG Version 4 ColdFire Core 8 KB Instruction Cache 8 KB Data Cache EMAC BDM Hardware Divide CAU MMU RGPIO 64 KB SRAM PLL Oscillator PLL 2 Ethernet Controllers eDMA USB Host L2 Switch Serial Boot Facility eSDHC USB OTG NAND Flash Controller Crossbar Switch (XBS) Peripheral Bus Controller 1 Peripheral Bus Controller 0 FlexBus Smart Card ADC 2 DACs 1 Wire mcPWM RTC & kHz Oscillator RNG EPORT 2 DSPIs 4 I2Cs GPIO 6 UARTs 2 SSIs 2 FlexCANs 2 I2Cs 2 DSPIs 3 INTCs 4 UARTs 4 PITs 4 DMA Timers ADC BDM CAU DAC DSPI eDMA eSDHC EMAC EPORT GPIO I2 C – Analog-to-digital converter – Background debug module – Cryptography acceleration unit – Digital-to-analog – DMA serial peripheral interface – Enhanced direct memory access module – Enhanced Secure Digital host controller – Enhanced multiply-accumulate unit – Edge port module – General purpose input/output module – Inter-Integrated Circuit DDR2 Controller Note: Each of the crossbar switch masters, the FlexBus and SDRAM controller have access to peripheral bus controller 0, which is not shown. INTC JTAG mcPWM PIT PLL RGPIO RNG RTC SSI USB OTG – Interrupt controller – Joint Test Action Group interface – Motor control pulse width modulator – Programmable interrupt timers – Phase locked loop module – Rapid GPIO – Random number generator – Real time clock – Synchronous serial interface – Universal Serial Bus On-the-Go controller MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 3 MCF5441x family comparison 1 MCF5441x family comparison Table 1. MCF5441x family configurations Module MCF54410 MCF54415 MCF54416 MCF54417 MCF54418 Version 4 ColdFire core with EMAC (enhanced multiply-accumulate unit) and MMU (memory management unit)      Cryptography acceleration unit (CAU) — —  —  Core (system) and SDRAM clock up to 250 MHz Peripheral clock (Core clock  2) up to 125 MHz External bus (FlexBus) clock up to 100 MHz Performance (Dhrystone 2.1 MIPS) up to 385 Static RAM (SRAM) 64 KB Independent data/instruction cache 8 KB each USB 2.0 Host controller —     USB 2.0 Host/Device/On-the-Go controller      UTMI+ Low Pin Interface (ULPI) for external high-speed USB PHY —     10/100 Mbps Ethernet controller with IEEE 1588 support 1 2 2 2 2 Level 2 IEEE 1588-compliant 3-port Ethernet switch — — —   Enhanced Secure Digital host controller (eSDHC)      Smart card/Subscriber Identity Module (SIM) — 2 ports 2 ports 2 ports 2 ports UARTs 6 10 10 10 10 DSPI 3 4 4 4 4 CAN 2.0B controllers 1 2 2 2 2 I C 4 6 6 6 6 Synchronous serial interface (SSI) 1 2 2 2 2 12-bit ADC —     12-bit DAC — 2 2 2 2 32-bit DMA timers 4 4 4 4 4 Periodic interrupt timers (PIT) 4 4 4 4 4 Motor control PWM timer (mcPWM) — 8 channel 8 channel 8 channel 8 channel 64-channel DMA controller      Real-time clock with 2 KB standby RAM and battery back-up input      DDR2 SDRAM controller      FlexBus external memory controller      2 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 4 Freescale Semiconductor Hardware design considerations Table 1. MCF5441x family configurations (continued) Module MCF54410 MCF54415 MCF54416 MCF54417 MCF54418      1-Wire interface      Serial boot facility      Watchdog timer      Interrupt controllers (INTC) 3 3 3 3 3 Edge port module (EPORT) 3 IRQs 5 IRQs 5 IRQs 5 IRQs 5 IRQs Rapid GPIO pins 9 16 16 16 16 General-purpose I/O (GPIO) pins 48 87 87 87 87      NAND flash controller ® ® JTAG - IEEE 1149.1 Test Access Port Package 1.1 196 MAPBGA 256 MAPBGA Ordering information Table 2. Orderable part numbers Freescale Part Number Description Package MCF54410CMF250 MCF54410 Microprocessor 196 MAPBGA MCF54415CMJ250 MCF54415 Microprocessor MCF54416CMJ250 MCF54416 Microprocessor Speed Temperature 250 MHz –40 to +85C 256 MAPBGA MCF54417CMJ250 MCF54417 Microprocessor MCF54418CMJ250 MCF54418 Microprocessor 2 Hardware design considerations 2.1 Power filtering To further enhance noise isolation, an external filter is strongly recommended for the analog VDD pins (VDDA_PLL and VDDA_DAC_ADC). The filter shown in Figure 1 should be connected between the board 3.3 V (nominal) supply and the analog pins. The resistor and capacitors should be placed as close to the dedicated analog VDD pin as possible. The 10  resistor in the given filter is required. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 5 Hardware design considerations 10  VDD_OSC_A_PLL EVDD Pin 1 µF 0.1 µF VSS_OSC 100 MHz GND Figure 1. Oscillator/PLL/DAC power filter Figure 2 shows an example for isolating the ADC power supply from the I/O supply (EVDD) and ground. Note that in this power supply the 10  resistor is replaced by a 0  resistor. This will reduce the IR drop into the ADC, limiting additional gain error. 0 Board 3.3 V supply VDDA_ADC 10 µF 0.1 µF GND Figure 2. ADC power filter Figure 3 shows an example for bypassing the internal core digital power supply for the MPU. This bypass should be applied to as many IVDD signals as routing allows. Each one should be placed as close to the ball as possible. Board 1.2 V supply IVDD 1 µF 0.1 µF GND Figure 3. IVDD power filter Figure 4 shows an example for bypassing the external pad ring digital power supply for the MPU. This bypass should be applied to as many EVDD signals as routing allows. Each one should be placed as close to the ball as possible. Board 3.3 V supply EVDD 1 µF 0.1 µF GND Figure 4. EVDD power filter MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 6 Freescale Semiconductor Hardware design considerations Figure 5 shows an example for bypassing the FlexBus power supply for the MPU. This bypass should be applied to as many FB_VDD signals as routing allows. Each one should be placed as close to the ball as possible. Board 1.8–3.3 V supply FB_VDD 1 µF 0.1 µF GND Figure 5. FB_VDD power filter 2.2 Supply voltage sequencing Figure 6 shows requirements in the sequencing of the I/O VDD (EVDD), FlexBus VDD (FBVDD), SDRAM VDD (SDVDD), PLL VDD (VDD_OSC_A_PLL), and internal logic/core VDD (IVDD). EVDD/FBVDD (3.3V) 3.3V DC Power Supply Voltage Supplies stable 2.5V SDVDD (2.5V — DDR) 1.8V SDVDD/FBVDD (1.8V — DDR2) 1.5V IVDD, VDD_OSC_A_PLL 0 Time Notes: 1 Input voltage must not be greater than the supply voltage (EVDD, FBVDD, SDVDD, IVDD, or PVDD) by more than 0.5V at any time, including during power-up. 2 Use 25 V/millisecond or slower rise time for all supplies. Figure 6. Supply voltage sequencing and separation cautions The relationships between FBVDD, SDVDD and EVDD are non-critical during power-up and power-down sequences. FBVDD (1.8 – 3.3V), SDVDD (2.5V or 1.8V) and EVDD are specified relative to IVDD. NOTE All I/O VDD pins must be powered on when the device is functioning, except when in standby mode. In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can be switched off. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 7 Hardware design considerations 2.2.1 Power-up sequence If EVDD/FBVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/FBVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/FBVDD/SDVDD powers up before IVDD must power up. IVDD should not lead the EVDD, FBVDD, or SDVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 25 V/millisecond to avoid turning on the internal ESD protection clamp diodes. 2.2.2 Power-down sequence If IVDD/PVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PVDD power down before EVDD, FBVDD, or SDVDD must power down. IVDD should not lag EVDD, FBVDD, or SDVDD going low by more than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. 2. 2.3 Drop IVDD/PVDD to 0 V. Drop EVDD/FBVDD/SDVDD supplies. Power consumption specifications Table 3. Estimated power consumption specifications Characteristic Core operating supply current (nominal 1.2 V)1 Run mode Wait mode Doze mode Stop00 mode Stop01 mode Stop02 mode Stop03 mode Symbol Unit 127 33 32 9.3 9.2 3.6 3.4 mA 80 49 42 40 28 mA 3 15 15 mA IVDD FlexBus operating supply current Run mode (application dependent) Wait mode Doze mode Stop00 mode Stop01, Stop02, Stop03 mode FBVDD SDRAM operating supply current (DDR2 at 1.8 V) Isys(DQ) [8, 2DQS] Isys(WR) [8, 2DQS] Isys(RD) [8, 2DQS] SDRAM input reference current Isys(REF) SDRAM termination current Isys(termRD) SDVDD SDVREF 1.3 SDVTT 41 Total SDIDD MPU side2 Oscillator/PLL operating supply current (nominal 3.3 V) Run, Wait, Doze, Stop00, Stop01 mode Stop02 mode Stop03 mode Typical 75 VDD_OSC_A_PLL 10 6 1 mA MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 8 Freescale Semiconductor Pin assignments and reset states Table 3. Estimated power consumption specifications (continued) Characteristic Symbol External I/O pad operating supply current (nominal 3.3 V) EVDD USB operating supply current (nominal 3.3 V) VDD_USBO, VDD_USBH ADC operating supply current (nominal 3.3 V) Speed mode 00 Speed mode 01 VDDA_ADC DAC operating supply current (nominal 3.3 V) VDDA_DAC_ADC RTC standby supply current ISTBY Typical Unit —3 mA 30 mA 14 22 mA 11 mA 17 A VSTBY_RTC 1 Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. 2 DDR2 interface power is estimated from the Micron DDR2 data sheet. The numbers given in this table do not include the actual power consumption of the memory itself. The current drawn by the memory needs to be added to the values in this table and may be several hundred mA. 3 EVDD values depend on the application, with the restrictions that any single pin cannot exceed 25 mA and that the total power does not exceed the thermal characteristics. 3 Pin assignments and reset states 3.1 Signal multiplexing The following table lists all the MCF5441x pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to the following sections for package diagrams. For a more detailed discussion of the MCF5441x signals, consult the MCF5441x Reference Manual (MCF54418RM). NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., FB_AD23), while designations for multiple signals within a group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Most pins that are muxed with GPIO default to their GPIO functionality. See the following table for a list of the exceptions. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 9 Pin assignments and reset states Table 4. Special-case default signal functionality Pin Default signal FB_CLK, FB_OE, FB_R/W, FB_BE/BWE[1:0], FB_CS[5:4] FB_CLK, FB_OE, FB_R/W, FB_BE/BWE[1:0], FB_CS[5:4] FB_ALE FB_ALE or FB_TS (depending on RCON[3]) FB_BE/BWE3 Boot from NFC, NF_ALE. Otherwise, FB_BE/BWE3. FB_BE/BWE2 Boot from NFC, NF_CLE. Otherwise, FB_BE/BWE2. FB_CS1 Boot from NFC, NFC_CE. Otherwise, GPIO. FB_CS0 Boot from FlexBus, FB_CS0. Otherwise, GPIO. FB_TA Boot from NFC, NFC_R/B. Otherwise, FB_TA. ALLPST, PST[3:0], DDATA[3:0] ALLPST, PST[3:0], DDATA[3:0] NOTE While most modules and functionalities between the 196 and 256 MAPBGA package are the same, the following modules have been removed from 196 MAPBGA for pin space: UART2, UART6, UART9, PWM, SSI1, SIM1, USB HOST, IRQ6, IRQ3, IRQ2, FLEXCAN1, I2C1, ADC, DAC. Other modifications to the 196 MAPBGA package are: • • • SDRAMC — One address line, SD_A14, is removed. SDHC — Number of data lines for eSDHC have been reduced to 4 instead of 8. MAC — Only MAC0_RMII mode is implemented. Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5. MCF5441x Signal information and muxing RESET — — — U I EVDD ssr K14 K15 RSTOUT — — — — O EVDD msr P12 L16 — — 4 I EVDD ae G14 G16 Signal name GPIO Alternate 1 Alternate 2 Reset Clock EXTAL/ RMII_REF_CLK — — MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 10 Freescale Semiconductor Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5. MCF5441x Signal information and muxing (continued) XTAL — — — — O EVDD ae H14 H16 — — I EVDD msr G5,H5 K5, L5 — — I/O FBVDD fsr A10, A9, B9, C8, A9, Mode selection BOOTMOD[1:0] — — FlexBus — FB_AD[31:24]/ NFC_IO[15:8]5 — B9, C9, A8, B8, D8, A8, B8, C8, A7 FB_AD[23:16]/ NFC_IO[7:0]5 — — — — I/O FBVDD fsr D7, B7 B7, C7, C6, C7, A7, D6, B6, A6, A5, A6, B6, D5, FB_AD[15:10] — — — —6 FB_AD[9:8] — — — U7 FB_AD[7:0] — — — — I/O FBVDD fsr I/O FBVDD fsr I/O FBVDD fsr B5, A4 C6, A5 C5, A3, B4, B5, A4, A3, C4, B3, A2 D4, B4, C5 B2, C3 C4, B3 D4, B1, C2, C3, E4, D3, D3, C1, D2, E3, A2, B2, E3, D1 C2, F3 FB_ALE PA7 FB_TS — — O FBVDD fsr E2 D2 FB_OE/ NFC_RE PA6 FB_TBST/ NFC_RE — — O FBVDD fsr H1 F1 FB_R/W/ NFC_WE PA5 — — — O FBVDD fsr H2 G2 FB_TA PA4 — NFC_R/B U8 O FBVDD fsr H3 H3 FB_BE/BWE3 PA3 FB_CS3 FB_A1/ NFC_ALE9 — O FBVDD fsr F3 C1 FB_BE/BWE2 PA2 FB_CS2 FB_A0/ NFC_CLE10 — O FBVDD fsr E1 E2 FB_BE/BWE[1:0] PA[1:0] FB_TSIZ[1:0] — — O FBVDD fsr F2, F1 D1, F4 FB_CLK PB7 — — — O FBVDD fsr G1 G1 FB_CS5 PB6 DACK1 — — O FBVDD fsr — F2 FB_CS4 PB5 DREQ1 — — O FBVDD fsr — B1 FB_CS1 PB4 — NFC_CE — O FBVDD fsr G3 E1 FB_CS0 PB3 — — — O FBVDD fsr G2 G3 I2C 0 I2C0_SCL PB2 UART8_TXD CAN0_TX — I/O EVDD ssr H12 G15 I2C0_SDA PB1 UART8_RXD CAN0_RX — I/O EVDD ssr G12 G14 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 11 Pin assignments and reset states Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5. MCF5441x Signal information and muxing (continued) CAN1_TX PB0 UART9_TXD I2C1_SCL — I/O EVDD ssr — D14 CAN1_RX PC7 UART9_RXD I2C1_SDA — I/O EVDD ssr — D15 — O SDVDD st_dec — P6 Signal name GPIO Alternate 1 Alternate 2 FlexCAN 1 SDRAM controller SD_A14 — — — ap SD_A[13:0] — — — — O SDVDD st_dec P3, M1, M3, R4, R1, R3, ap L2, L1, N4, N4, P3, T4, M2, P2, L3, R2, T2, N3, L4, N1, N2, P5, P4, N5, SD_BA[2:0] — — — — O SDVDD st_dec K1, N3 P2, T3 M6, J4, P4 P7, N6, R5 K4 N8 N6 R7 ap SD_CAS — — — — O SDVDD st_dec ap SD_CKE — — — — O SDVDD st_dec ap SD_CLK — — — — O SDVDD st_ck P6 T5 SD_CLK — — — — O SDVDD st_ck P7 T6 SD_CS — — — — O SDVDD st_dec M5 N7 P11, M10, T12, R11, N10, M9, T11, R10, P10, M8, N9, T10, N8, M7 P9, R9 ap SD_D[7:0] — — — — I/O SDVDD st_odt SD_DM — — — — O SDVDD st_odt N7 T7 SD_DQS — — — — I/O SDVDD st_dqs P8 T8 SD_DQS — — — — I/O SDVDD st_dqs P9 T9 SD_ODT — — — — O SDVDD st_dec P5 P8 M4 R6 N5 R8 ap SD_RAS — — — — O SDVDD st_dec ap SD_WE — — — — O SDVDD st_dec ap SD_VREF — — — — — SDVDD st_vref N9 P10 SD_VTT — — — — — SDVDD st_vtt L8 N10 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 12 Freescale Semiconductor Pin assignments and reset states 196 MAPBGA 256 MAPBGA Alternate 2 Pad type3 Alternate 1 Voltage domain GPIO Direction2 Signal name Pullup (U)1 Pulldown (D) Table 5. MCF5441x Signal information and muxing (continued) — I EVDD ssr G10 F12 — I EVDD ssr — N1 External interrupts port IRQ7 PC6 — — 11 IRQ6 PC5 — USB_CLKIN IRQ4 PC4 DREQ0 — — I EVDD ssr E11 F14 IRQ3 PC3 DSPI0_PCS3 USBH_VBUS_EN — I EVDD ssr — M1 IRQ2 PC2 DSPI0_PCS2 USBH_VBUS_OC —12 I EVDD ssr — M2 IRQ1 PC1 — — — I EVDD ssr E13 F13 — I/O VDD_ ae B13 A14 ae A13 B14 ae — A15 ae — B15 ae — K3 ae — H2, J3, G4 ae — K4 ae — J2, J1, H1 USB On-the-Go USBO_DM — — — USB0 USBO_DP — — — — I/O VDD_ USB0 USB host USBH_DM — — — — I/O VDD_ USBH USBH_DP — — — — I/O VDD_ USBH ADC ADC_IN7/ DAC1_OUT — — — — I VDDA_ DAC_ ADC ADC_IN[6:4] — — — — I VDDA_ ADC ADC_IN3/ DAC0_OUT — — — — I VDDA_ DAC_ ADC ADC_IN[2:0] — — — — I VDDA_ ADC Real time clock RTC_EXTAL — — — — 4 I VSTBY ae B14 B16 RTC_XTAL — — — — O VSTBY ae C14 C16 — I/O EVDD msr K3 L1 DSPI0/SBF13 DSPI0_PCS1/ SBF_CS PC0 — — MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 13 Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5. MCF5441x Signal information and muxing (continued) DSPI0_PCS0/SS PD7 I2C3_SDA SDHC_DAT3 — I/O EVDD msr J1 K2 DSPI0_SCK/ SBF_CK PD6 I2C3_SCL SDHC_CLK — I/O EVDD msr J3 L2 DSPI0_SIN/ SBF_DI PD5 UART3_RXD SDHC_CMD U14 I EVDD msr K2 L3 DSPI0_SOUT/ SBF_DO PD4 UART3_TXD SDHC_DAT0 — O EVDD msr J2 K1 — I/O EVDD ssr M11 N11 One wire OW_DAT RGPIO0/PD3 DACK0 — DMA timers T3IN/PWM_EXTA3 RGPIO1/PD2 T3OUT USBO_VBUS_EN/ ULPI_DIR15 — I EVDD msr G13 G13 T2IN/PWM_EXTA2 RGPIO2/PD1 T2OUT SDHC_DAT2 — I EVDD msr J12 H14 T1IN/PWM_EXTA1 RGPIO3/PD0 T1OUT SDHC_DAT1 — I EVDD msr H13 H13 USBO_VBUS_OC/ ULPI_NXT16 —17 I EVDD msr J13 H15 T0IN/PWM_EXTA0 RGPIO4/PE7 T0OUT UART 2 UART2_CTS RGPIO14/PE6 UART6_TXD SSI1_BCLK — I EVDD msr — M4 UART2_RTS RGPIO15/PE5 UART6_RXD SSI1_FS — O EVDD msr — M3 UART2_RXD PE4 PWM_A3 SSI1_RXD — I EVDD msr — P1 — 18 I/O EVDD msr — N2 UART2_TXD PE3 PWM_B3 SSI1_TXD UART 1 UART1_CTS RGPIO7/PE2 UART5_TXD DSPI3_SCK — I EVDD msr D12 C10 UART1_RTS RGPIO8/PE1 UART5_RXD DSPI3_PCS0 — O EVDD msr D11 D10 UART1_RXD PE0 I2C5_SDA DSPI3_SIN — I EVDD msr B10 C9 — 18 I/O EVDD msr C10 D9 UART1_TXD PF7 I2C5_SCL DSPI3_SOUT UART 0 UART0_CTS RGPIO5/PF6 UART4_TXD DSPI2_SCK — I EVDD msr E12 E13 UART0_RTS RGPIO6/PF5 UART4_RXD DSPI2_PCS0 — O EVDD msr C12 B11 UART0_RXD PF4 I2C4_SDA DSPI2_SIN — I EVDD msr C11 B10 — 18 I/O EVDD msr B11 D11 UART0_TXD PF3 I2C4_SCL DSPI2_SOUT MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 14 Freescale Semiconductor Pin assignments and reset states Voltage domain Pad type3 196 MAPBGA 256 MAPBGA SDHC_DAT3 PF2 PWM_A1 DSPI1_PCS0 — I/O EVDD msr — B13 SDHC_DAT2 PF1 PWM_B1 DSPI1_PCS2 — I/O EVDD msr — E14 SDHC_DAT1 PF0 PWM_A2 DSPI1_PCS1 — I/O EVDD msr — D12 SDHC_DAT0 PG7 PWM_B2 DSPI1_SOUT — I/O EVDD msr — B12 SDHC_CMD PG6 PWM_B0 DSPI1_SIN — I/O EVDD msr — C11 SDHC_CLK PG5 PWM_A0 DSPI1_SCK — O EVDD msr — A10 Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Table 5. MCF5441x Signal information and muxing (continued) Enhanced secure digital host controller Smart card interface 0 SIM0_DATA RGPIO13/PG4 PWM_FAULT2 SDHC_DAT7 — I/O EVDD msr — E12 SIM0_VEN RGPIO12/PG3 PWM_FAULT0 — — O EVDD msr — D13 SIM0_RST RGPIO11/PG2 PWM_FORCE SDHC_DAT6 — O EVDD msr — C15 SIM0_PD RGPIO10/PG1 PWM_SYNC SDHC_DAT5 — I EVDD msr — C14 SIM0_CLK RGPIO9/PG0 PWM_FAULT1 SDHC_DAT4 — O EVDD msr — A11 Synchronous serial interface 019 SSI0_RXD PH7 I2C2_SDA SIM1_VEN — I EVDD msr B12 C12 SSI0_TXD PH6 I2C2_SCL SIM1_DATA — O EVDD msr A11 C13 SSI0_FS PH5 UART7_TXD SIM1_RST — I/O EVDD msr C13 E15 SSI0_MCLK PH4 SSI_CLKIN SIM1_CLK — O EVDD msr A12 A12 SSI0_BCLK PH3 UART7_RXD SIM1_PD — I/O EVDD msr D13 A13 Ethernet subsystem MII0_MDC PI1 RMII0_MDC20 — — O EVDD fsr N14 P16 MII0_MDIO PI0 RMII0_MDIO20 — — I/O EVDD fsr M14 N16 PJ7 RMII0_CRS_DV20 — — I EVDD fsr M13 P14 PJ[6:5] RMII0_RXD[1:0]20 — — I EVDD fsr P13, N13 R15, T15 — — I EVDD fsr M12 N14 MII0_RXDV MII0_RXD[1:0] 20 MII0_RXER PJ4 RMII0_RXER MII0_TXD[1:0] PJ[3:2] RMII0_TXD[1:0]20 — — O EVDD fsr L12, L11 R13, P13 MII0_TXEN PJ1 RMII0_TXEN20 — D21 O EVDD fsr N12 P12 MII0_COL PJ0 RMII1_MDC ULPI_STP — I EVDD fsr — R12 MII0_TXER PK7 RMII1_MDIO ULPI_DATA4 — O EVDD fsr — R14 MII0_CRS PK6 RMII1_CRS_DV ULPI_DATA5 — I EVDD fsr — P11 MII0_RXD[3:2] PK[5:4] RMII1_RXD[1:0] ULPI_DATA[1:0] — I EVDD fsr — P15, N13 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 15 Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5. MCF5441x Signal information and muxing (continued) MII0_RXCLK PK3 RMII1_RXER ULPI_DATA6 — I EVDD fsr — M14 MII0_TXD[3:2] PK[2:1] RMII1_TXD[1:0] ULPI_DATA[3:2] — O EVDD fsr — T13, N12 I EVDD fsr — T14 MII0_TXCLK PK0 RMII1_TXEN ULPI_DATA7 21 D BDM/JTAG ALLPST22 PH2 — — — O EVDD fsr K12 — DDATA[3:2] PH[1:0] — — — O EVDD fsr — L15, M13 DDATA[1:0] PI[7:6] — — — O EVDD fsr — M15, L14 PST[3:0] PI[5:2] — — — O EVDD fsr — J13, J16, J15, J14 JTAG_EN — — — D I EVDD msr N11 N15 PSTCLK — TCLK23 — — I EVDD fsr L14 M16 DSI — TDI23 — U I EVDD msr L10 L13 — TDO23 — — O EVDD msr L13 K14 BKPT — TMS23 — U I EVDD msr K13 K16 DSCLK — TRST23 — U I EVDD msr L9 K13 D I EVDD ssr K10 R16 — — — — D9, D10, E9–E11, E9, E10, F9, F9–F11 DSO Test (this signal must be grounded) TEST — — — Power supplies IVDD — — — F10, F12 EVDD — — — — — — — F4–F7, G6, H8, J7–J10, G7, H6, H7, K6–K11, L6 J5, J6 FB_VDD SD_VDD — — — — — — — — — — — — — — D5–D7, E5–E7, F5, E4–E7 F6, G5 K7–K9, M7–M12 L5–L7 VDD_OSC_A_PLL — — — — — — vddint F14 F15 VSS_OSC_A_PLL — — — — — — vddint F13 F16 VDD_USBO — — — — — — vdde F11 G12 VDD_USBH — — — — — — vdde — H12 VDDA_ADC — — — — — — — — H4 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 16 Freescale Semiconductor Pin assignments and reset states Signal name GPIO Alternate 1 Alternate 2 Pullup (U)1 Pulldown (D) Direction2 Voltage domain Pad type3 196 MAPBGA 256 MAPBGA Table 5. MCF5441x Signal information and muxing (continued) VSSA_ADC — — — — — — vssint — H5 VDDA_DAC_ADC — — — — — — vddint — J4 VSSA_DAC_ADC — — — — — — vssint — J5 VSTBY — — — — — — vddint E14 E16 VSS — — — — — — — 24 A1, A14, A1, A16, D8, D14, D16, E8, E8, F8, G4, F7, F8, G8, G9, G6–G11, G11, H4, H6, H7, H8–11, H9–H11, J7–11, J14, J6, J11, K5, K6, J12, K12, K11, P1, L4, L7–L12, P14 M5, M6, T1, T16 1 All pins available with GPIO contain a configurable pull-up/down. This column indicates the pull devices that are enabled automatically at reset. Pull-ups are generally only enabled on pins with their primary function, except as noted. 2 Refers to pin’s primary function. 3 For details on the available slew rates of the various pad types see section “Output Pad Loading and Slew Rate” of the MCF5441x Data Sheet or section “Slew Rate Control Registers (SRCR_x)” in chapter “Pin-Multiplexing and Control” of the MCF5441x Reference Manual. 4 Enabled as input only in oscillator bypass mode (internal crystal oscillator is disabled). 5 These pins are time-division multiplexed between the FlexBus and NFC. An arbitration mechanism determines which module drives these pins at any point in time. 6 An internal pulldown circuit is enabled during system reset for FB_AD[10]. 7 An internal pullup circuit is enabled when the system is in reset state. 8 Configurable pull that is enabled and pulled up after reset. 9 When configured for FB_A1, this pin is time-division multiplexed between the FlexBus and NFC. An arbitration mechanism determines which module drives the pin at any point in time. When not configured as FB_A1, NFC_ALE cannot be used. 10 When configured for FB_A0, this pin is time-division multiplexed between the FlexBus and NFC. An arbitration mechanism determines which module drives the pin at any point in time. When not configured as FB_A0, NFC_CLE cannot be used. 11 Since USB_CLKIN is a clock signal, it must be dedicated to the USB system. Do not implement this pin as dual-use. 12 When Alternate 2 is selected, then internal pullup/pulldown control will come from the MISCCR[3] register of CIM. 13 When booting from serial boot flash, the SBF function is enabled automatically. After the SBF function completes its reset sequence, the signals are returned to GPIO functionality. 14 Automatic pull-up when SBF controls the pin during reset only. Configurable pull when UART, DSPI, or SDHC control the pin. 15 If ULPI is enabled, ULPI_DIR is available as the Alternate 2 function. If ULPI is disabled, USBO_VBUS_EN is available. 16 If ULPI is enabled, ULPI_NXT is available as the Alternate 2 function. If ULPI is disabled, USBO_VBUS_OC is available. 17 When Alternate 2 is selected, then internal pullup/pulldown control will come from the MISCCR[2] register of CIM. 18 UARTx_TXD pad can act as RXD(input) pad when UART One Wire mode is enabled. 19 The SIM1 signals are available with 256 MAPBGA but are not available with 196 MAPBGA. 20 These RMII functions are selected by the mode chosen by the MAC-NET, not by the pin-multiplexing and control (GPIO) module. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 17 Pin assignments and reset states 21 Configurable pull that is enabled and pulled down after reset. The ALLPST signal is available only on the 196 MAPBGA package and allows limited debug trace functionality compared to the 256 MAPBGA package. 23 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 24 VSTBY is for optional standby lithium battery. If not used, connect to EVDD. 22 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 18 Freescale Semiconductor Pin assignments and reset states 3.2 Pinout—196 MAPBGA The pinout for the MCF54410 package is shown below. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A GND FB_ AD10 FB_ AD14 FB_ AD16 FB_ AD18 FB_ AD19 FB_ AD24 FB_ AD27 FB_ AD30 FB_ AD31 SSI0_ TXD SSI0_ MCLK USB_ DPLS GND A B FB_ AD6 FB_ AD9 FB_ AD11 FB_ AD13 FB_ AD17 FB_ AD20 FB_ AD23 FB_ AD26 FB_ AD29 U1_ RXD U0_ TXD SSI0_ RXD USB_ DMNS RTC_ EXTAL B C FB_ AD3 FB_ AD5 FB_ AD8 FB_ AD12 FB_ AD15 FB_ AD21 FB_ AD22 FB_ AD25 FB_ AD28 U1_ TXD U0_ RXD U0RTS_ B SSI0_ FS RTC_ XTAL C D FB_ AD0 FB_ AD2 FB_ AD4 FB_ AD7 FBVDD FBVDD FBVDD GND CVDD CVDD U1RTS_ U1CTS_ B B SSI0_ BCLK GND D E FB_BE2 _B FB_ALE FB_ AD1 FBVDD FBVDD FBVDD FBVDD GND CVDD CVDD IRQ4_B U0CTS_ B IRQ1_B VSTBY E F FB_BE0 _B FB_BE1 _B FB_BE3 _B EVDD EVDD EVDD EVDD GND CVDD CVDD VDD_ USBO CVDD FB_CS0 FB_CS1 _B _B GND BOOT MOD1 EVDD EVDD GND GND IRQ7_B GND I2C0_ SDA T3IN EXTAL G H FB_OE_ FB_RW_ FB_TA_ B B B GND BOOT MOD0 EVDD EVDD GND GND GND GND I2C0_ SCL T1IN XTAL H J DSPI0_ PCS0 DSPI0_ SOUT DSPI0_ SCK SD_BA1 EVDD EVDD GND GND GND GND GND T2IN T0IN GND J K SD_A1 DSPI0_ SIN DSPI0_ PCS1 SD_CAS _B GND GND SDVDD SDVDD SDVDD TEST GND ALLPST TMS L SD_A9 SD_A10 SD_A5 SD_A4 SDVDD SDVDD SDVDD SD_VTT TRST_B TDI RM110_ TXD0 RM110_ TXD1 TDO TCLK L M SD_A12 SD_A7 SD_A11 SD_RAS SD_CS_ SD_BA2 _B B SD_D0 N SD_A3 SD_A2 SD_A0 P GND SD_A6 SD_A13 1 2 3 G FB_CLK SD_A8 4 5 6 RSTIN_ K B SD_D2 SD_D4 SD_D6 OWIO RMII0_ RXER RMII0_ CRS_DV RMII0_ MDIO M SD_D1 SD_VRE F SD_D5 JTAG_E N RMII0_ TXEN RMII0_ RXD0 RMII0_ MDC N SD_DQS SD_CLK_ SD_DQS B _B SD_D3 SD_D7 RSTOUT _B RMII0_ RXD1 GND P 10 11 12 13 14 SD_WE_ SD_CKE SD_DQM B SD_BA0 SD_ODT SD_CLK VSS_OS VDD_OS C_A_PL C_A_PL F L L 7 8 9 Figure 7. MCF54410 Pinout (196 MAPBGA) MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 19 Pin assignments and reset states 3.3 Pinout—256 MAPBGA The pinout for the MCF54415, MCF54416, MCF54417, and MCF54418 packages are shown below. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A VSS FB_ AD3 FB_ AD13 FB_ AD14 FB_ AD16 FB_ AD20 FB_ AD22 FB_ AD26 FB_ AD29 SDHC_ CLK SIM0_ CLK SSI0_ MCLK SSI0_ BCLK USBO_ DM USBH_ DM VSS A B FB_ CS4 FB_ AD2 FB_ AD8 FB_ AD11 FB_ AD15 FB_ AD19 FB_ AD24 FB_ AD28 FB_ AD31 UART0_ UART0_ SDHC_ RXD DAT0 RTS SDHC_ DAT3 USBO_ DP USBH_ DP RTC_ EXTAL B C FB_BE/ BWE3 FB_ AD1 FB_ AD7 FB_ AD9 FB_ AD10 FB_ AD17 FB_ AD23 FB_ AD30 UART1_ UART1_ SDHC_ RXD CMD CTS SSI0_ TXD SIM0_ PD SIM0_ RST RTC_ XTAL C D FB_BE/ BWE1 FB_ ALE FB_ AD5 FB_ AD12 FB_ AD18 FB_ AD21 FB_ AD25 FB_ AD27 UART1_ UART1_ UART0_ SDHC_ TXD TXD DAT1 RTS SIM0_ VEN CAN1_ TX CAN1_ RX VSS D E FB_ CS1 FB_ BE/BW E2 FB_ AD4 FB_ AD6 FB_ VDD FB_ VDD FB_ VDD VSS IVDD IVDD IVDD SIM0_ XMT UART0 _CTS SDHC_ DAT2 SSI0_ FS VSTBY_ E RTC F FB_ OE FB_ CS5 FB_ AD0 FB_BE/ BWE0 FB_ VDD FB_ VDD VSS VSS IVDD IVDD IVDD IRQ7 IRQ1 IRQ4 VDD_ OSC_A _PLL VSS_ OSC_A F _PLL G FB_ CLK FB_ R/W FB_ CS0 ADC_ IN4 FB_ VDD VSS VSS VSS VSS VSS VSS VDD_ USBO T3IN I2C0_ SDA I2C0_ SCL EXTAL G H ADC_ IN0 ADC_ IN6 FB_ TA AVDD_ ADC AVSS_ ADC VSS VSS EVDD VSS VSS VSS VDD_ USBH T1IN T2IN T0IN XTAL H J ADC_ IN1 ADC_ IN2 ADC_ IN5 VDDA_ DAC_ ADC VSSA_ DAC_ ADC VSS EVDD EVDD EVDD EVDD VSS VSS PST3 PST0 PST1 PST2 J ADC_ IN7 ADC_ IN3 BOOT MOD1 EVDD EVDD EVDD EVDD EVDD EVDD VSS TRST TDO RESET TMS K VSS BOOT MOD0 EVDD VSS VSS VSS VSS VSS VSS TDI DDATA0 DDATA3 RST OUT L VSS VSS SD_ VDD SD_ VDD SD_ VDD SD_ VDD SD_ VDD SD_ VDD DDATA2 MII0_ DDATA1 RXCLK TCLK M OW_ IO MII0_ TXD2 MII0_ RXD2 MII0_ RXER JTAG_ EN MII0_ MDIO N K DSPI0_ DSPI0_ SOUT PCS0 L DSPI0_ DSPI0_ DSPI0_ PCS1 SCK SIN M IRQ3 N IRQ6 P IRQ2 UART2_ UART2_ RTS CTS SD_ CAS SD_D3 SD_VTT SD_A4 SD_A14 SD_BA2 SD_ ODT SD_D1 SD_ VREF MII0_ CRS MII0_ TXEN MII0_ TXD0 MII0_ RXDV MII0_ RXD3 MII0_ MDC P SD_ RAS SD_ CKE SD_WE SD_D0 SD_D4 SD_D6 MII0_ COL MII0_ TXD1 MII0_ TXER MII0_ RXD1 TEST R T UART2_ SD_A5 SD_A10 SD_A2 SD_BA1 SD_CS TXD UART2_ SD_A1 RXD SD_A9 SD_A3 R SD_A12 SD_A7 SD_A11 SD_A13 SD_BA0 T SSI0_ RXD VSS SD_A6 SD_A0 SD_A8 SD_ CLK SD_ CLK SD_ DM SD_ DQS SD_ DQS SD_D2 SD_D5 SD_D7 MII0_ TXD3 MII0_ TXCLK MII0_ RXD0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 8. MCF54415, MCF54416, MCF54417, and MCF54418 Pinout (256 MAPBGA) MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 20 Freescale Semiconductor Electrical characteristics 4 Electrical characteristics This document contains electrical specification tables and reference timing diagrams for the MCF5441x microprocessor. This section contains detailed information on AC/DC electrical characteristics and AC timing specifications. NOTE The specifications for this device in any other document are superseded by the specifications in this document. 4.1 Absolute maximum ratings Table 6. Absolute maximum ratings1, 2 Rating Symbol Pin name Value Units External I/O pad supply voltage EVDD EVDD –0.3 to +4.0 V Internal logic supply voltage IVDD IVDD –0.5 to +2.0 V FlexBus I/O pad supply voltage FBVDD FB_VDD –0.3 to +4.0 V SDRAM I/O pad supply voltage SDVDD SD_VDD –0.3 to +4.0 V PVDD VDD_OSC_A_PLL –0.3 to +4.0 V USB OTG supply voltage USBVDD VDD_USBO –0.3 to +4.0 V USB host supply voltage USBVDD VDD_USBH –0.3 to +4.0 V AVDD VDDA_ADC –0.3 to +4.0 V DAC and ADC supply voltage — VDDA_DAC_ADC –0.3 to +4.0 V RTC standby supply voltage RTCVSTBY VSTBY_RTC –0.3 to +4.0 V VIN — –0.3 to +3.6 V Instantaneous maximum current Single pin limit (applies to all pins) 3, 4, 5 IDD — 25 mA Operating temperature range (packaged) TA (TL – TH) — –40 to +85 C Tstg — –55 to +150 C PLL supply voltage ADC supply voltage Digital input voltage3 Storage temperature range 1 2 3 4 5 Functional operating conditions are given in Table 11. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Immunity to static and electrical fields is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., VSS or EVDD). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, and then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and EVDD . Power supply must maintain regulation within operating EVDD, FBVDD, and SDVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD, FBVDD, or SDVDD) is greater than IDD, the injection current may flow out of EVDD, FBVDD, or SDVDD and could result in external power supply going out of regulation. Ensure the external EVDD, FBVDD, or SDVDD load shunts current greater than maximum injection current. This is the greatest risk when the MPU is not consuming power (for example, no clock). MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 21 Electrical characteristics 4.2 Thermal characteristics Table 7. Thermal characteristics Symbol 196 MAPBGA 256 MAPBGA Single layer board (1s)2 JA 58 — Four layer board (2s2p)2,3 JA 35 32 Single layer board (1s) JMA 48 — Four layer board (2s2p) JMA 32 29 C/W JB 22 22 C/W JC 14 12 C/W jt 3 2 C/W Tj 105 105 oC Characteristic Junction to ambient, natural convection1 Junction to ambient (@200 ft/min)1, 3 Junction to board4 Junction to case5 Junction to top of package, natural convection 1, 6 Maximum operating junction temperature 1 Unit C/W JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 3 The average chip-junction temperature (TJ) in C can be obtained from: T J = T A +  P D   JMA  Eqn. 1 Where: TA QJMA PD PINT PI/O = = = = = Ambient Temperature, C Package Thermal Resistance, Junction-to-Ambient, C/W PINT + PI/O IDD  IVDD, Watts - Chip Internal Power Power Dissipation on Input and Output Pins — User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: K P D = -------------------------------- T J + 273C  Eqn. 2 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 22 Freescale Semiconductor Electrical characteristics Solving equations 1 and 2 for K gives: 2 K = P D   T A  273C  + Q JMA  P D Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 4.3 ESD protection Table 8. ESD protection characteristics1, 2 Characteristics ESD Target for Human Body Model 1 2 4.4 Symbol Value Units HBM 2000 V All ESD testing is in conformity with JESD22 Stress Test Qualification. A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable specification at room temperature followed by hot temperature, unless specified otherwise in the device specifications provided in this document. Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: • • A supply over voltage is applied to each power supply pin. A current injection is applied to each input, output, and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 9. Latch-up results No. 1 4.5 Symbol LU CC Parameter Conditions Class Static latch-up class TA = 125 °C conforming to JESD 78 II level A DC electrical specifications Table 10. Power supply specifications Characteristic Symbol Pin Name Min Max Units IVDD IVDD 1.14 1.32 V FlexBus supply voltage Nominal 1.8–3.3 V FBVDD FB_VDD 1.71 3.63 SDRAM supply voltage DDR2 @ 1.8 V SDVDD 1.71 1.98 SDRAM input reference voltage SDVREF SD_VREF 0.49 x SDVDD 0.51 x SDVDD V SDRAM termination supply voltage SDVTT SD_VTT SDVREF – 0.04 SDVREF + 0.04 V PLL analog operation voltage range, nominal 3.3 V PVDD VDD_OSC_ A_PLL 3.135 3.63 V Internal logic supply voltage, nominal 1.2 V V V SD_VDD MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 23 Electrical characteristics Table 10. Power supply specifications (continued) Characteristic Symbol Pin Name Min Max Units EVDD EVDD 3.135 3.63 V USBVDD VDD_USBO VDD_USBH 3.135 3.63 V ADC supply voltage AVDD VDDA_ADC 3.135 3.63 V DAC supply voltage — VDDA_DAC_ ADC 3.135 3.63 V RTCVSTBY VSTBY_RTC 1.6 EVDD – 0.2V V External I/O pad supply voltage, nominal 3.3 V USB supply voltage, nominal 3.3 V RTC standby supply voltage Table 11. I/O electrical specifications Characteristic Symbol Min Max Units CMOS input high voltage EVIH 0.65  EVDD EVDD + 0.3 V CMOS input low voltage EVIL VSS – 0.3 0.35  EVDD V CMOS output high voltage IOH = –2.0 mA EVOH 0.8  EVDD — V CMOS output low voltage IOL = 2.0 mA EVOL — 0.2  EVDD V SDRAM input high voltage DDR2 @ 1.8V SDVIH SDVREF + 0.125 SDVDD + 0.3 SDRAM input low voltage DDR2 @ 1.8V SDVIL 0.3 SDVREF  0.125 SDRAM output high voltage DDR2@ 1.8V IOH = –13.4 mA SDVOH SDVDD  0.9 — SDRAM output low voltage DDR2@ 1.8V IOH = 13.4 mA SDVOL — SDVDD  0.1 FlexBus input high voltage @ 1.8V–3.3V FBVIH 0.51  FBVDD FBVDD + 0.3 V FlexBus input low voltage @ 1.8V–3.3V FBVIL VSS – 0.3 0.42  FBVDD V FlexBus output high voltage @ 1.8V–3.3V IOH = –5.0 mA for all modes FBVOH 0.8  FBVDD — V FlexBus output low voltage @ 1.8V–3.3V IOL = 5.0 mA for all modes FBVOL — 0.2  FBVDD V Iin –2.5 2.5 A Input Leakage Current Vin = VDD or VSS, Input-only pins V V V V MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 24 Freescale Semiconductor Electrical characteristics Table 11. I/O electrical specifications (continued) Characteristic Weak internal pull-up/pull-down device current1 Selectable weak internal pull-up/pull-down device current 1 2 Min Max Units IAPU 10 315 A IAPU 25 150 A — — 7 7 Input capacitance All input-only pins All input/output (three-state) pins Cin Output loading for CMOS pads (EVDD and FBVDD domains) Low drive High drive CL Output loading for SDRAMC pads (SDVDD domain) Low drive High drive CL 1 2 4.6 Symbol pF pF 50 200 pF 5 50 Refer to the signals section for pins having weak internal pull-up devices. This parameter is characterized before qualification rather than 100% tested. Output pad loading and slew rate The output pins on the MCF5441x devices have programmable slew rates. Table 12 lists the rise/fall time for pins based on the type of pad used for the signal, the value programmed into the appropriate field of the slew rate control registers, and capacitive loading. Refer to Table 5 for a list of the external signals to pad connections. NOTE To allow the I/O interfaces to run at their maximum frequency, set their respective slew rate select values to 11. Table 12. Output pad slew rates Pad type1 Slew rate select field value ssr Drive load (pF) Rise/fall time (ns) 50 2.2 200 6 50 22 200 28 50 42 200 50 50 210 200 220 11 10 01 00 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 25 Electrical characteristics Table 12. Output pad slew rates (continued) Pad type1 Slew rate select field value Drive load (pF) Rise/fall time (ns) 50 1.2 200 6 50 9 200 14 50 17 200 23 50 110 200 120 50 1.1 200 2.6 50 2.4 200 5 50 5 200 8 50 16 200 21 msr 11 10 01 00 fsr 11 10 01 00 1 4.7 The ae pads are used for USB communication and are governed by usb.org specifications. They are not included in this table. DDR pad drive strengths The DDR pins on the MCF5441x devices have programmable drive strengths. Table 13 lists the drive strengths for pins based on the value programmed into the appropriate field of the drive strength control register. Refer to Table 5 for a list of the external signals to pad connections. NOTE For a single device drive, this setting should be 00 to enable Half Strength mode. High strength is intended for multiple device drives (DIMM). Table 13. DDR pad drive strengths Pad type Drive strength select field value Drive strength st 00 Half strength 1.8V DDR2 01 Full strength 1.8V DDR2 10 Reserved 11 Reserved MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 26 Freescale Semiconductor Electrical characteristics 4.8 Oscillator and PLL electrical characteristics Reference Figure 9 for crystal circuits. Table 14. PLL electrical characteristics Num 1 2 3 4 5 6 7 8 PLL Reference Frequency Range1 Crystal reference External reference 2 Core frequency FB_CLK frequency2 (MISCCR2[FBHALF] = 0) 3 VCO frequency 4 DCC frequency3 4, 5 Symbol Min Max Unit fref_crystal fref_ext 141 141 501 501 MHz MHz fsys fsys/2 120 60 250 100 MHz MHz fvco 240 500 MHz fDCC 300 500 MHz tcst — 10 ms 5 Crystal start-up time 6 EXTAL input high voltage External and limp modes VIHEXT EVIH EVDD V EXTAL input low voltage External and limp modes VILEXT 0 EVIL V tlpll — 50 ms 7 1 Characteristic 4, 6 8 PLL lock time 9 Duty cycle of reference 4 tdc –45% +45% % 10 Crystal capacitive load CL — From crystal spec pF 11 Feedback resistor RF 10 — M 12 Series resistor RS 0 200  13 Discrete load capacitance for XTAL CL_XTAL — 2  CL – CS_XTAL – CPCB_XTAL7 pF 14 Discrete load capacitance for EXTAL CL_EXTAL — 2  CL – CS_EXTAL – CPCB_EXTAL7 pF 15 FB_CLK period jitter, 4, 5, 7, 8, Measured at fSYS Max Peak-to-peak jitter (clock edge to clock edge) Long term jitter — — 10 0.1 % fsys/3 % fsys/3 Cjitter These reference value ranges are for after a PLL predivider (PREDIV), which can be programmed to 1, 2, 4, 8, or 16. The PREDIV value can be set while booting from serial flash. In parallel reset configuration, the PREDIV value is set to one. In this mode, if the input frequency results in an out of range reference frequency, boot the processor in limp mode, set the proper PREDIV and multiplier settings, and switch to PLL mode. All internal registers retain data at 0 Hz. Required only for DDR2 memory. This parameter is guaranteed by characterization before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This specification is the PLL lock time only and does not include oscillator start-up time. CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 27 Electrical characteristics XOSC EXTAL XTAL RF RS Crystal or Resonator CC1L CL C2 Figure 9. Typical crystal circuit 4.9 Reset timing specifications Table 15 lists specifications for the reset timing parameters shown in Figure 10. Table 15. Reset and configuration override timing Num Characteristic Min Max Unit R11 RESET valid to FB_CLK (setup) 9 — ns R2 FB_CLK to RESET invalid (hold) 1.5 — ns R3 RESET valid time2 5 — FB_CLK cycles R4 FB_CLK to RSTOUT valid — 10 ns R5 RSTOUT valid to Configuration Override inputs valid 0 — ns R6 Configuration Override inputs valid to RSTOUT invalid (setup) 20 — FB_CLK cycles R7 Configuration Override inputs invalid after RSTOUT invalid (hold) 0 — ns R8 RSTOUT invalid to Configuration Override inputs High Impedance — 1 FB_CLK cycles R9 Minimum RSTOUT pulse width 512 — FB_CLK cycles 1 RESET and configuration override data lines are synchronized internally. Setup and hold times must be met only if recognition on a particular clock is required. 2 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 28 Freescale Semiconductor Electrical characteristics FB_CLK R1 R2 R3 RESET R4 R4 R9 RSTOUT R8 R5 R6 R7 BOOTMOD[1:0] Figure 10. RESET and configuration override timing 4.10 FlexBus timing specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the FlexBus output clock (FB_CLK). All other timing relationships can be derived from these values. All FlexBus signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 16. FlexBus timing specifications Num Characteristic Min Max Unit Notes Frequency of operation — 62.5 MHz FB1 Clock period 16 — ns FB2 Output valid — 6.0 ns 1 FB3 Output hold 0.5 — ns 1 FB4 Input setup 5.5 — ns 2 FB5 Input hold 0 — ns 2 1 Specification is valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn, and FB_TSIZ[1:0]. 2 Specification is valid for all FB_AD[31:0] and FB_TA. 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 29 Electrical characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 FB_AD[Y:0] ADDR[Y:0] FB2 FB_AD[31:X] FB5 ADDR[31:X] DATA FB4 FB_R/W FB_ALE FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB4 FB5 FB_TA FB_TSIZ[1:0] TSIZ[1:0] Note: 1 FB2 and FB3 output specifications are valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn, and FB_TSIZ[1:0]. 2 FB4 and FB5 input specifications are valid for all FB_AD[31:0] and FB_TA. Figure 11. FlexBus read timing MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 30 Freescale Semiconductor Electrical characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[Y:0] FB_AD[Y:0] FB2 FB_AD[31:X] ADDR[31:X] DATA FB_R/W FB_ALE FB_TS FB_CSn, FB_BE/BWEn FB_OE FB4 FB5 FB_TA FB_TSIZ[1:0] TSIZ[1:0] Note: 1 FB2 and FB3 output specifications are valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn, and FB_TSIZ[1:0]. 2 FB4 and FB5 input specifications are valid for all FB_AD[31:0] and FB_TA. Figure 12. FlexBus write timing 4.11 NAND flash controller (NFC) timing specifications The NAND flash controller (NFC) implements the interface to standard NAND flash memory devices. This section describes the timing parameters of the NFC. All NFC signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 17. NFC timing specifications Num Characteristic Symbol Frequency of operation Min Max Unit — 401 MHz NF1 Clock period tNFC 25 — ns NF2 NFC_CLE setup time tCLS 1.5  tNFC — ns NF3 NFC_CLE hold time tCLH tNFC — ns NF4 NFC_CE setup time tCS 1.5  tNFC — ns NF5 NFC_CE hold time tCH tNFC — ns NF6 NFC_WE pulse width tWP 0.5  tNFC – 0.5 — ns 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 31 Electrical characteristics Table 17. NFC timing specifications (continued) Num 1 Characteristic Symbol Min Max Unit NF7 NFC_ALE setup time tALS 1.5  tNFC — ns NF8 NFC_ALE hold time tALH tNFC — ns NF9 Data setup time tDS 0.5  tNFC – 4 — ns NF10 Data hold time tDH 0.5  tNFC – 10 — ns NF11 Write cycle time tWC tNFC — ns NF12 NFC_WE high hold time tWH 0.5  tNFC – 1 — ns NF13 Ready to NFC_RE low tRR 4.5  tNFC — ns NF14 NFC_RE pulse width tRP 0.5  tNFC – 0.5 — ns NF15 Read cycle time tRC tNFC — ns NF16 NFC_RE high hold time tREH 0.5  tNFC – 1 — ns NF17 Data in setup time tDSU 6 — ns 50 MHz maximum frequency can only be used if the part is in EDO (enhanced data out) mode. NFC_CLE NF2 NF3 NF4 NF5 NFC_CE NF6 NFC_WE NF7 NF8 NFC_ALE NF9 NFC_IO[7:0] NF10 Command Figure 13. Command latch cycle timing MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 32 Freescale Semiconductor Electrical characteristics NFC_CLE NF2 NF4 NF5 NFC_CE NF11 NF6 NF12 NFC_WE NF7 NF8 NFC_ALE NF10 NF9 NFC_IO[7:0] Address Figure 14. Address latch cycle timing NF3 NFC_CLE NF5 NFC_CE NF11 NF6 NF12 NFC_WE NF7 NFC_ALE NF9 NFC_IO[15:0] NF10 Data to NF Figure 15. Write data latch timing MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 33 Electrical characteristics NF5 NFC_CE NF15 NF14 NF16 NFC_RE NF17 NFC_IO[15:0] NF10 Data from NF NF13 NFC_R/B Figure 16. Read data latch timing 4.12 DDR SDRAM controller timing specifications The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing numbers are relative to the DQS byte lanes. Table 18. SDRAM timing specifications Num Characteristic Symbol Min Max Unit 100 250 MHz tSDCK 4.0 10.0 ns Frequency of operation DD1 Clock period DD2 Pulse width high tSDCKH 0.45 0.55 tSDCK 1 DD3 Pulse width low tSDCKL 0.45 0.55 tSDCK 3 DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] — output valid tCMV — 0.5  tSDCK + 1 ns 2 DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] — output hold tCMH 0.5  tSDCK – 1 — ns DD6 Write command to first DQS latching transition tDQSS — WL + 0.2  tSDCK ns DD7 Data and data mask output setup (DQDQS) relative to DQS (DDR write mode) tQS 0.4 — ns DD8 Data and data mask output hold (DQSDQ) relative to DQS (DDR write mode) tQH 0.4 — ns 5 DD9 Input data skew relative to DQS (input setup) tIS — 0.5 ns 6 tIH 0.375  tSDCK — ns 7 DD10 Input data hold relative to DQS. 1 2 Notes 3 4 Pulse width high plus pulse width low cannot exceed min and max clock period. Command output valid should be 1/2 the memory bus clock (tSDCK) plus some minor adjustments for process, temperature, and voltage variations. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 34 Freescale Semiconductor Electrical characteristics 3 4 5 6 7 This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2] The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. This specification relates to the required hold time of DDR memories. SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2] Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid. DD1 DD2 SD_CLK DD3 SD_CLK DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS CMD DD6 DD4 SD_A[13:0] ROW COL DD7 SD_DM DD8 SD_DQS DD7 SD_D[7:0] WD1 WD2 WD3 WD4 DD8 Figure 17. DDR write timing MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 35 Electrical characteristics DD1 DD2 SD_CLK DD3 SD_CLK DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS CL=2 CMD DD4 SD_A[13:0] CL=2.5 ROW COL DD9 DQS Read Preamble CL = 2 SD_DQS DQS Read Postamble DD10 CL = 2.5 SD_D[7:0] RD1 RD2 RD3 RD4 DQS Read DQS Read Preamble Postamble SD_DQS SD_D[7:0] RD1 RD2 RD3 RD4 Figure 18. DDR read timing 4.13 USB transceiver timing specifications The MCF5441x device is compliant with industry standard USB 2.0 specification. 4.14 ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in Table 19. These timings apply to synchronous mode only. All timings are measured with respect to the clock as seen at the USB_CLKIN pin on the MCF5441x. The ULPI PHY is the source of the 60MHz clock. NOTE The USB controller requires a 60-MHz clock, even if using the on-chip FS/LS transceiver instead of the ULPI interface. In this case, the 60-MHz clock can be generated by the PLL or input on the USB_CLKIN pin. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 36 Freescale Semiconductor Electrical characteristics All ULPI signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 19. ULPI interface timing Num Characteristic Min Nominal Max Units USB_CLKIN operating frequency — 60 — MHz USB_CLKIN duty cycle — 50 — % U1 USB_CLKIN clock period — 16.67 — ns U2 Input setup (control and data) 5.0 — — ns U3 Input hold (control and data) 1.0 — — ns U4 Output valid (control and data) — — 9.5 ns U5 Output hold (control and data) 1.0 — — ns U1 USB_CLKIN U3 U2 ULPI_DIR / ULPI_NXT (Control Input) U2 U3 ULPI_DATA[7:0] (Data Input) U5 U4 ULPI_STP (Control Output) U4 U5 ULPI_DATA[7:0] (Data Output) Figure 19. ULPI timing diagram 4.15 eSDHC timing specifications This section describes the electrical information of the eSDHC. All eSDHC signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.2 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. 2.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 37 Electrical characteristics 4.15.1 eSDHC timing specifications Figure 20 depicts the timing of eSDHC, and Table 20 lists the eSDHC timing characteristics. Table 20. eSDHC interface timing specifications ID Parameter Symbols Min Max Unit Clock frequency (low speed) fPP1 0 400 kHz Clock frequency (SD/SDIO full speed) fPP2 0 40 MHz Clock frequency (MMC full speed) fPP3 0 20 MHz 100 400 kHz Card Input Clock SD1 4 Clock frequency (identification mode) fOD SD2 Clock low time tWL 7 — ns SD3 Clock high time tWH 7 — ns SD4 Clock rise time tTLH — 3 ns SD5 Clock fall time tTHL — 3 ns –5 5 ns eSDHC Output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 eSDHC output delay (output valid) tOD eSDHC Input / card outputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 eSDHC input setup time tISU 5 — ns SD8 eSDHC input hold time tIH 0 — ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal data transfer mode for SD/SDIO card, clock frequency can be any value from 0 to 25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value from 0 to 20 MHz. 4 In card identification mode, card clock must be 100 kHz– 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 SD2 SD5 SD1 SD4 SDHC_CLK SD3 Output from eSDHC to card SDHC_CMD SDHC_DAT[3:0] SD6 SD7 SD8 Input from card to eSDHC SDHC_CMD SDHC_DAT[3:0] Figure 20. eSDHC timing MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 38 Freescale Semiconductor Electrical characteristics 4.15.2 eSDHC electrical DC characteristics Table 21 lists the eSDHC electrical DC characteristics. Table 21. MMC/SD interface electrical specifications Num Parameter Design value Min Max Unit Condition/remark Bus signal line load 7 Pull-up resistance 47 10 100 k Internal PU 8 Open drain resistance NA NA NA k For MMC cards only Open drain signal level 9 Output high voltage 10 Output low voltage For MMC cards only V IOH = –100 µA V IOL = 2 mA V IOH = –100 µA @VDD min 0.125 x VDD V IOL = 100 µA @VDD min VDD – 0.2 0.3 Bus signal levels 11 Output high voltage 12 Output low voltage 13 Input high voltage 0.625 x VDD VDD + 3 V 14 Input low voltage VSS – 0.3 0.25 x VDD V 4.16 0.75 x VDD SIM timing specifications Each SIM card interface consist of a total of 12 pins (two separate ports of six pins each. Mostly one port with 5 pins is used). The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used by the SIM card to recover the clock from the data, like a standard UART. All six (or five when a bidirectional TXRX is used) of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between the signals in normal mode. However, there are some in reset and power down sequences. All SIM signals use pad type pad_msr. SIM timing is fairly relaxed compared to other interfaces and can be met at 50 pF loading with any slew rate setting other than 00.1 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 39 Electrical characteristics 4.16.1 General timing requirements Figure 21 shows the timing of the SIM module, and Table 22 lists the timing parameters. 1/Sfreq SIM_CLK Sfall Srise Figure 21. SIM clock timing diagram Table 22. SIM timing specification—High Drive strength Num Description Symbol Min Max Unit 1 SIM clock frequency (SIM_CLK)1 Sfreq 0.01 5 (Some new cards may reach 10) MHz 2 SIM_CLK rise time 2 Srise – 20 ns 3 SIM_CLK fall time 3 Sfall – 20 ns 4 SIM input transition time (RX, SIM_PD) Strans – 25 ns 1 50% duty cycle clock With C = 50pF 3 With C = 50pF 2 4.16.2 4.16.2.1 Reset sequence Cards with internal reset The reset sequence for this kind of SIM card is as follows (see Figure 22): • • • After powerup, the clock signal is enabled on SIM_CLK (time T0) After 200 clock cycles, RX must be high. The card must send a response on RX acknowledging the reset between 400 and 40,000 clock cycles after T0. SIM_VEN SIM_CLK Response SIM_RX 1 2 T0 400 clock cycles < 1 < 200 clock cycles 2 < 40,000 clock cycles Figure 22. Internal-reset card reset sequence MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 40 Freescale Semiconductor Electrical characteristics 4.16.2.2 Cards with active-low reset The sequence of reset for this kind of card is as follows (see Figure 23): 1. 2. 3. 4. 5. After powerup, the clock signal is enabled on SIM_CLK (time T0) After 200 clock cycles, RX must be high. SIM_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those 40,000 clock cycles) SIM_RST is set high (time T1) SIM_RST must remain high for at least 40,000 clock cycles after T1 and a response must be received on RX between 400 and 40,000 clock cycles after T1. SIM_VEN SIM_RST SIM_CLK SIM_RX Response 2 1 3 3 T0 T1 1 < 200 clock cycles 400 clock cycles < 2 < 40,000 clock cycles 400,000 clock cycles < 3 Figure 23. Active-low-reset card reset sequence 4.16.3 Power-down sequence Power down sequence for SIM interface is as follows: 1. 2. 3. 4. 5. SIM_PD port detects the removal of the SIM card SIM_RST goes low SIM_CLK goes low SIM_TX goes low SIM_VEN goes low Each of these steps is completed in one CKIL period (usually 32 kHz). Power-down may be started in response to a card-removal detection or launched by the processor. Figure 24 and Table 23 show the usual timing requirements for this sequence, with Fckil = CKIL frequency value. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 41 Electrical characteristics Table 23. Timing requirements for power-down sequence Num Description Symbol Min Max Unit 1 SIM reset to SIM clock stop Srst2clk 0.9  fCKIL 0.8 µs 2 SIM reset to SIM TX data low Srst2dat 1.8  fCKIL 1.2 µs 3 SIM reset to SIM voltage enable low Srst2ven 2.7  fCKIL 1.8 µs 4 SIM presence detect to SIM reset low Spd2rst 0.9  fCKIL 25 ns Spd2rst SIM_PD SIM_RST Srst2clk SIM_CLK Srst2dat SIM__TX Srst2ven SIM_VEN Figure 24. SmartCard interface power-down AC timing 4.17 SSI timing specifications This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync (SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below. All SSI signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF. When the SSI_MCLK output is not used, the maximum SSI bit clock (SSI_BCLK) frequency is such that timing can also be met at slew rate settings 10 and 01.1 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 42 Freescale Semiconductor Electrical characteristics Table 24. SSI timing — master modes1 Num Description Symbol Min Max Units Notes tMCLK 15.15 — ns 2 45% 55% tMCLK 80 — ns 45% 55% tBCLK S1 SSI_MCLK cycle time S2 SSI_MCLK pulse width high / low S3 SSI_BCLK cycle time S4 SSI_BCLK pulse width S5 SSI_BCLK to SSI_FS output valid — 15 ns S6 SSI_BCLK to SSI_FS output invalid 0 — ns S7 SSI_BCLK to SSI_TXD valid — 15 ns S8 SSI_BCLK to SSI_TXD invalid / high impedance 0 — ns S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 15 — ns S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns tBCLK 3 1 All timings specified with a capacitive load of 25pF. SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (fsys). 3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (f ). sys 2 Table 25. SSI timing — slave modes1 Num 1 Description Symbol Min Max Units tBCLK 80 — ns 45% 55% tBCLK S11 SSI_BCLK cycle time S12 SSI_BCLK pulse width high / low S13 SSI_FS input setup before SSI_BCLK 10 — ns S14 SSI_FS input hold after SSI_BCLK 2 — ns S15 SSI_BCLK to SSI_TXD / SSI_FS output valid — 15 ns S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high impedance 0 — ns S17 SSI_RXD setup before SSI_BCLK 15 — ns S18 SSI_RXD hold after SSI_BCLK 2 — ns Notes All timings specified with a capacitive load of 25pF. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 43 Electrical characteristics S1 S2 S2 SSI_MCLK (Output) S3 SSI_BCLK (Output) S4 S4 S5 S6 SSI_FS (Output) S9 S10 SSI_FS (Input) S7 S7 S8 S8 SSI_TXD S9 S10 SSI_RXD Figure 25. SSI timing — master modes S11 SSI_BCLK (Input) S12 S12 S15 S16 SSI_FS (Output) S13 S14 SSI_FS (Input) S15 S16 S16 S15 SSI_TXD S17 S18 SSI_RXD Figure 26. SSI timing — slave modes 4.18 12-bit ADC specifications Table 26. ADC parameters1 Characteristic Name Min Typical Max 200kHz — 12MHz tADC 8.33 — 500 ns Low reference voltage VREFL VSS — VREFH V High reference voltage VREFH VREFL — AVDD V INL — ±3 — lsb Frequency of operation ADC clock period Integral non-linearity (10% to 90% input signal range)2 Unit MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 44 Freescale Semiconductor Electrical characteristics Table 26. ADC parameters1 (continued) Characteristic Differential non-linearity (10% to 90% input signal range)3 Name Min Typical Max Unit DNL — ±0.6 — lsb Monotonicity Guaranteed Conversion time — — 6 tADC cycles Sample time — — 1 tADC cycles ADC power-up time4 tADPU — — 13 tADC cycles5 Recovery from auto standby tREC — 0 6 tADC cycles Input impedance XIN — 2k —  Input injection current6, per pin IADI — — 3 mA IVREFH — 100 — nA VOFFSET0 — ±20 — LSB Offset voltage internal reference (at the 50% FSR point) VOFFSET50 — ±12 — LSB Gain error (transfer path) EGAIN — ±0.2 — % Spurious free dynamic range SFDR — 57 — dB Signal-to-noise plus distortion SINAD — 55 — dB SNR — 60 — dB ENOB — 9 — Bits VREFH current Offset voltage internal reference (at the y intercept) Signal-to-noise ratio Effective number of bits 1 2 3 4 5 6 All ADC parameter measurements are preliminary pending full characterization. These measurements were made at VDD = 3.3 V, VREFH = 3.3 V, and VREFL = ground. INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH Includes power-up of ADC and VREF ADC clock cycles The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC 4.19 12-bit DAC timing specifications Table 27 shows electrical specifications of DAC. Table 27. DAC parameters1 Characteristic Name Min Typical Max Unit Range of digital input words: 497 to 3599 (0x1F1–0xE0F) LSB — 806 — uV Monotonicity Guaranteed Conversion time (high-speed) 1 — — us Conversion time (low-speed) 2 — — us Conversion rate (high-speed) — — 1M conv/sec Conversion rate (low-speed) — — 500K conv/sec AVSS + 0.04 — AVDD – 0.04 V Output swing MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 45 Electrical characteristics Table 27. DAC parameters1 (continued) Characteristic Name Min Typical Max Unit Integral non-linearity (497 to 3599) INL — — ±8.0 lsb Differential non-linearity (497 to 3599) DNL — — ±0.5 lsb Gain error (497 to 3599) EGAIN — ±0.26 — % Effective number of bits ENOB 9 — — bits DAC power-up time tDAPU — — 11 us Output load resistance RL 3K — — Ohm Output load capacitance CL — 400 — pF PSRR — 60 — dB Power supply ripple rejection 1 All measurements were made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground 4.20 mcPWM timing specifications Table 28. mcPWM timing Num 4.21 Characteristic Min Max Unit G1 FB_CLK high to output valid — 7 ns G2 FB_CLK high to output invalid 1 — ns G3 Input valid to FB_CLK high 3 — ns G4 FB_CLK high to input invalid 1 — ns I2C timing specifications Table 29 lists specifications for the I2C input timing parameters shown in Figure 27. Table 29. I2C input timing specifications between SCL and SDA Num Characteristic Min Max Units I1 Start condition hold time 2 — 1/fSYS I2 Clock low period 8 — 1/fSYS I3 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 ms I4 Data hold time 0 — ns I5 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 1 ms I6 Clock high time 4 — 1/fSYS I7 Data setup time 0 — ns I8 Start condition setup time (for repeated start condition only) 2 — 1/fSYS I9 Stop condition setup time 2 — 1/fSYS Table 30 lists specifications for the I2C output timing parameters shown in Figure 27. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 46 Freescale Semiconductor Electrical characteristics Table 30. I2C output timing specifications between SCL and SDA Num I1 1 I21 I3 2 Characteristic Min Max Units Start condition hold time 6 — 1/fSYS Clock low period 10 — 1/fSYS I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — — µs I41 Data hold time 7 — 1/fSYS I53 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 3 ns I61 Clock high time 10 — 1/fSYS I7 1 Data setup time 2 — 1/fSYS I8 1 Start condition setup time (for repeated start condition only) 20 — 1/fSYS I9 1 Stop condition setup time 10 — 1/fSYS 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 30. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR. However, the numbers given in Table 30 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. I5 I6 I2 I2C_SCL I1 I4 I7 I8 I3 I9 I2C_SDA Figure 27. I2C input/output timings 4.22 Ethernet assembly timing specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. All Ethernet signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 47 Electrical characteristics 4.22.1 Receive signal timing specifications The following timing specs meet the requirements for MII and RMII interfaces for a range of transceiver devices. Table 31. Receive signal timing MII mode Num — 1 RMII mode Characteristic Unit RXCLK frequency setup1 Min Max Min Max — 25 — 50 MHz 5 — 4 — ns 5 — 2 — ns E1 RXD[n:0], RXDV, RXER to RXCLK E2 RXCLK to RXD[n:0], RXDV, RXER hold1 E3 RXCLK pulse width high 35% 65% 35% 65% RXCLK period E4 RXCLK pulse width low 35% 65% 35% 65% RXCLK period In MII mode, n = 3; In RMII mode, n = 1 E4 RXCLK (MII) / EXTAL (RMII) E1 RXD[n:0] RXDV, RXER E3 E2 Valid Data Figure 28. MII/RMII receive signal timing diagram 4.22.2 Transmit signal timing specifications Table 32. Transmit signal timing MII mode Num — 1 RMII mode Characteristic Unit TXCLK frequency 1 Min Max Min Max — 25 — 50 MHz E5 TXCLK to TXD[n:0], TXEN, TXER invalid 4 — 5 — ns E6 TXCLK to TXD[n:0], TXEN, TXER valid1 — 25 — 14 ns E7 TXCLK pulse width high 35% 65% 35% 65% tTXCLK E8 TXCLK pulse width low 35% 65% 35% 65% tTXCLK In MII mode, n = 3; In RMII mode, n = 1 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 48 Freescale Semiconductor Electrical characteristics E8 TXCLK (MII) / EXTAL (RMII) E7 E6 TXD[n:0] TXEN, TXER E5 Valid Data Figure 29. MII/RMII transmit signal timing diagram 4.22.3 Asynchronous input signal timing specifications Table 33. MII/RMII transmit signal timing Num Characteristic E9 CRS, COL minimum pulse width Min Max Unit 1.5 — TXCLK period CRS, COL E9 Figure 30. MII/RMII async inputs timing diagram 4.22.4 MDIO serial management timing specifications Table 34. MDIO serial management channel signal timing Num Characteristic Symbol Min Max Unit tMDC 400 — ns E10 MDC cycle time E11 MDC pulse width 40 60 % tMDC E12 MDC to MDIO output valid — 375 ns E13 MDC to MDIO output invalid 25 — ns E14 MDIO input to MDC setup 10 — ns E15 MDIO input to MDC hold 0 — ns MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 49 Electrical characteristics E10 E11 MDC (Output) E11 E13 E12 Valid Data MDIO (Output) E14 MDIO (Input) E15 Valid Data Figure 31. MDIO serial management channel timing diagram 4.23 32-bit timer module timing specifications Table 35 lists timer module AC timings. Table 35. Timer module AC timing specifications Name 4.24 Characteristic Min Max Unit T1 DTnIN cycle time (n = 0:3) 3 — 1/fSYS/2 T2 DTnIN pulse width (n = 0:3) 1 — 1/fSYS/2 DSPI timing specifications The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. Table 36 provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the MCF54418 Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. All DSPI signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 36. DSPI module AC timing specifications1 Name Characteristic Symbol Min Max Unit Notes Master Mode — DSPI_SCK frequency fSCK — 50 MHz DS1 DSPI_SCK cycle time tSCK 20 — ns 2 DS2 DSPI_SCK duty cycle — (tsck 2) – 2.0 (tsck 2) + 2.0 ns 3 DS3 DSPI_PCSn to DSPI_SCK delay tCSC (tsck 2) – 2.0 — ns 4 DS4 DSPI_SCK to DSPI_PCSn delay tASC (tsck 2) – 3.0 — ns 5 DS5 DSPI_SCK to DSPI_SOUT valid — — 5 ns 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 50 Freescale Semiconductor Electrical characteristics Table 36. DSPI module AC timing specifications1 (continued) Name Characteristic Symbol Min Max Unit DS6 DSPI_SCK to DSPI_SOUT invalid — –5 — ns DS7 DSPI_SIN to DSPI_SCK input setup — 6 — ns DS8 DSPI_SCK to DSPI_SIN input hold — 0 — ns Notes Slave Mode 1 2 3 4 5 — DSPI_SCK frequency fSCK — fSYS  8 MHz DS9 DSPI_SCK cycle time tSCK 8 fSYS — ns DS10 DSPI_SCK duty cycle — (tsck 2) – 2.0 (tsck 2) + 2.0 ns DS11 DSPI_SCK to DSPI_SOUT valid — — 12 ns DS12 DSPI_SCK to DSPI_SOUT invalid — 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup — 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold — 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — — 10 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — — 10 ns Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges. When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR]. This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR], DCTARn[CPHA], and DCTARn[PBR]. The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK]. The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC]. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 51 Electrical characteristics DS3 DS4 DSPI_PCSn DS1 DS2 DSPI_SCK (DCTARn[CPOL] = 0) DS2 DSPI_SCK (DCTARn[CPOL] = 1) DS7 DS8 DSPI_SIN First Data Data DS5 DSPI_SOUT Last Data DS6 First Data Data Last Data Figure 32. DSPI Classic SPI timing — master Mode DSPI_SS DS9 DSPI_SCK (DCTARn[CPOL] = 0) DS10 DS10 DSPI_SCK (DCTARn[CPOL] = 1) DS15 DSPI_SOUT DS12 First Data DS13 DSPI_SIN DS11 Data Last Data Data Last Data DS16 DS14 First Data Figure 33. DSPI Classic SPI timing — slave mode MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 52 Freescale Semiconductor Electrical characteristics 4.25 SBF timing specifications The Serial boot facility (SBF) provides a means to read configuration information and system boot code from a broad array of SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 37 provides the AC timing specifications for the SBF. All SBF signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 37. SBF AC timing specifications Name 1 Characteristic Symbol Min Max Unit — SBF_CK frequency fSBFCK — 62.5 MHz SB1 SBF_CK cycle time tSBFCK 16.67 — ns SB2 SBF_CK high/low time — 30% — tSBFCK SB3 SBF_CS to SBF_CK delay — tSBFCK – 2.0 — ns SB4 SBF_CK to SBF_CS delay — tSBFCK – 2.0 — ns SB5 SBF_CK to SBF_DO valid — — 5 ns SB6 SBF_CK to SBF_DO invalid — –5 — ns SB7 SBF_DI to SBF_SCK input setup — 10 — ns SB8 SBF_CK to SBF_DI input hold — 0 — ns Notes 1 At reset, the SBF_CK cycle time is tREF  60. The first byte of data read from the serial memory contains a divider value that is used to set the SBF_CK cycle time for the duration of the serial boot process. SBF_CS SB3 SB2 SBF_CK SB7 SBF_DI SB1 SB4 SB2 SB8 First Data Data Last Data SB6 SB5 SBF_DO First Data Data Last Data Figure 34. SBF timing 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 53 Electrical characteristics 4.26 1-Wire timing specifications Specifications for the 1-Wire interface are provided by Maxim Integrated Products, Inc. Please refer to data sheet information for the appropriate device at www.maxim-ic.com. 4.27 General purpose I/O timing specifications Table 38. GPIO timing1 Num 1 Characteristic Min Max Unit G1 FB_CLK high to GPIO output valid — 9 ns G2 FB_CLK high to GPIO output invalid 1 — ns G3 GPIO input valid to FB_CLK high 9 — ns G4 FB_CLK high to GPIO input invalid 1.5 — ns These general purpose specifications apply to the following signals: IRQn, all UART signals, all timer signals, FlexCAN signals, DACKn and DREQn, and all signals configured as GPIO. FB_CLK G1 G2 GPIO Outputs G3 G4 GPIO Inputs Figure 35. GPIO timing 4.28 Rapid general purpose I/O timing specifications RGPIO signals use a mix of pad types: pad_fsr, pad_msr, and pad_ssr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF. Table 39. RGPIO timing Num Characteristic Min Max Unit RG1 PST_CLK high to RGPIO output valid — 6 ns RG2 PST_CLK high to RGPIO output Invalid 0.5 — ns RG3 RGPIO input valid to PST_CLK high 6 — ns RG4 PST_CLK high to RGPIO input invalid 1.5 — ns MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 54 Freescale Semiconductor Electrical characteristics PST_CLK RG1 RG2 RGPIO Outputs RG3 RG4 RGPIO Inputs Figure 36. RGPIO timing 4.29 JTAG and boundary scan timing specifications All JTAG signals use pad type pad_msr except for TCLK which use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 40. JTAG and boundary scan timing Characteristics1 Num 1 Min Max Unit J1 TCLK frequency of operation DC 25 MHz J2 TCLK cycle period 40 — ns J3 TCLK clock pulse width 20 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 4 — ns J6 Boundary scan input data hold time after TCLK rise 20 — ns J7 TCLK low to boundary scan output data valid — 13 ns J8 TCLK low to boundary scan output high-Z — 13 ns J9 TMS, TDI input data setup time to TCLK rise 4 — ns J10 TMS, TDI input data hold time after TCLK rise 10 — ns J11 TCLK low to TDO data valid — 12 ns J12 TCLK low to TDO high-Z — 0 ns J13 TRST assert time 32 — ns J14 TRST setup time (negation) to TCLK high 8 — ns JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it. 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 55 Electrical characteristics J2 J3 J3 VIH TCLK (input) VIL J4 J4 Figure 37. Test clock input timing TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 38. Boundary scan (JTAG) timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 39. Test access port timing TCLK J14 TRST J13 Figure 40. TRST timing MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 56 Freescale Semiconductor Electrical characteristics 4.30 Debug AC timing specifications Table 41 lists specifications for the debug AC timing parameters shown in Figure 41 and Table 42. All debug signals use pad type pad_msr except for PSTCLK which use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50 pF.1 Table 41. Debug AC timing specification Num Min Max Units D0 PSTCLK cycle time 0.5 0.5 1/fSYS D1 PSTCLK rising to PSTDDATA valid — 3.0 ns D2 PSTCLK rising to PSTDDATA invalid 0.5 — ns D3 DSI-to-DSCLK setup 1 — PSTCLK 1 DSCLK-to-DSO hold 4 — PSTCLK D5 DSCLK cycle time 5 — PSTCLK D6 BKPT assertion time 1 — PSTCLK D4 1 Characteristic DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK. D0 PSTCLK D2 D1 PSTDDATA[7:0] Figure 41. Real-time trace AC timing D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 42. BDM serial port AC timing 1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase edge rise and fall times, thus reducing EMI. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 57 Package information 5 Package information The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire. Table 42 lists the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest package outline drawings. Table 42. Package information Device Package type Case outline numbers MCF54410 196 MAPBGA 98ASA00321D 256 MAPBGA 98ARH98219A MCF54415 MCF54416 MCF54417 MCF54418 6 Product documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 58 Freescale Semiconductor Revision history 7 Revision history Table 43 summarizes revisions to this document. Table 43. Revision history Rev. No. 2 Date Summary of changes 10 Jun 2009 In Section 2.2, “Supply voltage sequencing” added the following note: NOTE All I/O VDD pins must be powered on when the device is functioning, except when in standby mode. In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can be switched off. Added Section 3.2, “Pinout—169 MAPBGA” and Section 3.3, “Pinout—256 MAPBGA” and updated Table 5 with pin locations. In Section 4.1, “Absolute maximum ratings”: • Added USB OTG, USB host, ADC, DAC/ADC, and RTC standby supply voltages In Section 4.5, “DC electrical specifications”: • Added RTC standby supply voltage • Split out Power Supplies and I/O Characteristics to two separate tables In Section 4.10, “FlexBus timing specifications”: • Changed maximum frequency to 100MHz and updated specs throughout the table • Changed FB2 maximum from 5 to 6 • Added notes to Figure 11 and Figure 12 In Section 4.12, “DDR SDRAM controller timing specifications”: • Changed minimum frequency from 50 to 100 • Changed maximum DD1 from 20 to 10 • Changed DD5 from 2 to 0.5 x tSDCK – 1 • Changed DD6 from 1.2 x tSDCK to WL + 0.2 x tSDCK • Changed DD7 from 1.5 to 0.7 • Changed DD8 from 1.0 to 0.7 • Changed DD9 from 1.0 to 0.5 • Changed DD10 from 0.25 x tSDCK + 0.5 to 0.375 x tSDCK In Section 4.17, “SSI timing specifications”: • Changed S7, S9, S15, and S17 from 10 to 15 In Section 4.22.2, “Transmit signal timing specifications”: • Changed E5 for MII from 5 to 4 In Section 4.20, “mcPWM timing specifications”: • Changed G2 from 2 to 1 In Section 4.24, “DSPI timing specifications”: • Changed DS3 from (2 x 1/fsys) – 2.0 to (tsck ³ 2) – 2.0 • Changed DS4 from (2 x 1/fsys) – 3.0 to (tsck ³ 2) – 3.0 • Changed DS7 from 7 to 6 • Changed DS11 from 4 to 12 In Section 4.25, “SBF timing specifications”: • Changed SB5 maximum from 5 to 3 • Changed SB6 minimum from –5 to 5 In Section 4.26, “1-Wire timing specifications”: • Added link to 1-wire specs In Section 4.27, “General purpose I/O timing specifications”: • Changed G2 from 1.5 to 1 In Section 4.28, “Rapid general purpose I/O timing specifications”: • Changed RG1 from 3 to 6 • Changed RG2 from 1.5 to 0.5 • Changed RG3 from 3 to 6 In Section 4.29, “JTAG and boundary scan timing specifications”: • Changed J9-12 and J14 from TBD In Section 4.30, “Debug AC timing specifications”: • Changed D2 from 1.5 to 0.5 MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor 59 Revision history Table 43. Revision history (continued) Rev. No. Date Summary of changes 3 31 July 2009 Changed 169MAPBGA package to 196MAPBGA throughout. MCF54410 device now supports a single SSI module and one Ethernet controller with IEEE 1588 support 4 17 Aug 2009 Updated MCF5441x Signal Information and Muxing table with 196MAPBGA pin locations Changed SD_Dn pin locations on 256 MAPBGA package Added note to Section 4.6, “Output pad loading and slew rate” 5 29 Jan 2010 Added orderable part numbers 6 7 8 Swapped locations of RTC_EXTAL and RTC_XTAL pins in Table 5, Figure 7, and Figure 8 Corrected instances of MCF5445x to MCF5441x Added thermal characteristic s to Table 7 Added case outline numbers to Table 42 Changed PLL supply voltage from “–0.5 to +2.0” to “–0.3 to +4.0” in Table 6 Miscellaneous corrections based on information from shared review comments by team members October 2011 • • • • • June 2012 Updated the pinouts in Table 5, “MCF5441x Signal information and muxing”. Updated the Figure 7, “MCF54410 Pinout (196 MAPBGA)”. Removed the symbol ADC_IN7/DAC1_OUT from Table 9, “Latch-up results”. Updated Table 11, “I/O electrical specifications”. Updated Table 13, “DDR pad drive strengths”. • In Table 7, added the thermal characteristics for the 196 MAPBGA package. • In Table 42, updated the case outline number for the 196 MAPBGA package from “98ARH98217” to “98ASA00321D”. MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8 60 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MCF54418 Rev. 8 06/2012 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2011-2012. All rights reserved.
MCF54415CMJ250 价格&库存

很抱歉,暂时无法提供与“MCF54415CMJ250”相匹配的价格&库存,您可以联系我们找货

免费人工找货