MCIMX6V2CVM08AB

NXP Semiconductors Data Sheet: Technical Data Document Number: IMX6SLLIEC Rev. 1, 01/2019 MCIMX6V2CVM08AB i.MX 6SLL Applications Processors for Industrial Products Package Information Plastic Package 14 x 14 mm, 0.65 mm pitch BGA Ordering Information See Table 1 on page 2 1 Introduction The i.MX 6SLL processor represents NXP’s latest achievement in integrated multimedia applications processors, which are part of a growing family of multimedia-focused products that offer high performance processing and are optimized for lowest power consumption. The processor features NXP’s advanced implementation of a single Arm® Cortex®-A9, which operates at speeds up to 800 MHz. The processor provides a 32-bit DDR interface that supports LPDDR2 and LPDDR3. In addition, there are a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, displays, and camera sensors. The i.MX 6SLL processor is specifically useful for applications, such as: • Color and monochrome eReaders • Barcode scanners • Connectivity • IoT devices NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. © 2017-2019 NXP Semiconductors All rights reserved. 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1. Special Signal Considerations . . . . . . . . . . . . . . . 11 3.2. Recommended Connections for Unused Analog Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 15 4.2. Power Supplies Requirements and Restrictions . 23 4.3. Integrated LDO Voltage Regulator Parameters . . 24 4.4. PLL’s Electrical Characteristics . . . . . . . . . . . . . . 25 4.5. On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . 26 4.6. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31 4.8. Output Buffer Impedance Parameters . . . . . . . . . 34 4.9. System Modules Timing . . . . . . . . . . . . . . . . . . . . 37 4.10. External Peripheral Interface Parameters . . . . . . 40 5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . 66 5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . . 66 5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . . 67 6. Package Information and Contact Assignments . . . . . . 68 6.1. 14 x 14 mm Package Information . . . . . . . . . . . . . 68 7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Introduction The i.MX 6SLL processor features: • Applications processor—The i.MX 6SLL incorporates a 1 GHz Cortex A9 with the NEON SIMD engine and a floating point engine that is optimized for low power consumption and includes hardware that allows dynamic voltage and frequency scaling (DVFS). This optimizes the voltage to the processor as the frequency changes with the demands of the application. • Multilevel memory system—The multilevel memory system for the processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processor supports many types of external memory devices, including LPDDR2, LPDDR3, and eMMC. • Powerful graphics acceleration—The processor has a 2D graphics processor called the pixel processor (PXP) that can support CSC, dithering, rotation, resize, and overlay. • Interface flexibility—The processor supports connections to a variety of interfaces: high-speed USB on-the-go with PHY, high-speed USB host PHY, multiple expansion card ports (high-speed MMC/SDIO host and other), and a variety of other popular interfaces (such as UART, I2C, and I2S). • Electronic Paper Display Controller—The processor integrates EPD controller that supports E-INK color and monochrome with up to 2332 x 1650 resolution and 5-bit grayscale. • Advanced security—The processor delivers hardware-enabled security features that enable secure information encryption, secure boot, and secure software downloads. The security features are discussed in the i.MX 6SLL Security Reference Manual (IMX6SLLSRM). Contact your local NXP representative for more information. • GPIO with interrupt capabilities—The GPIO pad design supports configurable dual voltage rails at 1.8 V and 3.3 V supplies. The pad is configurable to interface at either voltage level. 1.1 Ordering Information Table 1 shows the orderable part numbers covered by this data sheet. Table 1. Example Orderable Part Numbers Part Number Feature MCIMX6V2CVM08AB Features supports: • 800 MHz, industrial grade for general purpose • Basic security • With LCD/CSI • PXP • No EPDC • eMMC 5.0/SD 3.0 x3 • USB OTG x2 • UART x5 • SSI x3 • Timer x3 • PWM x4 • I2C x4 • SPI x4 Temperature (Tj) Package -40 to +105 C 14x14 mm, 0.65 mm pitch BGA i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 2 NXP Semiconductors Introduction Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be identified (for example, Cores, Frequency, Temperature Grade, Fuse options, Silicon revision). • The i.MX 6SLL Applications Processors for Industrial Products Data Sheet (IMX6SLLIEC) covers parts listed with a “C (Industrial temp)” Ensure to have the right data sheet for specific part by checking the Temperature Grade (Junction) field and matching it to the right data sheet. If there are any questions, visit the web page NXP.com/imx6series or contact a NXP representative. MC IMX6 X @ + VV $$ % A MC Silicon Rev A Prototype Samples PC Rev 1.0 A Mass Production MC Rev 1.1 B Special SC Qualification Level Part # series X i.MX 6SLL V Part differentiator @ With EPDC 7 Reserved for GPU option in the future 6 Fusing % Reserved A Arm Cortex-A9 Frequency $$ 1 GHz 10 800 MHz 08 Package Type 5 RoHS 13 x 13 0.5 mm BGA VN 14 x 14 0.65 mm BGA VM 4 Security 3 General Purpose 2 (Full Feature) 2 General Purpose 1 (Reduced Feature) 1 Baseline, consumer 0 Junction Temperature (Tj) + Consumer: 0 to + 95 °C D Industrial: -40 to +105 °C C Figure 1. Part Number Nomenclature—i.MX 6SLL 1.2 Features The i.MX 6SLL processor is based on Arm Cortex-A9 processor, which has the following features: • Arm Cortex-A9 MPCore CPU processor (with TrustZone) • The core configuration is symmetric, where each core includes: — 32 KByte L1 Instruction Cache — 32 KByte L1 Data Cache — Private Timer and Watchdog — Cortex-A9 NEON MPE (Media Processing Engine) co-processor i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 NXP Semiconductors 3 Introduction The Arm Cortex-A9 includes: • General Interrupt Controller (GIC) with 128 interrupt support • Global Timer • 256 KB unified I/D L2 cache • Two Master AXI (64-bit) bus interfaces output of L2 cache • Frequency of the core (including NEON and L1 cache) as per Table 9, "Operating Ranges," on page 19 • NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64-bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating point execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components: — Boot ROM, including HAB (96 KB) — Internal multimedia / shared, fast access RAM (OCRAM, 128 KB) • External memory interfaces: — 32-bit LPDDR2/LPDDR3 Each i.MX 6SLL processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): • Display: — EPDC, color, and monochrome E-INK, up to 2332x1650 resolution and 5-bit grayscale — 24-bit parallel LCD • Expansion cards: — Three MMC/SD/SDIO card ports all supporting: – SD 3.0 support – eMMC 5.0 support in HS400 mode • USB: — Two High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY • Miscellaneous IPs and interfaces: — SSI block—capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2S mode — Five UARTs, up to 5.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs supports 8-wire, while others four supports 4-wire. This is due to the SoC IOMUX limitation, since all UART IPs are identical. i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 4 NXP Semiconductors Introduction — — — — — — — — Four eCSPI (Enhanced CSPI) Three I2C, supporting 400 kbps Four Pulse Width Modulators (PWM) System JTAG Controller (SJC) GPIO with interrupt capabilities Sony Philips Digital Interface (SPDIF), Rx and Tx Two Watchdog timers (WDOG) Audio MUX (AUDMUX) The i.MX 6SLL processor integrates power management unit and controllers: • • • • • • Provide PMU, including LDO supplies, for on-chip resources Use Temperature Sensor for monitoring the die temperature Support DVFS techniques for low power modes Use Software State Retention and Power Gating for Arm and NEON Support various levels of system power modes Use flexible clock gating control scheme The i.MX 6SLL processor uses dedicated hardware accelerators to meet needs of E-INK Displays. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.MX 6SLL processor incorporates the following hardware accelerators: • PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to support the EPD display applications. Security functions are enabled and accelerated by the following hardware: • Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.) • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features. • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock. • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements. The actual feature set depends on the part numbers as described in Table 1, "Example Orderable Part Numbers," on page 2. Functions, such as 2D hardware graphics acceleration or E-Ink may not be enabled for specific part numbers. i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 NXP Semiconductors 5 Architectural Overview 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 6SLL processor system. 2.1 Block Diagram Figure 2 shows the functional modules in the i.MX 6SLL processor system. System Control Connectivity CPU Platform Secure JTAG PLL, OSC RTC and Reset eMMC 5.0 / SD 3.0 x3 ARM Cortex-A9 32 KB I-cache USB2 OTG with PHY x2 32 KB D-cache UART x5 Smart DMA ETM NEON I2C x3 IOMUX 256 KB L2-cache Timer x3 Multimedia SPI x4 GPIO PWM x4 E-INK™ Display Controller S/PDIF Tx/Rx Watch Dog x2 PXP CSC/Rotation/Resize/Overlay I2S/SSI x3 16-bit Parallel CSI 8 x 8 Keypad 24-bit Parallel LCD Security Power Management LDO Temp Monitor eFuse Internal Memory External Memory Secure RTC 96 KB ROM 32-bit DRAM Controller 400 MHz LPDDR2/LPDDR3 128 KB RAM HAB Figure 2. i.MX 6SLL System Block Diagram NOTE The numbers in brackets indicate number of module instances. For example, PWM (x4) indicates four separate PWM peripherals. i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 6 NXP Semiconductors Modules List 3 Modules List The i.MX 6SLL processor contains a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Table 2. i.MX 6SLL Modules List Block Mnemonic Block Name Subsystem Brief Description Fuse Box Electrical Fuse Array Security Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security Keys, and many other system parameters. Arm Arm Platform Arm AUDMUX Digital Audio Mux Multimedia Peripherals CCM GPC SRC Clock Control Module, General Power Controller, System Reset Controller CSI Parallel CSI Multimedia Peripherals The CSI IP provides parallel CSI standard camera interface port. The CSI parallel data ports are up to 24 bits. It is designed to support 24-bit RGB888/YUV444, CCIR656 video interface, 8-bit YCbCr, YUV or RGB, and 8-bit/10-bit/16-bit Bayer data input. CSU Central Security Unit Security The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX 6SLL platform. The Security Control Registers (SCR) of the CSU are set during boot time by the HAB and are locked to prevent further writing. CTI-1 CTI-2 Cross Trigger Interfaces Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from masters attached to CTIs. The CTI module is internal to the Cortex-A9 Core Platform. CTM Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs. The CTM module is internal to the Cortex-A9 Core Platform. DAP Debug Access Port System Control Peripherals The DAP provides real-time access for the debugger without halting the core to: • System memory and peripheral registers • All debug configuration registers The DAP also provides debugger access to JTAG scan chains. The DAP module is internal to the Cortex-A9 Core Platform. DCP Data co-processor Security This module provides support for general encryption and hashing functions typically used for security functions. Because its basic job is moving data from memory to memory, it also incorporates a memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the DMA-based approach. The Arm Cortex-A9 platform consists of a Cortex-A9 core and associated sub-blocks, including level 2 cache controller, GIC (General Interrupt Controller), private timers, watchdog, and CoreSight debug modules. The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnect device for voice, audio, and synchronous data routing between Synchronous Serial Interface Controller (SSI) and audio/voice codec’s (also known as coder-decoders) peripheral serial interfaces. These modules are responsible for clock and reset distribution in the system, Clocks, Resets, and and also for the system power management. Power Control i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 NXP Semiconductors 7 Modules List Table 2. i.MX 6SLL Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description eCSPI-1 eCSPI-2 eCSPI-3 eCSPI-4 Configurable SPI Connectivity Peripherals Full-duplex enhanced Synchronous Serial Interface. It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. EPDC Electrophoretic Display Controller Peripherals The EPDC is a feature-rich, low power, and high-performance direct-drive, active matrix EPD controller. It is specifically designed to drive E-INK™ EPD panels, supporting a wide variety of TFT backplanes. EPIT-1 EPIT-2 Enhanced Periodic Interrupt Timer Timer Peripherals Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPIO-5 GPIO-6 General Purpose I/O Modules System Control Peripherals Used for general purpose input/output to external ICs. GPIO module (1 - 5) supports 32 bits of I/O and GPIO6 supports 5 bits of I/O. GPT General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget” mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. I2C-1 I2C-2 I2C-3 I2C Interface Connectivity Peripherals I2C provide serial interface for external devices. Data rates of up to 400 kbps are supported. IOMUXC IOMUX Control System Control Peripherals This module enables flexible IO multiplexing. Each IO pad has default and several alternate functions. The alternate functions are software configurable. LCDIF LCD interface Connectivity peripherals The LCDIF is a general purpose display controller used to drive a wide range of display devices varying in size and capability. The LCDIF is designed to support dumb (synchronous 24-bit Parallel RGB interface) and smart (asynchronous parallel MPU interface) LCD devices. MMDC Multi-Mode DDR Controller Connectivity Peripherals DDR Controller has the following features: • Support 32-bit LPDDR2/LPDDR3 • Supports up to 2 GByte DDR memory space i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 8 NXP Semiconductors Modules List Table 2. i.MX 6SLL Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description OCOTP_ CTRL OTP Controller Security The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals, requiring permanent non-volatility. OCRAM On-Chip Memory Controller Data Path The On-Chip Memory controller (OCRAM) module is designed as an interface between system’s AXI bus and internal (on-chip) SRAM memory module. In i.MX 6SLL processor, the OCRAM is used for controlling the 128 KB multimedia RAM through a 64-bit AXI bus. OCRAM_L 2 On-Chip Memory Controller for L2 Cache Data Path The On-Chip Memory controller for L2 cache (OCRAM_L2) module is designed as an interface between system’s AXI bus and internal (on-chip) L2 cache memory module during boot mode. OSC 32 kHz OSC 32 kHz Clocking PMU PowerManagement functions Data Path Integrated power management unit. Used to provide power to various SoC domains. PWM-1 PWM-2 PWM-3 PWM-4 Pulse Width Modulation Connectivity Peripherals The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound. PXP PiXel Processing Pipeline Display Peripherals A high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma-mapping, and rotation. The PXP is enhanced with features specifically for gray scale applications. In addition, the PXP supports traditional pixel/frame processing paths for still-image and video processing applications, allowing it to interface with either of the integrated EPD controllers. RAM 128 KB Internal RAM Internal Memory Internal RAM, which is accessed through OCRAM memory controller. RNGB Random Number Generator Security Random number generating module. ROM 96KB Boot ROM Internal Memory Supports secure and regular Boot Modes. Includes read protection on 4K region for content protection. ROMCP ROM Controller with Patch Data Path ROM Controller with ROM Patch support SDMA Smart Direct Memory Access System Control Peripherals The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off-loading the various cores in dynamic data routing. Generates 32.768 kHz clock from external crystal. i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 NXP Semiconductors 9 Modules List Table 2. i.MX 6SLL Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description SJC System JTAG Controller System Control Peripherals The SJC provides JTAG interface, which complies with JTAG TAP standards, to internal logic. The i.MX 6SLL processor uses JTAG port for production, testing, and system debugging. In addition, the SJC provides BSR (Boundary Scan Register) standard support, which complies with IEEE1149.1 and IEEE1149.6 standards. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The i.MX 6SLL SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. SNVS Secure Non-Volatile Storage Security SPDIF Sony Phillips Digital Interface Multimedia Peripherals A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. Has Transmitter and Receiver functionality. SSI-1 SSI-2 SSI-3 I2S/SSI/AC97 Interface Connectivity Peripherals The SSI is a full-duplex synchronous interface, which is used on the AP to provide connectivity with off-chip audio peripherals. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock / frame sync options. TEMPMON Temperature Monitor System Control Peripherals The temperature monitor/sensor IP, for detecting high temperature conditions. The Temperature sensor IP for detecting die temperature. The temperature read out does not reflect case or ambient temperature, but the proximity of the temperature sensor location on the die. Temperature distribution may not be uniformly distributed, therefore the read out value may not be the reflection of the temperature value of the entire die. TZASC Trust-Zone Address Space Controller Security The TZASC (TZC-380 by Arm) provides security address region control functions required for intended application. It is used on the path to the DRAM controller. UART-1 UART-2 UART-3 UART-4 UART-5 UART Interface Connectivity Peripherals Each of the UARTv2 modules support the following serial data transmit/receive protocols and configurations: • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) • Programmable baud rates up to 5 Mbps. • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud • IrDA 1.0 support (up to SIR speed of 115200 bps) • Only one can operate as 8-pins full UART, DCE, or DTE USBO2 2x USB 2.0 High Speed OTG Connectivity Peripherals USBO2 contains: • Two high-speed OTG module with integrated HS USB PHY Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 10 NXP Semiconductors Modules List Table 2. i.MX 6SLL Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description uSDHC-1 uSDHC-2 uSDHC-3 SD/MMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller Connectivity Peripherals i.MX 6SLL specific SoC characteristics: All three MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. They are: • Fully compliant with MMC command/response sets and Physical Layer as defined in the Multimedia Card System Specification, v5.0 including high-capacity (size > 2 GB) cards HC MMC. • Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDHC cards up to 32 GB and SDXC cards up to 2 TB. • Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v1.10. • Conforms to the SD Host Controller Standard Specification version 3.0. WDOG-1 Watchdog Timer Peripherals The Watchdog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. WDOG-2 (TZ) Watchdog (TrustZone) Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. Such situation is undesirable as it can compromise the system’s security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. If it is still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode Software. XTALOSC Crystal Oscillator I/F Clocking 3.1 The XTALOSC module enables connectivity to external crystal oscillator device. In a typical application use-case, it is used for 24 MHz oscillator. Special Signal Considerations Table 3 lists special signal considerations for the i.MX 6SLL processor. The signal names are listed in alphabetical order. The package contact assignments can be found in Section 6, Package Information and Contact Assignments.” Signal descriptions are provided in the i.MX 6SLL Reference Manual. i.MX 6SLL Applications Processors for Industrial Products, Rev. 1, 01/2019 NXP Semiconductors 11 Modules List Table 3. Special Signal Considerations Signal Name Remarks CLK1_P/ CLK1_N One general purpose differential high speed clock Input/output is provided. It could be used to: • To feed external reference clock to the PLLs and further to the modules inside SoC, for example as alternate reference clock for Audio interfaces, etc. • To output internal SoC clock to be used outside the SoC as either reference clock or as a functional clock for peripherals. See the i.MX 6SLL Reference Manual for details on the respective clock trees. The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard. The corresponding CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing. Termination should be provided in case of high frequency signals. See LVDS pad electrical specification for further details. After initialization, the CLK1 input/output could be disabled (if not used). If unused, the CLK1_N/P pair may remain unconnected. DRAM_VREF When using DRAM_VREF with DDR I/O, the nominal reference voltage must be half of the NVCC_DRAM supply. The user must tie DRAM_VREF to a precision external resistor divider. Use a 1 k 0.5% resistor to GND and a 1 k 0.5% resistor to NVCC_DRAM. Shunt each resistor with a closely-mounted 0.1 µF capacitor. To reduce supply current, a pair of 1.5 k 0.1% resistors can be used. Using resistors with recommended tolerances ensures the ± 2% DRAM_VREF tolerance (per the DDR3 specification) is maintained when four DDR3 ICs plus the i.MX 6SLL are drawing current on the resistor divider. It is recommended to use regulated power supply for “big” memory configurations (more that eight devices). JTAG_nnnn The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However, if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed. For example, do not use an external pull down on an input that has on-chip pull-up. JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and should be avoided. JTAG_MODE must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MODE set to high configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MODE set to low configures the JTAG interface for common Software debug adding all the system TAPs to the chain. NC These signals are No Connect (NC) and should be disconnected by the user. ONOFF In normal mode may be connected to ONOFF button (de-bouncing provided at this input). Internally this pad is pulled up. A short duration (100 M). This will debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V. If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin must remain unconnected or driven with a complimentary signal. The logic level of this forcing clock should not exceed VDD_SNVS_CAP level and the frequency should be