Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MKMxxZxxCxx5
Rev. 7, 01/2014
MKMxxZxxCxx5
KM Family
Supports the following:
MKM14Z64CHH5, MKM14Z128CHH5,
MKM33Z64CLH5, MKM33Z128CLH5,
MKM33Z64CLL5, MKM33Z128CLL5,
MKM34Z128CLL5
Features
• Operating Characteristics
– Voltage range: 1.71 V to 3.6 V (when Analog Front
End (AFE) is not used)
– Voltage range: 2.7 V to 3.6 V (when Analog Front
End (AFE) is used)
– iRTC battery supply voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40°C to 85°C
• Performance
– Up to 50 MHz ARM Cortex-M0+ core delivering
0.95 Dhrystone MIPS per MHz
• Memories and memory interfaces
– 128/64 KB program flash memory. There is no
FlexMemory on these devices
– 16 KB of single access RAM
• Clocks
– 1 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 4-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Robust watchdog monitor
– Low-leakage wakeup unit
– Asynchronous wakeup unit
– Peripheral Crossbar (allows internal signals to be
connected to other on-chip modules)
• Security and integrity modules
– Hardware programmable CRC module to support
fast cyclic redundancy checks
– Hardware random-number generator
– 128-bit unique identification (ID) number per chip
• Human-machine interface
– Segment LCD controller supporting up to 36
frontplanes and 8 backplanes or 40 frontplanes and 4
backplanes
– General-purpose input/output which can acts as
Rapid GPIO (single cycle access)
• Analog modules
– 16-bit SAR ADC
– 24-bit Analog Front End comprising of 24-bit Sigma
Delta ADCs (after averaging)
– Programmable Gain Amplifier (PGA with gains
upto 32)
– Two analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– 1.2V Voltage reference
• Timers
– 4 channel Quad Timer with 16-bit counters
– Periodic interrupt timers
– 16-bit low-power timer
– Independent Real Time Clock with calendaring and
compensation
• Communication interfaces
– One SPI module with FIFO support (supports 5V
AMR operation)
– One SPI module without FIFO (no AMR operation)
– Two I2C modules with SMBus support
– Two UART modules with ISO7816 support and
Two UART without ISO 7816 support
– Any one SCI can be used for IrDA operation. 5V
AMR support on one SCI.
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2011–2014 Freescale Semiconductor, Inc.
KM Family Data Sheet, Rev. 7, 01/2014.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................4
5.3 Switching specifications.....................................................18
1.1 Determining valid order-able parts....................................4
5.3.1
Device clock specifications...................................18
2 Part identification......................................................................4
5.3.2
General switching specifications...........................18
2.1 Description.........................................................................4
5.4 Thermal specifications.......................................................19
2.2 Format...............................................................................4
5.4.1
Thermal operating requirements...........................19
2.3 Fields.................................................................................4
5.4.2
Thermal attributes.................................................19
2.4 Example............................................................................5
6 Peripheral operating requirements and behaviors....................20
3 Terminology and guidelines......................................................5
6.1 Core modules....................................................................21
3.1 Definition: Operating requirement......................................5
6.1.1
Single Wire Debug (SWD)....................................21
3.2 Definition: Operating behavior...........................................6
6.1.2
Analog Front End (AFE)........................................21
3.3 Definition: Attribute............................................................6
6.2 Clock modules...................................................................22
3.4 Definition: Rating...............................................................7
6.2.1
MCG specifications...............................................22
3.5 Result of exceeding a rating..............................................7
6.2.2
Oscillator electrical specifications.........................24
3.6 Relationship between ratings and operating
6.2.3
32 kHz oscillator electrical characteristics.............27
requirements......................................................................7
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................8
6.3 Memories and memory interfaces.....................................28
6.3.1
Flash electrical specifications................................28
6.4 Analog...............................................................................29
3.9 Typical value conditions....................................................9
6.4.1
ADC electrical specifications.................................29
4 Ratings......................................................................................10
6.4.2
CMP and 6-bit DAC electrical specifications.........33
4.1 Thermal handling ratings...................................................10
6.4.3
Voltage reference electrical specifications............35
4.2 Moisture handling ratings..................................................10
6.4.4
AFE electrical specifications.................................36
4.3 ESD handling ratings.........................................................10
6.5 Timers................................................................................40
4.4 Voltage and current operating ratings...............................11
6.6 Communication interfaces.................................................40
5 General.....................................................................................11
6.6.1
I2C switching specifications..................................40
5.1 AC electrical characteristics..............................................11
6.6.2
UART switching specifications..............................40
5.2 Nonswitching electrical specifications...............................11
6.6.3
SPI switching specifications..................................40
5.2.1
Voltage and current operating requirements.........11
6.7 Human-Machine Interfaces (HMI).....................................43
5.2.2
LVD and POR operating requirements.................12
5.2.3
Voltage and current operating behaviors..............13
7 Dimensions...............................................................................44
5.2.4
Power mode transition operating behaviors..........14
7.1 Obtaining package dimensions.........................................45
5.2.5
Power consumption operating behaviors..............15
8 Pinout........................................................................................45
5.2.6
EMC radiated emissions operating behaviors.......17
8.1 KM Signal multiplexing and pin assignments....................45
5.2.7
Designing with radiated emissions in mind...........17
8.2 KM Family Pinouts.............................................................48
5.2.8
Capacitance attributes..........................................18
9 Revision History........................................................................51
6.7.1
LCD electrical characteristics................................43
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid order-able parts
Valid order-able part numbers are provided on the web. To determine the order-able part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers:
• MKM13Z64CHH5
• MKM14Z64CHH5
• MKM14Z128CHH5
• MKM32Z64CLH5
• MKM33Z64CLH5
• MKM33Z128CLH5
• MKM32Z64CLL5
• MKM33Z64CLL5
• MKM33Z128CLL5
• MKM34Z128CLL5
• MKM38Z128CLL5
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K M S R FFF T PP CC N
KM Family Data Sheet, Rev. 7, 01/2014.
4
Freescale Semiconductor, Inc.
Terminology and guidelines
2.3 Fields
Following table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Pre-qualification (Proto)
K
Main family
• K = Kinetis
M
Sub family
• M1 = Metering only (No LCD support)
• M3 = Metering with LCD support
S
Number of Sigma Delta (SD) ADC
•
•
•
•
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
FFF
Program flash memory size
• 64 = 64 KB
• 128 = 128 KB
T
Temperature range (°C)
• C = –40 to 85
PP
Package identifier
• HH = 44 LGA (5 mm x 5 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LL = 100 LQFP (14 mm x 14 mm)
CC
Maximum CPU frequency (MHz)
• 5 = 50 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2 = 1 SD ADC with PGA and 1 SD ADC
3 = 2 SD ADC with PGA and 1 SD ADC
4 = 2 SD ADC with PGA and 2 SD ADC
8 = Same as '4'.
2.4 Example
This is an example part number:
• MKM34Z128CLL5
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
KM Family Data Sheet, Rev. 7, 01/2014.
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
e
Op
ing
rat
r
(
ng
ati
in.
t (m
)
n.
mi
rat
e
Op
ing
)
t (m
e
ir
qu
re
n
me
ing
rat
e
Op
ax
.)
e
ir
qu
re
n
me
ing
rat
e
Op
ng
ati
ax
(m
.)
r
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
g
lin
nd
Ha
in
rat
n.)
mi
g(
nd
Ha
g
lin
ing
rat
ax
(m
.)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
KM Family Data Sheet, Rev. 7, 01/2014.
8
Freescale Semiconductor, Inc.
Terminology and guidelines
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
9
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Min.
Max.
Unit
Notes
Electrostatic discharge voltage, human body model (All
pins except RESET pin)
-4000
+4000
V
1
Electrostatic discharge voltage, human body model
(RESET pin only)
-2500
+2500
V
1
VCDM
Electrostatic discharge voltage, charged-device model
(for corner pins)
-750
+750
V
2
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
3
VPESD
Powered ESD voltage
-6000
+6000
V
Latch-up current at ambient temperature of 105°C
-100
+100
mA
VHBM
ILAT
Description
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
KM Family Data Sheet, Rev. 7, 01/2014.
10
Freescale Semiconductor, Inc.
General
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.6
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
Tamper input voltage
–0.3
VBAT + 0.3
V
Analog1,
–0.3
VDD + 0.3
V
–25
25
mA
VDD – 0.3
VDD + 0.3
V
–0.3
3.6
V
VDTamper
VAIO
ID
RESET, EXTAL, and XTAL input voltage
Instantaneous maximum current single pin limit (applies to all
port pins)
VDDA
Analog supply voltage
VBAT
RTC battery supply voltage
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
5.2 Nonswitching electrical specifications
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
11
General
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Supply voltage when AFE is operational
2.7
3.6
V
Supply voltage when AFE is NOT operational
1.71
3.6
V
Analog supply voltage
2.7
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
• VIN < VSS-0.3V (Negative current injection)
-3
—
• VIN > VDD+0.3V (Positive current injection)
—
+3
-25
—
—
+25
VPOR_VBAT
—
VDD
VDDA
VBAT
VIH
VIL
RTC battery supply voltage
Input low voltage
Input hysteresis
IICDIO
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
IICcont
Analog2, EXTAL, and XTAL pin DC injection current —
single pin
mA
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
VRFVBAT
1
Input high voltage
VHYS
IICAIO
Notes
VBAT voltage required to retain the VBAT register file
mA
V
1. VBAT always needs to be there for the chip to be operational.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Notes
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
12
Freescale Semiconductor, Inc.
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = 20 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = 10 mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = 5 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = 2.5 mA
VDD – 0.5
—
V
—
100
mA
Notes
Output high voltage — high-drive strength
Output high voltage — low-drive strength
IOHT
Output high current total for all ports
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
13
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
VOL
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
0.5
V
Notes
Output low voltage — high-drive strength
Output low voltage — low-drive strength
IOLT
Output low current total for all ports
—
100
mA
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
30
60
kΩ
1,
RPD
Internal pulldown resistors
30
60
kΩ
2
1. Measured at Vinput = VSS
2. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
•
CPU and system clocks = 50 MHz
Bus clock = 25 MHz
Flash clock = 25 MHz
Temp: -40 °C, 25 °C, and 85 °C
VDD: 1.71 V, 3.3 V, and 3.6 V
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
Unit
Notes
After a POR event, amount of time from the point VDD
reaches 1.71 V to execute the first instruction across
the operating temperature range of the chip.
563
659
μs
1
—
372
μs
—
372
μs
—
273
μs
—
273
μs
—
5.0
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• VLPS → RUN
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
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Freescale Semiconductor, Inc.
General
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
• STOP → RUN
Min.
Max.
Unit
—
5.0
μs
Notes
1. Normal boot (FTFA_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
2
• @ 3.0 V
• 25 °C
• -40 °C
• 105 °C
IDD_RUN
—
6.17
7.1
mA
—
6.39
6.7
mA
—
6.93
8.3
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
2
• @ 3.0 V
• 25 °C
• -40 °C
• 105 °C
IDD_WAIT
IDD_WAIT
IDD_VLPR
IDD_VLPR
Wait mode high frequency current at 3.0 V— all
peripheral clocks disabled and Flash is not in
low-power
• 25 °C
• -40 °C
• 105 °C
Wait mode high frequency current at 3.0 V— all
peripheral clocks disabled and Flash disabled
(put in low-power)
• 25 °C
• -40 °C
• 105 °C
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
• 25 °C
• -40 °C
• 105 °C
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
• 25 °C
• -40 °C
• 105 °C
—
8.24
10.4
mA
—
8.26
9.8
mA
—
9.00
11.5
mA
2
—
3.95
4.65
mA
—
4.4
mA
—
6
mA
2, 3
—
3.81
4.4
mA
—
4.2
mA
—
5.8
mA
4
—
248.8
500
μA
—
245.30
470
μA
—
535.40
1800
μA
5
—
343.4
530
μA
—
336.62
500
μA
—
626.18
2000
μA
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
15
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VLPW
Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
• 25 °C
• -40 °C
• 105 °C
IDD_STOP
IDD_VLPS
IDD_VLLS3
IDD_VLLS2
IDD_VLLS1
IDD_VLLS0
IDD_VLLS0
IDD_VBAT
Min.
Stop mode current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
Very-low-power stop mode current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
Very low-leakage stop mode 3 current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
Very low-leakage stop mode 2 current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
Very low-leakage stop mode 1 current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• 25 °C
• -40 °C
• 105 °C
Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• 25 °C
• -40 °C
• 105 °C
Average current with RTC and 32 kHz disabled
at 3.0 V and VDD is OFF
• 25 °C
• -40 °C
• 105 °C
Typ.
Max.
Unit
Notes
6
—
162
350
μA
—
158.50
330
μA
—
446.94
1700
μA
—
311.90
730
μA
—
364
700
μA
—
645.13
2250
μA
—
8.56
46
μA
—
44
μA
—
1500
μA
3.5
μA
—
3.3
μA
—
85
μA
2.6
μA
—
2.5
μA
—
59.5
μA
1.7
μA
—
1.6
μA
—
38.8
μA
0.67
μA
—
0.64
μA
—
38
μA
0.76
μA
—
0.72
μA
—
38.4
μA
1
μA
—
0.95
μA
—
15
μA
—
—
—
—
—
—
1.98
1.24
0.89
0.35
0.472
0.3
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
16
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_VBAT
Average current when VDD is OFF and LFSR
and Tamper clocks set to 2 Hz.
• @ 3.0 V
• 25 °C
• -40 °C
• 105 °C
Typ.
Max.
Unit
Notes
8, 9
—
1.3 7
3
μA
2.5
μA
16
μA
1. See AFE specification for IDDA.
2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FBE mode. All peripheral
clocks disabled.
3. Should be reduced by 500 μA.
4. 2 MHz core, system, bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing while (1) loop from flash.
5. 2 MHz core, system and bus clock, and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled
but peripherals are not in active operation. Code executing while (1) loop from flash.
6. 2 MHz core, system and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
No flash accesses; some activity on DMA & RAM assumed.
7. Current consumption will vary with number of CPU accesses done and is dependent on the frequency of the accesses and
frequency of bus clock. Number of CPU accesses should be optimized to get optimal current value.
8. Includes 32 kHz oscillator current and RTC operation.
9. An external power switch for VBAT should be present on board to have better battery life and keep VBAT pin powered in
all conditions. There is no internal power switch in RTC.
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
14
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
16
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
12
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
5
dBμV
IEC level
0.15–1000
M
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 50 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
17
General
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
Input capacitance: fast digital pins
—
9
pF
CIN_D_io60
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
50
MHz
fBUS
Bus clock
25
MHz
Flash clock
25
MHz
6.5
MHz
fFLASH
fAFE
AFE Modulator clock
VLPR
mode1
fSYS
System and core clock
2
MHz
fBUS
Bus clock
1
MHz
1
MHz
1.6
MHz
fFLASH
fAFE
Flash clock
AFE Modulator
clock2
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
2. AFE working in low-power mode.
KM Family Data Sheet, Rev. 7, 01/2014.
18
Freescale Semiconductor, Inc.
General
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Asynchronous path
16
—
ns
2
External reset pulse width (digital glitch filter disabled)
100
—
ns
2
Port rise and fall time—Low (All pins) and high drive
(only PTC2) strength
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7 V
3
—
8
ns
—
5
ns
—
27
ns
—
16
ns
• 2.7 ≤ VDD ≤ 3.6 V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. Only PTC2 has high drive capability and load is 75 pF, other pins load (low drive) is 25 pF.
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
105
°C
TA
Ambient temperature
–40
85
°C
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
5.4.2 Thermal attributes
Board type
Symbol
Description
44 LGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
63
resistance,
junction to
ambient (natural
convection)
95
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal
50
resistance,
junction to
ambient (natural
convection)
50
°C/W
1
Single-layer
(1s)
RθJMA
Thermal
53
resistance,
junction to
ambient (200 ft./
min. air speed)
79
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal
44
resistance,
junction to
ambient (200 ft./
min. air speed)
45
°C/W
1
—
RθJB
Thermal
resistance,
junction to
board
36
35
°C/W
2
—
RθJC
Thermal
resistance,
junction to case
18
28
°C/W
3
—
ΨJT
Thermal
3
characterization
parameter,
junction to
package top
outside center
(natural
convection)
4
°C/W
4
1.
2.
3.
4.
100 LQFP
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
KM Family Data Sheet, Rev. 7, 01/2014.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Single Wire Debug (SWD)
Table 12. SWD switching characteristics at 2.7 V (2.7-3.6 V)
Symbol
Description
Value
Unit
Notes
SWD CLK
Frequency of SWD
operation
20
MHz
1
Inputs, tSUI
Data setup time
5
ns
1
inputs,tHI
Data hold time
0
ns
1
after clock edge, tDVO
Data valid Time
32
ns
1
tHO
Data Valid Hold
0
ns
1
1. Input transition assumed =1 ns. Output transition assumed = 50 pf.
Table 13. Switching characteristics at 1.7 V (1.7-3.6 V)
Symbol
Description
Value
Unit
SWD CLK
Frequency of SWD
operation
18
MHz
Inputs, tSUI
Data setup time
4.7
ns
inputs,tHI
Data hold time
0
ns
after clock edge, tDVO
Data valid Time
49.4
ns
tHO
Data Valid Hold
0
ns
Notes
2
1. Frequency of SWD clock (18 Mhz) is applicable only in case the input setup time of the device outside is not more than
6.15 ns, else the frequency of SWD clock would need to be lowered.
6.1.2 Analog Front End (AFE)
AFE switching characteristics at (2.7 V-3.6 V)
Case1: Clock is coming In and Data is also coming In (XBAR ports timed with respect to
the XBAR ports timed with respect to AFE clock defined at pad ptb[7] and pte[3])
Table 14. AFE switching characteristics (2.7 V-3.6 V)
Symbol
Description
Value
Unit
Notes
AFE CLK
Frequency of operation 10
MHz
1
Inputs, tSUI
Data setup time
5
ns
1
inputs,tHI
Data hold time
0
ns
1
1. Input Transition: 1ns. Output Load: 50 pf.
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to
generated clock defined at the XBAR out ports)
Table 15. AFE switching characteristics (2.7V-3.6V)
Symbol
Description
Value
Unit
AFE CLK
Frequency of operation 6.2
MHz
Inputs, tSUI
Data setup time
36
ns
inputs,tHI
Data hold time
0
ns
Notes
AFE switching characteristics at (1.7 V-3.6 V)
Case1: Clock is coming In and Data is also coming In ( XBAR ports timed with respect
to AFE clock defined at pad ptb[7] and pte[3])
Table 16. AFE switching characteristics (1.7 V-3.6 V)
Symbol
Description
Value
Unit
AFE CLK
Frequency of operation 10
MHz
Inputs, tSUI
Data setup time
5.1
ns
inputs,tHI
Data hold time
0
ns
Notes
Case 2: Clock is going Out and Data is coming In ( XBAR ports timed with respect to
generated clock defined at XBAR out ports)
Table 17. AFE switching characteristics (1.7 V-3.6 V)
Symbol
Description
Value
Unit
AFE CLK
Frequency of operation 6.2
MHz
Inputs, tSUI
Data setup time
54
ns
inputs,tHI
Data hold time
0
ns
Notes
6.2 Clock modules
6.2.1 MCG specifications
Table 18. MCG specifications
Symbol
fints_ft
Description
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
Notes
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol
Δfints_t
fints_t
Description
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
Internal reference frequency (slow clock) — user
trimmed
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
Min.
Typ.
Max.
Unit
Notes
—
±4
± 15
%
31.25
—
33.4234
kHz
—
± 0.3
± 0.6
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
Δfintf_t
Total deviation of internal reference frequency
(fast clock) over voltage and temperature
—
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
fintf_t
4
MHz
± 10
± 15
%
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
20
20.97
22
MHz
40
41.94
45
MHz
60
62.91
67
MHz
80
83.89
90
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
FLL period jitter
—
70
140
ps
7
FLL target frequency acquisition time
—
—
1
ms
8
FLL
fdco
DCO output
frequency range
Low-range (DRS=00)
2, 3
640 × fints_t
Mid-range (DRS=01)
1280 × fints_t
Mid-high range (DRS=10)
1920 × fints_t
High-range (DRS=11)
2560 × fints_t
fdco_t_DMX32 DCO output
frequency
Low-range (DRS=00)
4, 5, 6
732 × fints_t
Mid-range (DRS=01)
1464 × fints_t
Mid-high range (DRS=10)
2197 × fints_t
High-range (DRS=11)
2929 × fints_t
Jcyc_fll
tfll_acquire
PLL
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol
Description
fvco
VCO operating frequency
Ipll
PLL operating current
• IO 3.3 V current
• Max core voltage current
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Min.
Typ.
Max.
Unit
11.71875
12.288
14.648437
5
MHz
—
300
—
µA
31.25
32.768
39.0625
kHz
Notes
9
100
10
• fvco = 12 MHz
700
ps
± 2.98
%
Dlock
Lock entry frequency tolerance
± 1.49
—
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
150 × 10-6
+ 1075(1/
fpll_ref)
s
11
12
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. Chip max freq is 50 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be
configured.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. Chip max freq is 50 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be
configured.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
11. Will be updated later
12. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.2.2 Oscillator electrical specifications
6.2.2.1
Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
Notes
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol
Description
IDDOSC
Supply current — low-power mode (HGO=0)
IDDOSC
Min.
Typ.
Max.
Unit
Notes
1
• 32 kHz
—
500
—
nA
• 1 MHz
—
200
—
μA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 1 MHz
—
300
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
—
—
Capacitance of EXTAL
247
• Die level (100 LQFP)
• Package level (100 LQFP)
Capacitance of XTAL
pF
—
265
• Die level (100 LQFP)
• Package level (100 LQFP)
RF
0.495
ff
—
0.495
ff
pF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
2, 4
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol
RS
Description
Min.
Typ.
Max.
Unit
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
6.6
—
kΩ
—
3.3
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
Series resistor — high-frequency, high-gain
mode (HGO=1)
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
5
Vpp
1.
2.
3.
4.
5.
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
6.2.2.2
Symbol
Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
1
—
8
MHz
Notes
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 20. Oscillator frequency specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.2.3 32 kHz oscillator electrical characteristics
6.2.3.1
32 kHz oscillator DC electrical specifications
Table 21. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
VBAT
Supply voltage
Typ.
Max.
Unit
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.2.3.2
Symbol
fosc_lo
32 kHz oscillator frequency specifications
Table 22. 32 kHz oscillator frequency specifications
Description
Oscillator crystal
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
Notes
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 22. 32 kHz oscillator frequency specifications (continued)
Symbol
tstart
Description
Crystal start-up time
vec_extal32 Externally provided input clock amplitude
Min.
Typ.
Max.
Unit
Notes
—
1000
—
ms
1
700
—
VBAT
mV
2,3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3 Memories and memory interfaces
6.3.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.3.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm4
Notes
Longword Program high-voltage time
—
7.5
18
μs
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
52
452
ms
1
1. Maximum time based on expectations at cycling end-of-life.
6.3.1.2
Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
Table continues on the next page...
KM Family Data Sheet, Rev. 7, 01/2014.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
tpgm4
Program Longword execution time
—
65
145
μs
tersscr
Erase Flash Sector execution time
—
14
114
ms
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
trdonce
Read Once execution time
—
—
25
μs
Program Once execution time
—
65
—
μs
tersall
Erase All Blocks execution time
—
88
650
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
2
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.3.1.3
Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
6.3.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 26. NVM reliability specifications
Description
Typ.1
Max.
Unit
50
—
years
20
100
—
years
10 K
50 K
—
cycles
Min.
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k
Data retention after up to 1 K cycles
nnvmcycp
Cycling endurance
5
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
6.4 Analog
6.4.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
KM Family Data Sheet, Rev. 7, 01/2014.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
6.4.1.1
16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input capacitance
• 16-bit mode
—
8
10
pF
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
RADIN
RAS
Input series
resistance
Notes
kΩ
Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 12-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 12-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
KM Family Data Sheet, Rev. 7, 01/2014.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 2. ADC input impedance equivalency diagram
6.4.1.2
16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
•
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