NXP Semiconductors
Data Sheet: Technical Data
KM35P144M75SF0
Rev. 2, March 2020
Kinetis KM35 Sub-Family Data
Sheet
Enabling high accuracy, secure 1-, 2- and 3-phase electricity
metering solutions through a powerful analog front end (AFE),
auto-compensated iRTC with hardware tamper detection,
segment LCD controller, rich security protection and multiple low
power features in a 32-bit Arm® Cortex®-M0+ MCU. This product
offers:
• Enabling single-chip 1-, 2- and 3-phase metering designs
• AFE, Security and HMI. Single crystal implementation
• Single point of calibration during manufacture
• Highest accuracy metrology with regional feature support
• Multiple ƩΔ ADCs with PGA
• Supports neutral disconnect use case
• Compliance with WELMEC/OIML recommendations
• Memory and peripheral protection
• Hardware tamper detect with time stamping
• Low-power RTC, battery backup with tamper memory
Core
• Arm® Cortex®-M0+ core up to 75 MHz
• Metering specific Memory Mapped Arithmetic Unit
(MMAU)
Clocks
• 75 MHz high-accuracy internal reference clock
• 32 kHz, and 4 MHz internal reference clock
• 1 kHz LPO clock
• 32.768 kHz crystal oscillator in iRTC power domain
• 1 MHz to 32 MHz crystal oscillator
• FLL and PLL
System peripherals
• Memory Protection Unit (MPU)
• 4-channel DMA controller
• Watchdog and EWM
• Low-leakage Wakeup Unit (LLWU)
• SWD debug interface and Micro Trace Buffer (MTB)
• Bit Manipulation Engine (BME)
• Inter-peripheral Crossbar Switch (XBAR)
MKM35Z256VLL7
MKM35Z256VLQ7
MKM35Z512VLL7
MKM35Z512VLQ7
100 LQFP
144 LQFP
14 mm × 14 mm Pitch 20 mm × 20 mm Pitch
0.5 mm
0.5 mm
Memories
• Up to 512 KB program flash memory
• Up to 64 KB SRAM
Operating Characteristics
• Voltage range: 1.71 to 3.6 V (without AFE)
• Voltage range: 2.7 to 3.6 V (with AFE)
• Temperature range (ambient): –40 to 105 °C
Low power features
• 13 power modes to provide power optimization
based on application requirements
• 8.82 mA @ 75 MHz run current
• Less than 220 μA very low power run current
• 6.05 μA very low power stop current
• Down to 261 nA deep sleep current
• VBAT domain current < 1 μA with iRTC operational
• Low-power boot with less than 2.33 mA peak
current
Communication interfaces
• 16-bit SPI modules
Analog Modules
• Low-power UART module
• 4 AFE channels (4× 24-bit ƩΔ ADCs with PGA)
• UART module complying with ISO7816-3
• 16-channel 16-bit SAR ADC with 4 result registers
• Basic UART module
• High-speed analog comparator containing a 6-bit DAC
• I2C with SMBus
and programmable reference input
• Internal 1.2 V reference voltage 10–15 ppm/℃
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Timers
• Quad Timer (QTMR)
• Periodic Interrupt Timer (PIT)
• Low Power Timer (LPTMR)
• Programmable Delay Block (PDB)
• Independent Real Time Clock (iRTC)
Security and integrity modules
• Memory Mapped Cryptographic Acceleration Unit
(MMCAU) for AES encryption
• Random Number Generator (RNGA), complying
with NIST: SP800-90
• Programmable Cyclic Redundancy Check (PCRC)
• 80-bit unique identification number per chip
Human-machine interface
• Up to 4×60 (8×56, 6×58) segment LCD controller
operating in all low-power modes
• General purpose input/output (GPIO)
The following figure shows the functional modules in the chip.
Accessed by Micro Transfer Buffer (MTB) for trace
TCU
Serial
Wire
Debug
MMAU MMCAU
Serial
Wire
Debug
SRAM
(64 KB)
S1
MTB
(part of PPB)
MPU
M0
Flash
Controller
S0
Interrupt
from
Modules
IOPORT
(part of PPB)
NVIC
Port P0
Arm
M0+ Core
®
Multiple
DMA
Requests
from
Modules
Cortex®
S2
DMA
MUX
4-ch
DMA
Single Ended
Channels
SAR
ADC
Comparator
Inputs
BME
Port P1
AIPS
(AHB to IPS)
eGPIO
(dual port)
GPIO
Pins
M2
IPS Bus
AHB
Crossbar
Switch
CMP
x3
AFE
Modulator
Clock
MCG
Flash
(512 KB)
PLL
Digital
I/Os
PIT
x2
XBAR
PDB
PCRC
RNGA
I2C
x2
SIM
SMC
QTMR
WDOG
EWM
SLCD
VREF
Dec
Filter
x4
UART
x4,
LPUART
Digital
I/Os
SPI
x3
Digital
I/Os
CLK
GEN
LLWU
PMC
LPTMR
x2
OSC
MHz
OSC
32k
RTC
POR
IRTC
LCD
Pins
Modules in
VDDA Domain
XTAL32
Core, System and
Flash Clocks
XTAL
Refer Clocking
Chapter for more
detailed diagram
on MCG
FLL
EXTAL
IRC
32 kHz
EXTAL32
IRC
4 MHz
Modules in
VBAT Domain
SD ADC x4
+ PGA x4
TAMPER SD ADC Channels
Analog Front End
x4
Fine Compensation Clock
Modules in
VDD Domain
Figure 1. Functional block diagram
2
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Ordering Information
Part Number 1
Memory
ADC
Channels
Maximum
number of
GPIOs
Security
SLCD
Package
Type
Packaging
Type
Flash
(KB)
SRAM
(KB)
MKM35Z256VLL
7
256
64
12
72
CRC, MMCAU,
RNG
Yes
LQFP 100
Tray
MKM35Z256VLQ
7
256
64
16
99
CRC, MMCAU,
RNG
Yes
LQFP 144
Tray
MKM35Z256VLL
7R
256
64
12
72
CRC, MMCAU,
RNG
Yes
LQFP 100
Reel
MKM35Z256VLQ
7R
256
64
16
99
CRC, MMCAU,
RNG
Yes
LQFP 144
Reel
MKM35Z512VLL
7
512
64
12
72
CRC, MMCAU,
RNG
Yes
LQFP 100
Tray
MKM35Z512VLQ
7
512
64
16
99
CRC, MMCAU,
RNG
Yes
LQFP 144
Tray
MKM35Z512VLL
7R
512
64
12
72
CRC, MMCAU,
RNG
Yes
LQFP 100
Reel
MKM35Z512VLQ
7R
512
64
16
99
CRC, MMCAU,
RNG
Yes
LQFP 144
Reel
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KM3xPB 1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KM35P144M75SF0RM
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document:
KM35P144M75SF0
Chip Errata
The chip mask set Errata provides additional or corrective information
for a particular device mask set.
KINETIS_M_P90A
Package
Drawing
Package dimensions are provided in package drawings.
100-LQFP: 98ASS23308W 1
144-LQFP: 98ASS23177W 1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 6
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 Designing with radiated emissions in mind..........12
2.2.7 Capacitance attributes.........................................12
2.3 Switching specifications...................................................12
2.3.1 Device clock specifications..................................12
2.3.2 General switching specifications......................... 13
2.4 Thermal specifications..................................................... 14
2.4.1 Thermal operating requirements......................... 14
2.4.2 Thermal attributes................................................14
3 Peripheral operating requirements and behaviors.................. 14
3.1 Core modules.................................................................. 14
3.1.1 Single Wire Debug (SWD)...................................14
3.1.2 Analog Front End (AFE)...................................... 15
3.2 Clock modules................................................................. 16
3.2.1 MCG specifications..............................................16
3.2.2 Oscillator electrical specifications........................18
3.2.3 32 kHz oscillator electrical characteristics........... 21
3.3 Memories and memory interfaces................................... 23
3.3.1 Flash electrical specifications.............................. 23
3.4 Analog............................................................................. 24
3.4.1 ADC electrical specifications............................... 24
3.4.2
4
5
6
7
8
9
3.4.3 Voltage reference electrical specifications.......... 30
3.4.4 AFE electrical specifications................................31
3.5 Timers..............................................................................35
3.6 Communication interfaces............................................... 35
3.6.1 I2C switching specifications.................................35
3.6.2 UART switching specifications............................ 36
3.6.3 SPI switching specifications................................ 36
3.7 Human-Machine Interfaces (HMI)....................................40
3.7.1 LCD electrical characteristics.............................. 40
Dimensions............................................................................. 42
4.1 Obtaining package dimensions....................................... 42
Pinout...................................................................................... 42
5.1 KM35 Signal multiplexing and pin assignments.............. 42
5.2 KM35 Pinouts.................................................................. 50
Ordering parts......................................................................... 51
6.1 Determining valid orderable parts....................................51
Part identification.....................................................................52
7.1 Description.......................................................................52
7.2 Format............................................................................. 52
7.3 Fields............................................................................... 52
7.4 Example...........................................................................53
Terminology and guidelines.................................................... 53
8.1 Definition: Operating requirement....................................53
8.2 Definition: Operating behavior......................................... 53
8.3 Definition: Attribute.......................................................... 54
8.4 Definition: Rating............................................................. 54
8.5 Result of exceeding a rating............................................ 55
8.6 Relationship between ratings and operating
requirements....................................................................55
8.7 Guidelines for ratings and operating requirements..........55
8.8 Definition: Typical value...................................................56
8.9 Typical value conditions.................................................. 57
Revision History...................................................................... 57
CMP and 6-bit DAC electrical specifications....... 28
4
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Min.
Max.
Unit
Electrostatic discharge voltage, human body model
(All pins except RESET pin)
–4000
+4000
V
Electrostatic discharge voltage, human body model
(RESET pin only)
–2500
+2500
V
VCDM
Electrostatic discharge voltage, charged-device
model (for corner pins)
–750
+750
V
VCDM
Electrostatic discharge voltage, charged-device
model
–500
+500
V
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
VHBM
ILAT
Description
Notes
1
2
1. Determined according to JEDEC Standard JS-001-2014, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JS-001-2014, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
5
NXP Semiconductors
General
1.4 Voltage and current operating ratings
Symbol
Description
Min.
VDD
Digital supply voltage
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
VDTamper
VAIO
ID
Max.
Unit
–0.3
3.6
V
–0.3
VDD + 0.3
V
Tamper input voltage
–0.3
VBAT + 0.3
V
Analog1,
RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
–0.3
3.6
V
VDDA
Analog supply voltage
VBAT
RTC battery supply voltage
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Supply voltage when AFE is operational
2.7
3.6
V
Supply voltage when AFE is NOT operational
1.71
3.6
V
Analog supply voltage
2.7
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
–5
—
mA
• VIN < VSS–0.3 V (Negative current injection)
–3
—
• VIN > VDD+0.3 V (Positive current injection)
—
+3
–25
—
—
+25
VPOR_VBAT
—
VDD
VDDA
VBAT
VIH
VIL
RTC battery supply voltage
Input low voltage
VHYS
Input hysteresis
Digital pin negative DC injection current — single pin
• VIN < VSS–0.3 V
IICcont
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
mA
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
VRFVBAT
1
Input high voltage
IICDIO
IICAIO
Notes
VBAT voltage required to retain the VBAT register file
mA
V
1. VBAT always needs to be there for the chip to be operational.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
VPOR
Description
Min.
Typ.
Max.
Unit
Falling VDD POR detect voltage
0.8
1.1
1.5
V
Notes
Table continues on the next page...
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
7
NXP Semiconductors
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
VLVDH
Description
Min.
Typ.
Max.
Unit
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
IOHT
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = 5 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = 2.5 mA
VDD – 0.5
—
V
—
100
mA
Notes
Output high voltage — low-drive strength
Output high current total for all ports
Table continues on the next page...
8
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
VOL
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
0.5
V
Notes
Output low voltage — low-drive strength
IOLT
Output low current total for all ports
—
100
mA
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pull-up resistors
30
60
kΩ
1
RPD
Internal pull-down resistors
30
60
kΩ
2
1. Measured at Vinput = VSS.
2. Measured at Vinput = VDD.
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
•
CPU and system clocks = 75 MHz
Bus clock = 25 MHz
Flash clock = 25 MHz
Temperature: −40 °C, 25 °C, and 105 °C
VDD: 1.71 V, 3.3 V, and 3.6 V
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
After a POR event, amount of time from the
point VDD reaches 1.71 V to execute the first
instruction across the operating temperature
range of the chip.
563
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Typ.
Max.
Unit
Notes
659
μs
1
—
370
382
μs
—
370
382
μs
—
270
275
μs
—
270
275
μs
—
5
6
μs
—
5
6
μs
9
NXP Semiconductors
General
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
NOTE
The maximum (Max.) values stated in the following table
represent characterized results equivalent to the mean plus
three times the standard deviation (mean + 3×sigma).
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 3.0 V
• 25 °C
• –40 °C
• 105 °C
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 3.0 V
• 25 °C
• –40 °C
• 105 °C
IDD_WAIT
IDD_WAIT
IDD_VLPR
IDD_VLPR
Wait mode high frequency current at 3.0 V— all
peripheral clocks disabled and Flash is not in
low-power
• 25 °C
• –40 °C
• 105 °C
Wait mode high frequency current at 3.0 V— all
peripheral clocks disabled and Flash disabled
(put in low-power)
• 25 °C
• –40 °C
• 105 °C
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
• 25 °C
• –40 °C
• 105 °C
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
• 25 °C
• –40 °C
• 105 °C
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
2
—
8.82
9.15
mA
—
8.80
9.13
mA
—
9.19
9.59
mA
2
—
12.38
12.83
mA
—
12.32
12.76
mA
—
12.67
13.1
mA
2
—
5.78
5.90
mA
—
5.76
5.88
mA
—
6.34
6.52
mA
2
—
4.56
4.6
mA
—
4.56
4.68
mA
—
4.98
5.15
mA
3
—
212
500
μA
—
212
470
μA
—
550
900
μA
4
—
343
530
μA
—
327
507
μA
—
638
1000
μA
Table continues on the next page...
10
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VLPW
Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
• 25 °C
• –40 °C
• 105 °C
IDD_STOP
IDD_VLPS
Min.
Stop mode current at 3.0 V
• 25 °C
• –40 °C
• 105 °C
Very-low-power stop mode current at 3.0 V
• 25 °C
• –40 °C
• 105 °C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• 25 °C
• –40 °C
• 105 °C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• 25 °C
• –40 °C
• 105 °C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• 25 °C
• –40 °C
• 105 °C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• 25 °C
• –40 °C
• 105 °C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• 25 °C
• –40 °C
• 105 °C
IDD_VBAT
Average current with RTC and 32 kHz disabled
at 3.0 V and VDD is OFF
• 25 °C
• –40 °C
• 105 °C
Typ.
Max.
Unit
Notes
5
—
133
350
μA
—
132
330
μA
—
475
800
μA
—
406
730
μA
—
386
700
μA
—
792
898
μA
—
6.05
46
μA
—
2.68
44
μA
—
347
700
μA
—
2.78
3.86
μA
—
2.16
3.85
μA
—
61.9
—
2.45
3.06
μA
—
2.10
3.04
μA
—
40.2
59.5
μA
—
1.20
2.14
μA
—
1.07
1.84
μA
—
30.8
38.8
μA
—
0.261
0.67
μA
—
0.222
0.64
μA
—
29.1
38.0
μA
—
0.559
0.790
μA
—
0.494
0.784
μA
—
29.5
38.4
μA
—
0.243
1.00
μA
—
0.143
0.95
μA
—
6.05
15
μA
85.0
μA
Table continues on the next page...
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
11
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VBAT
Average current when VDD is OFF and LFSR
and Tamper clocks set to 2 Hz.
• @ 3.0 V
• 25 °C
• –40 °C
• 105 °C
Min.
Typ.
Max.
Unit
—
1.42
3.00
μA
1.24
2.96
μA
8.04
16.0
μA
Notes
6, 7
1. See all related analog peripheral specifications for IDDA.
2. 75 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FBE mode. All
peripheral clocks disabled.
3. 2 MHz core/system clock, and 1 MHz bus/flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing while (1) loop from flash.
4. 2 MHz core/system clock, and 1 MHz bus/flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but
peripherals are not in active operation. Code executing while (1) loop from flash.
5. 2 MHz core/system clock, and 1 MHz bus/flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
No flash accesses; some activity on DMA & RAM assumed.
6. Includes 32 kHz oscillator current and RTC operation.
7. An external power switch for VBAT should be present on board to have better battery life and keep VBAT pin powered in
all conditions. There is no internal power switch in RTC.
2.2.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.7 Capacitance attributes
Table 7. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
Input capacitance: fast digital pins
—
9
pF
CIN_D_io60
2.3 Switching specifications
12
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
General
2.3.1 Device clock specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
75
MHz
fBUS
Bus clock
—
25
MHz
Flash clock
—
25
MHz
—
6.5
MHz
fFLASH
fAFE
AFE Modulator clock
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
Flash clock
—
1
MHz
AFE Modulator clock2
—
1.6
MHz
fFLASH
fAFE
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2. AFE working in low-power mode.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Table 9. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Asynchronous path
16
—
ns
External reset pulse width (digital glitch filter
disabled)
100
—
ns
• 1.71 ≤ VDD ≤ 2.7 V
—
8
ns
• 2.7 ≤ VDD ≤ 3.6 V
—
5
ns
• 1.71 ≤ VDD ≤ 2.7 V
—
27
ns
• 2.7 ≤ VDD ≤ 3.6 V
—
16
ns
2
Port rise and fall time
• Slew disabled
• Slew enabled
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
13
NXP Semiconductors
Peripheral operating requirements and behaviors
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 10. Thermal operating requirements
Description
Min.
Max.1
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Symbol
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ . The simplest method to
determine TJ is:
TJ = TA + RθJA × chip power dissipation.
2.4.2 Thermal attributes
Rating
Board Type1
Symbol
100 LQFP
144 LQFP
Unit
Junction to
Ambient Thermal
Resistance2
JESD51-7, 2s2p
RθJA
48.6
41.7
°C/W
Junction-to-Top of
Package Thermal
Characterization
Parameter 2
JESD51-7, 2s2p
ΨJT
0.52
0.63
°C/W
1. Thermal test board meets JEDEC specification for this package (JESD51-7).
2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report
is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is
not meant to predict the performance of a package in an application-specific environment.
3 Peripheral operating requirements and behaviors
3.1 Core modules
14
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Peripheral operating requirements and behaviors
3.1.1 Single Wire Debug (SWD)
Table 11. SWD switching characteristics at 2.7 V (2.7–3.6 V)
Symbol
Description
Value
Unit
Notes
SWD CLK
Frequency of SWD
operation
20
MHz
Inputs, tSUI
Data setup time
5
ns
1
inputs, tHI
Data hold time
0
ns
1
after clock edge, tDVO
Data valid Time
32
ns
1
tHO
Data Valid Hold
0
ns
1
1. Input transition assumed = 1 ns. Output transition assumed = 50 pF.
Table 12. Switching characteristics at 1.7 V (1.7–3.6 V)
Symbol
Description
Value
Unit
Notes
SWD CLK
Frequency of SWD
operation
18
MHz
Inputs, tSUI
Data setup time
4.7
ns
1
inputs, tHI
Data hold time
0
ns
1
after clock edge, tDVO
Data valid Time
49.4
ns
2
tHO
Data Valid Hold
0
ns
1
1. Input transition assumed = 1 ns. Output transition assumed = 50 pF.
2. Frequency of SWD clock (18 MHz) is applicable only in case the input setup time of the device outside is not more
than 6.15 ns, else the frequency of SWD clock would need to be lowered.
3.1.2 Analog Front End (AFE)
AFE switching characteristics at (2.7 V–3.6 V)
Case 1: Clock is coming In and Data is also coming In (XBAR ports timed with
respect to AFE clock defined at pad PTB7, PTE3, and PTK4).
Table 13. AFE switching characteristics (2.7 V–3.6 V)
Symbol
Description
Value
Unit
Notes
AFE CLK
Frequency of operation 10
MHz
Inputs, tSUI
Data setup time
5
ns
1
inputs, tHI
Data hold time
0
ns
1
1. Input Transition: 1 ns. Output Load: 50 pF.
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
15
NXP Semiconductors
Peripheral operating requirements and behaviors
Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to
generated clock defined at the XBAR out ports).
Table 14. AFE switching characteristics (2.7 V–3.6 V)
Symbol
Description
Value
Unit
Notes
AFE CLK
Frequency of operation 6.2
MHz
Inputs, tSUI
Data setup time
36
ns
1
inputs, tHI
Data hold time
0
ns
1
1. Input Transition: 1 ns. Output Load: 50 pF.
AFE switching characteristics at (1.7 V–3.6 V)
Case 1: Clock is coming In and Data is also coming In (XBAR ports timed with respect
to AFE clock defined at pad PTB7, PTE3, and PTK4).
Table 15. AFE switching characteristics (1.7 V–3.6 V)
Symbol
Description
Value
Unit
Notes
AFE CLK
Frequency of operation 13
MHz
Inputs, tSUI
Data setup time
30
ns
1
inputs, tHI
Data hold time
5
ns
1
1. Input Transition: 1 ns. Output Load: 50 pF.
Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to
generated clock defined at XBAR out ports).
Table 16. AFE switching characteristics (1.7 V–3.6 V)
Symbol
Description
Value
Unit
Notes
AFE CLK
Frequency of operation 6.5
MHz
Inputs, tSUI
Data setup time
36
ns
1
inputs, tHI
Data hold time
0
ns
1
1. Input Transition: 1 ns. Output Load: 50 pF.
3.2 Clock modules
16
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Peripheral operating requirements and behaviors
3.2.1 MCG specifications
Table 17. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Δfints_t
Total deviation of internal reference
frequency (slow clock) over voltage and
temperature
—
+0.5/-0.7
—
%
Δfints_t
Total deviation of internal reference
frequency (slow clock) over fixed voltage
and full operating temperature range
-2
—
+2
%
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
fints_t
Internal reference frequency (slow clock) —
user trimmed
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature
— using SCTRIM and SCFTRIM
Δfdco_t
Total deviation of trimmed average DCO
output frequency over voltage and
temperature
—
+0.5/-0.7
Δfdco_t
Total deviation of trimmed average DCO
output frequency over fixed voltage and
temperature range of 0–70 °C
—
± 0.4
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
Δfintf_t
Total deviation of internal reference
frequency (fast clock) over voltage and
temperature — factory trimmed at nominal
VDD and 25 °C
fintf_t
Notes
%fdco
1
—
%fdco
1
4
—
MHz
—
+1/-2
—
%
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency
— RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency
— RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
20
20.97
22
MHz
40
41.94
45
MHz
60
62.91
67
MHz
80
83.89
90
MHz
—
23.99
—
MHz
FLL
fdco
DCO output
frequency
range
Low-range (DRS=00)
2, 3
640 × fints_t
Mid-range (DRS=01)
1280 × fints_t
Mid-high range (DRS=10)
1920 × fints_t
High-range (DRS=11)
2560 × fints_t
fdco_t_DMX32 DCO output
frequency
Low-range (DRS=00)
4, 5, 6
732 × fints_t
Table continues on the next page...
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
17
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
FLL period jitter
—
70
140
ps
7
FLL target frequency acquisition time
—
—
1
ms
8
11.71875
12.288
14.6484375
MHz
—
300
—
µA
39.0625
kHz
700
ps
Mid-range (DRS=01)
Notes
1464 × fints_t
Mid-high range (DRS=10)
2197 × fints_t
High-range (DRS=11)
2929 × fints_t
Jcyc_fll
tfll_acquire
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• IO 3.3 V current
• Max core voltage current
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
100
31.25
32.768
• fvco = 12 MHz
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. Chip maximum freq is 75 MHz, so high-range of DCO cannot be used and should not be configured.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. Chip max freq is 75 MHz, so High-range of DCO cannot be used and should not be configured.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.2.2 Oscillator electrical specifications
18
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Peripheral operating requirements and behaviors
3.2.2.1
Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 1 MHz
—
200
—
μA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 1 MHz
—
300
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, lowpower mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
6.6
—
kΩ
—
3.3
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
• 1 MHz resonator
• 2 MHz resonator
Table continues on the next page...
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
19
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol
Vpp5
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
• 4 MHz resonator
—
0
—
kΩ
• 8 MHz resonator
—
0
—
kΩ
• 16 MHz resonator
—
0
—
kΩ
• 20 MHz resonator
—
0
—
kΩ
• 32 MHz resonator
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation.
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
3.2.2.2
Symbol
Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
1
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
ms
tcst
Notes
1, 2
3, 4
Table continues on the next page...
20
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Peripheral operating requirements and behaviors
Table 19. Oscillator frequency specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
Notes
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.2.3 32 kHz oscillator electrical characteristics
3.2.3.1
32 kHz Oscillator Maximum Ratings
NOTE
Functional operating conditions are given in DC Electrical
Specifications. Absolute Maximum Ratings are stress ratings
only, and functional operation at the maxima is not
guaranteed. Stress beyond those listed may affect device
reliability or cause permanent damage to the device.
Table 20. 32 kHz oscillator absolute maximum ratings
Num
Symbol
1
VDD33OSC
Description
Min.
Max.
Unit
RTC oscillator
(A_IP_OSC_3v32k
VLP_NN_C90LP)
Module 3.3V
Analog Supply
Voltage
–0.3
3.6
V
2
VEXTAL
EXTAL Input
Voltage
–0.3
3.6
V
3
VXTAL
XTAL Input
Voltage
–0.3
3.6
V
4
TA
Operating
Temperature
Range (Packaged)
–40
135
°C
Table continues on the next page...
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
21
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 20. 32 kHz oscillator absolute maximum ratings (continued)
Num
Symbol
5
TJ
6
Tstg
3.2.3.2
Description
Min.
Max.
Unit
Operating
Temperature
Range (Junction)
–40
135
°C
Storage
Temperature
Range
–65
150
°C
32 kHz oscillator DC electrical specifications
Table 21. 32 kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.2.3.3
32 kHz oscillator frequency specifications
Table 22. 32 kHz Crystal and Oscillator Specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fosc_lo
Crystal
frequency
—
32.768
—
kHz
TA
Operating
temperature
-40
—
105
°C
1
Total crystal
frequency
tolerance
-500
—
500
ppm
2,3
CL
Load
capacitance
—
12.5
—
pF
2
ESR
Equivalent
series
resistance
—
—
80
kOhms
2
tstart
Crystal start-up
time
—
1000
—
ms
4
fec_extal32
External input
—
clock frequency
32.768
—
kHz
5
vec_xtal32
External input
0.7
clock amplitude
—
VDD
V
6
22
NXP Semiconductors
Notes
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Peripheral operating requirements and behaviors
1.
2.
3.
4.
5.
6.
Full temperature range of this device. A reduced range can be chosen to meet application needs.
Recommended crystal specification.
Sum of crystal initial frequency tolerance, crystal frequency stability, and aging tolerances given by crystal vendor.
Time from oscillator enable to clock stable. Dependent on the complete hardware configuration of the oscillator.
External oscillator connected to EXTAL32K. XTAL32K must be unconnected.
The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VDD.
3.3 Memories and memory interfaces
3.3.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.3.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
ms
1
1. Maximum time based on expectations at cycling end-of-life.
3.3.1.2
Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
tpgmchk
trdrsrc
Program Check execution time
—
—
45
μs
1
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
μs
1
tpgmonce
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
—
30
23
NXP Semiconductors
Peripheral operating requirements and behaviors
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.3.1.3
Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.3.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 26. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 105 °C.
3.4 Analog
3.4.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
3.4.1.1
16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
–100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
–100
0
+100
mV
2
Notes
Table continues on the next page...
24
NXP Semiconductors
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC operating conditions (continued)
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VREFH
ADC reference
voltage high
Absolute
VDDA
VDDA
VDDA
V
3
VREFL
ADC reference
voltage low
Absolute
VSSA
VSSA
VSSA
V
4
VADIN
Input voltage
VSSA
—
VDDA
V
CADIN
Input
capacitance
• 16-bit mode
—
8
10
pF
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
Symbol
RADIN
RAS
Input series
resistance
kΩ
Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 12-bit mode
1.0
—
18.0
MHz
6
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
6
Crate
ADC conversion
rate
≤ 12-bit modes
No ADC hardware averaging
5
7
20.000
—
818.330
kS/s
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
7
37.037
—
461.467
kS/s
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH is internally tied to VDDA.
4. VREFL is internally tied to VSSA.
5. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
6. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
7. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020
25
NXP Semiconductors
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 3. ADC input impedance equivalency diagram
3.4.1.2
16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
Conditions1
Min.
IDDA_ADC Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
Max.
Notes
0.215
—
1.7
mA
3
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
See Reference Manual chapter for sample times
Total
unadjusted error
• 12-bit modes
—
±4
±6.8
•
工商网监
湘ICP备2023018690号
