NXP Semiconductors
Data Sheet: Technical Data
KV5XP144M240
Rev. 5, 03/2020
KV5x Data Sheet
240 MHz Cortex-M7 based MCU for Real-time, high
performance connected control
The Kinetis KV5x family of MCU is a high-performance solution
offering exceptional precision, sensing, and control targeting
Motor Control, Industrial Drives and Automation, and Power
Conversion. Apart from the high performance Cortex-M7 core, it
features top notch real time control peripherals such as high
resolution pulse-width modulation (PWM) with 260 ps resolution,
4 Fast 12-bit ADCs with 5 MSps, up to 44 PWM channels for
supporting multi-motor systems. It also comes with multiple
communication peripherals including 3 FlexCAN modules,
optional Ethernet Communications, and multiple UART, SPI, and
I2C modules. The KV5x is supported by a comprehensive
enablement suite from NXP and third-party resources including
reference designs, software libraries, and motor configuration
tools.
Core
• ARM® Cortex®-M7 core up to 240 MHz with single
precision Floating Point Unit (FPU)
Memories
• Up to 1 MB program flash memory
• Up to 256 KB RAM
• External memory interface (FlexBus)
System peripherals
• 32-channel DMA controller
• Low-leakage wakeup unit
• SWD debug interface
• Advanced independent clocked watchdog
• JTAG debug interface
MKV58F1M0Vxx24
MKV56F1M0Vxx24
MKV58F512Vxx24
MKV56F512Vxx24
144 LQFP
20 x 20 x 1.4 mm Pitch
0.5 mm
144 BGA
13 x 13 x 1.23 mm
Pitch 1.0 mm
100 LQFP
14 x 14 x 1.4 mm Pitch 0.5 mm
Communication interfaces
• Six UART/FlexSCI modules with programmable 8or 9-bit data format
• Three 16-bit SPI modules
• Two I2C modules
• Three FlexCAN modules
• Ethernet Module (Optional)
Analog Modules
• Four 12-bit SAR High Speed ADCs with 5 MSPS
sample rate
• One 16-bit ADC
• Four CMPs with a 6-bit DAC and programmable
reference input
• One 12-bit DAC
Clocks
Timers
• 32 to 40 kHz or 3 to 32 MHz crystal oscillator
• Two eflexPWM with 4 sub-modules, with 12 PWM
• MCG with FLL and PLL referencing internal or external
outputs, one eflexPWM module with less than 285
reference clock
ps resolution provided by nano-edge module.
• Two 8-channel FlexTimers (FTM0 and FTM3)
Operating Characteristics
• Two 2-channel FlexTimers (FTM1 and FTM2)
• Voltage range: 1.71 to 3.6 V
• Four Periodic interrupt timers (PIT)
• Temperature range: –40 to 105 °C
• Two Programmable Delay Blocks (PDB)
• Quadrature Encoder/Decoder (ENC)
Human-machine interface
• General-purpose input/output
Security and integrity modules
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Hardware CRC module to support fast cyclic
redundancy checks
• External Watchdog Monitor (EWM)
• True Random Number Generator (TRNG)
• Memory mapped Cryptographic Acceleration Unit
(MMCAU)
• Advanced Watchdog (WDOG) timer modules
Orderable part numbers summary1
NXP part number
CPU
frequency
(MHz)
Ambient
operating
temperat
ure (°C)
Package
Flash/
SRAM
Ethernet
CAN
GPIO
MKV58F1M0VMD242
240
105
144
MAPBGA
1 MB/256
KB
Yes
3
111
MKV58F1M0VLQ24
240
105
144 LQFP
1 MB/256
KB
Yes
3
111
MKV58F1M0VLL24
240
105
100 LQFP
1 MB/256
KB
Yes
3
74
MKV56F1M0VMD242
240
105
144
MAPBGA
1 MB/256
KB
No
2
111
MKV56F1M0VLQ24
240
105
144 LQFP
1 MB/256
KB
No
2
111
MKV56F1M0VLL24
240
105
100 LQFP
1 MB/256
KB
No
2
74
MKV58F512VMD242
240
105
144
MAPBGA
512 KB/128
KB
Yes
3
111
MKV58F512VLQ24
240
105
144 LQFP
512 KB/128
KB
Yes
3
111
MKV58F512VLL24
240
105
100 LQFP
512 KB/128
KB
Yes
3
74
MKV56F512VMD242
240
105
144
MAPBGA
512 KB/128
KB
No
2
111
MKV56F512VLQ24
240
105
144 LQFP
512 KB/128
KB
No
2
111
MKV56F512VLL24
240
105
100 LQFP
512 KB/128
KB
No
2
74
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
2. The 144-pin MAPBGA package for this product is not yet available. However, it is included in a Package Your Way
program for Kinetis MCUs. Visit nxp.com/KPYW for more details.
Related Resources
Type
Selector
Guide
Description
The Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Resource
Solution Advisor
Table continues on the next page...
2
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Related Resources (continued)
Type
Description
Resource
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KV5XP144M240RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KV5XP144M2401
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_V_0N86P1
a particular device mask set.
KINETIS_V_1N86P1
Package
drawing
Package dimensions are provided in package drawings.
• MAPBGA 144-pin:
98ASA00222D1
• LQFP 144-pin:
98ASS23177W1
• LQFP 100-pin:
98ASS23308W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
KV5x Data Sheet, Rev. 5, 03/2020
3
NXP Semiconductors
MMCAU
Trace
Port
JTAG &
PPB
SWJ-DP
Serial Wire
AHBD
64b TCM
64KB ITCM
32b TCM
64KB DTCM
32b TCM
64KB DTCM
ETM
NVIC
MPU
ITM
DSP
FPB
SFPU
DWT
Cache Controller
8 KB D$
16 KB I$
TCM
32b AHBS
S0
S1
OSC
Arm Cortex-M7 Core
TPIU
PIT
IRC
IRC
FLL
WIC
MCG
32-39kHz 4 MHz
PLL
LPO
DMA
MUX
32b AHBP
1588 tmr
10/100 ENET
eDMA
32 ch
64b AXIM
PL301
M0
M1
M1
M0
S0
S1
Crossbar Switch (AXBS x32)
S6
SMPU
S4
M3
M2
S5
S2
SMPU
Port Split
OCRAM0
Flash
Controller
FlexBus
S3
64K
RAM
BME2
RGPIO
AHB to IPS x2
x256
Flash
1M Byte
eflexPWM
x4 subm
NanoEdge
CRC
eflexPWM
x4 subm
PMC
FlexTimer
8ch + 8ch+
2ch+2ch
3 x flexCAN
5MSPS-ADC
x4
16bit SAR ADC
Low-power
Timer
FlexSCI x6
12-bit DAC
TRNG
XBARA
XBARB
AOI
ENC
DSPI
x3
WDOG
PDB x2
PIT
I2C
x2
HSCMP x4
with 6b DAC?
EWM
Figure 1. KV5x block diagram
4
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Table of Contents
1 Ratings.................................................................................. 6
1.1 Thermal handling ratings............................................... 6
1.2 Moisture handling ratings...............................................6
1.3 ESD handling ratings..................................................... 6
1.4 Voltage and current operating ratings............................6
2 General................................................................................. 7
2.1 AC electrical characteristics...........................................7
2.2 Nonswitching electrical specifications............................7
2.2.1 Voltage and current operating requirements......8
2.2.2 HVD, LVD, and POR operating requirements....8
2.2.3 Voltage and current operating behaviors........... 9
2.2.4 Power mode transition operating behaviors.......10
2.2.5 Power consumption operating behaviors...........11
2.2.6 EMC radiated emissions operating behaviors... 15
2.2.7 Designing with radiated emissions in mind........ 16
2.2.8 Capacitance attributes....................................... 16
2.3 Switching specifications................................................. 16
2.3.1 Device clock specifications................................ 16
2.3.2 General switching specifications........................17
2.4 Thermal specifications................................................... 18
2.4.1 Thermal operating requirements........................18
2.4.2 Thermal attributes.............................................. 19
3 Peripheral operating requirements and behaviors................ 19
3.1 Core modules................................................................ 19
3.1.1 SWD Electricals ................................................ 19
3.1.2 Debug trace timing specifications...................... 21
3.1.3 JTAG electricals.................................................22
3.2 System modules............................................................ 25
3.3 Clock modules............................................................... 25
3.3.1 MCG specifications............................................ 25
3.3.2 Oscillator electrical specifications...................... 27
3.4 Memories and memory interfaces................................. 29
3.4.1 Flash (FTFE) electrical specifications................ 29
3.5 Flexbus switching specifications.................................... 31
3.6 Security and integrity modules.......................................34
3.7 Analog............................................................................34
3.7.1 12-bit SAR High Speed Analog-to-Digital
Converter (HSADC) parameters........................ 35
KV5x Data Sheet, Rev. 5, 03/2020
4
5
6
7
8
3.7.2 ADC electrical specifications..............................39
3.7.3 CMP and 6-bit DAC electrical specifications......44
3.7.4 12-bit DAC electrical characteristics.................. 45
3.8 Timers............................................................................ 48
3.8.1 Enhanced NanoEdge PWM characteristics....... 48
3.9 Communication interfaces............................................. 49
3.9.1 CAN switching specifications............................. 49
3.9.2 Ethernet switching specifications....................... 49
3.9.3 DSPI switching specifications (limited voltage
range).................................................................51
3.9.4 DSPI switching specifications (full voltage
range).................................................................52
3.9.5 I2C..................................................................... 54
3.9.6 UART................................................................. 54
Dimensions........................................................................... 54
4.1 Obtaining package dimensions......................................54
Pinouts and Packaging......................................................... 55
5.1 KV5x Signal Multiplexing and Pin Assignments............ 55
5.2 KV5x Pinouts................................................................. 64
Ordering parts....................................................................... 66
6.1 Determining valid orderable parts.................................. 66
Part identification...................................................................67
7.1 Description..................................................................... 67
7.2 Format........................................................................... 67
7.3 Fields............................................................................. 67
7.4 Example......................................................................... 68
Terminology and guidelines.................................................. 68
8.1 Definition: Operating requirement.................................. 68
8.2 Definition: Operating behavior....................................... 68
8.3 Definition: Attribute........................................................ 69
8.4 Definition: Rating........................................................... 69
8.5 Result of exceeding a rating.......................................... 69
8.6 Relationship between ratings and operating
requirements.................................................................. 70
8.7 Guidelines for ratings and operating requirements........ 70
8.8 Definition: Typical value................................................. 71
8.9 Typical Value Conditions............................................... 72
9 Revision History.................................................................... 72
5
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human-body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105 °C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-up Test.
1.4 Voltage and current operating ratings
6
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
General
Symbol
VDD
IDD
VIO
ID
VDDA
Description
Min.
Max.
Unit
Digital supply voltage
–0.3
3.8
V
—
2201
mA
Pin input voltage
–0.3
3.82
V
Instantaneous maximum current single pin limit (applies to
all port pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
Digital supply current
Analog supply voltage3
1. All VDD/VSS pins must be utilized for this value to be valid.
2. Maximum value of VIO must be 3.8 V.
3. Limits on VDDA also apply to VREFH.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2.2 Nonswitching electrical specifications
KV5x Data Sheet, Rev. 5, 03/2020
7
NXP Semiconductors
General
2.2.1 Voltage and current operating requirements
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is between 1 ms and 200 ms.
Table 1. Voltage and current operating requirements (VREFLx=0V, VSSA=0V, VSS=0V)
Symbol
Notes1
Description
Min
Max
Unit
VDD
Digital supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
VDD
3.6
V
VREFHx
ADC Reference Voltage High
1.8
VDDA
V
ΔVDD
Voltage difference VDD to VDDA
-0.1
0.1
V
ΔVSS
Voltage difference VSS to VSSA
-0.1
0.1
V
•
•
Input Voltage High (digital inputs)
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.7 x VDD
—
0.75 x VDD
—
•
•
Input Voltage Low (digital inputs)
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
—
0.35 x VDD
—
0.3 x VDD
-3
—
—
mA
-25
—
—
mA
VIH
VIL
IICIO
V
V
V
IO pin negative DC injection current – single pin.
VIN < VSS – 0.3V
IICcont
Contiguous pin DC injection current – regional limit,
includes sum of negative injection currents of 16
contiguous pins
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
• Pin Group 6: PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4. have high output current capability
2. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is
greater than VIO_MIN (= VSS-0.3 V), then there is no need to provide current limiting resistors at the pads. If this limit
cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R = (VIO_MIN - VIN)/|IICIO|.
2.2.2 HVD, LVD, and POR operating requirements
Table 2. VDD supply HVD, LVD and POR operating requirements
Symbol
VPOR
Description
Min.
Typ.
Max.
Unit
Falling VDD POR detect voltage
0.8
1.1
1.5
V
Notes
Table continues on the next page...
8
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
2
General
Table 2. VDD supply HVD, LVD and POR operating requirements (continued)
Symbol
VLVDH
Description
Min.
Typ.
Max.
Unit
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Notes
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
±80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
VHVDH
High Voltage Detect (High Trip Point)
—
3.7202
—
V
VHVDL
High Voltage Detect (Low Trip Point)
—
3.4582
—
V
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
±60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
VOH
VOH
Description
Min.
Typ.
Max.
Unit
Notes
2.7 V ≤ VDD ≤ 3.6 V, IOH = -10 mA
VDD – 0.5
—
—
V
1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -5 mA
VDD – 0.5
—
—
V
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
VDD – 0.5
—
—
V
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
VDD – 0.5
—
—
V
Output high voltage — Normal drive pad
except RESET_B
Output high voltage — High drive pad
except RESET_B
1
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
9
NXP Semiconductors
General
Table 3. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
—
100
mA
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
0.5
V
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
V
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
—
0.5
V
Output low current total for all ports
—
—
100
mA
—
0.002
0.5
μA
IOHT
Output high current total for all ports
VOL
Output low voltage — Normal drive pad
except RESET_B
VOL
VOL
IOLT
IIN
1
Output low voltage — High drive pad
except RESET_B
1
Output low voltage — RESET_B
Input leakage current (per pin) for full
temperature range
All pins other than high drive port pins
High drive port pins
VODPU
Notes
Open drain pullup voltage level
1, 2
—
0.004
0.5
μA
VDD
—
VDD
mA
3
RPU
Internal pullup resistors
20
—
50
kΩ
4
RPD
Internal pulldown resistors
20
—
50
kΩ
5
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability selected
by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Open drain outputs must be pulled to VDD.
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus and flash clock = 25 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
Min.
Typ.
Max.
Unit
—
—
300
μs
Notes
Table continues on the next page...
10
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
General
Table 4. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
—
149
μs
—
—
149
μs
—
—
79
μs
—
—
5.7
μs
—
—
5.7
μs
Notes
first instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
2.2.5 Power consumption operating behaviors
NOTE
In the following table, the maximum values represent
characterized results equivalent to the mean plus three times
the standard deviation (mean + 3σ).
Table 5. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Run mode current — all peripheral clocks
disabled, code executing from flash, while(1)
loop, excludes ADC IDDA
• @ 1.8V
Min.
Typ.
Max.
Unit
Notes
—
5
8
mA
HSADC0 and
HSADC1 with
66.6 MHz
clock, ADC0
with 25 MHz
clock.
Core frequency
of 25 MHz
—
7.5
36
mA
—
7.6
39
mA
• @ 3.0V
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash, while(1)
loop, excludes ADC IDDA
• @ 1.8V
• @ 3.0V
Core frequency
of 50 MHz
—
10.8
—
mA
—
10.8
—
mA
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
11
NXP Semiconductors
General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash, while(1)
loop, excludes ADC IDDA
• @ 3.0V
• @25°C
• @105°C
IDD_RUN
Typ.
Max.
Unit
Core frequency
of 160 MHz.
—
27.9
30.0
mA
—
44.3
55.7
mA
Run mode current — all peripheral clocks
disabled, running benchmark code from
flash, excludes ADC IDDA
• @ 3.0V
• @25°C
• @105°C
—
70.0
—
mA
—
79.9
—
mA
IDD_HSRUN Run mode current — all peripheral clocks
disabled, code executing from flash, while(1)
loop, excludes ADC IDDA
• @ 3.0V
• @25°C
• @105°C
Notes
CoreMark
benchmark
compiled using
IAR 7.50 with
optimization
level set to
High for Speed
with no size
constraints
option
selected.
Clock
frequencies
configured as
follows:
•
Core
clock is
160 MHz
•
Fast
Peripher
al clock
is 80
MHz
• Flexbus
clock is
26.67
MHz
•
Bus/
Flash
clock is
26.67
MHz
Core frequency
of 240 MHz.
—
43.8
47.1
mA
—
62.5
80.8
mA
IDD_HSRUN Run mode current — all peripheral clocks
enabled, code executing from flash, while(1)
loop, excludes ADC IDDA
• @ 3.0V
Core frequency
of 240 MHz.
Nanoedge
module at 120
MHz.
Table continues on the next page...
12
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• @ 25°C
—
70.8
74.1
mA
• @ 105°C
—
92.3
107.9
mA
IDD_HSRUN HSRun mode current — all peripheral clocks
disabled, running benchmark code from
flash, excludes ADC IDDA
• @ 3.0V
Notes
CoreMark
benchmark
compiled using
IAR 7.50 with
optimization
level set to
High for Speed
with no size
constraints
option
selected.
Clock
frequencies
configured as
follows:
•
Core
clock is
240 MHz
•
Fast
Peripher
al clock
is 120
MHz
• Flexbus
clock is
30 MHz
•
Bus/
Flash
clock is
24 MHz
—
116
—
mA
—
132.9
—
mA
Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
16.3
—
mA
160 MHz PEE
mode, Fast
Peripheral
clock = 80
MHz, Flexbus
clock = 80
MHz, Bus/
Flash clock =
20 MHz
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
—
0.729
7.6
mA
CPU frequency
4 MHz
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
—
1.2
9.4
mA
CPU frequency
4 MHz
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
—
0.33
0.43
mA
4 MHz System/
Core clock,
Fast peripheral
clock, and
Flexbus clock.
• @ 25°C
• @ 105°C
IDD_WAIT
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
13
NXP Semiconductors
General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
1 MHz bus/
flash clock. All
peripheral
clocks
disabled. Temp
= 25°C.
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
0.55
0.91
mA
• @ 105°C
—
11.1
18.3
mA
• @ –40 to 25°C
—
0.107
0.33
mA
• @ 105°C
—
4.0
7.6
mA
• @ –40 to 25°C
—
5.2
8.6
μA
• @ 70°C
—
29.8
85
μA
• @ 105°C
—
122.4
185
μA
• @ –40 to 25°C
—
3.2
4.8
μA
• @ 70°C
—
11.6
45
μA
• @ 105°C
—
47.2
71
μA
• @ –40 to 25°C
—
0.778
2.6
μA
• @ 70°C
—
3.9
21
μA
• @ 105°C
—
18.8
36
μA
• @ –40 to 25°C
—
0.5
2.1
μA
• @ 70°C
—
3.4
21
μA
• @ 105°C
—
18.2
36
μA
• @ –40 to 25°C
—
0.147
1.69
μA
• @ 70°C
—
3.0
16.8
μA
• @ 105°C
—
17.6
29.2
μA
IDD_VLPS Very-low-power stop mode current at 3.0 V
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0
V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0
V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0
V
IDD_VLLS0B Very low-leakage stop mode 0 current at 3.0
V with POR detect circuit enabled
IDD_VLLS0A Very low-leakage stop mode 0 current at 3.0
V with POR detect circuit disabled
14
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
General
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS
mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
nA
VLLS1
VLLS3
440
490
540
560
570
580
LLS
440
490
540
560
570
580
VLPS
490
490
540
560
570
680
STOP
510
560
560
560
610
680
510
560
560
560
610
680
22
22
22
22
22
22
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
KV5x Data Sheet, Rev. 5, 03/2020
µA
µA
66
66
66
66
66
66
214
234
246
254
260
268
45
45
45
45
45
45
µA
15
NXP Semiconductors
General
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
VEME
Conditions
Device configuration, test
conditions and EM testing per
standard IEC 61967-2.
• Supply voltage VDD = 3.3
V
• Temperature = 25 °C
Clocks
Frequency
band (MHz)
Typ.
Unit
Notes
• fOSC= 20
MHz
(crystal)
• fSYS = 150
MHz
0.15–50
14
dBμV
1
50–150
25
dBμV
150–500
23
dBμV
500–1000
16
dBμV
0.15–1000
K
—
2
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
16
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
General
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
—
240
MHz
Notes
High Speed run mode
fsys
System (CPU) clock
Normal run mode (and High Speed run mode unless otherwise specified above)
fsys
System (CPU) clock
—
160
MHz
Fast Peripheral Clock
—
120
MHz
FB_CLK
FlexBus clock
—
60
MHz
fBus_Flash
Bus / Flash clock
—
27.5
MHz
—
24
MHz
System (CPU) clock
—
4
MHz
Fast Peripheral Clock
—
4
MHz
FB_CLK
FlexBus clock
—
4
MHz
fBus_Flash
Bus / Flash Clock
—
500
kHz
fERCLK
External reference clock
—
16
MHz
fLPTMR
LPTMR clock
—
24
MHz
fFastPeripheral
fLPTMR
LPTMR clock
1
VLPR mode
fsys
fFastPeripheral
2
1. When using this clock to supply the nano-edge module, this clock must be 1/2 of the system clock.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is a clock input connected to the
EXTAL pin with the OSC configured for bypass (external clock) operation.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
FlexCAN, and I2C signals.
Table 10. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter enabled,
analog filter disabled) — Asynchronous path
80
—
ns
2
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled) — Asynchronous path
50
—
ns
2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
10
—
ns
2
Port rise and fall times
3, 4
Normal drive fast pins
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
17
NXP Semiconductors
General
Table 10. General switching specifications (continued)
Description
• 2.7≤ VDD ≤ 3.6 V
• Fast slew rate
Min.
Max.
Unit
—
0.7
ns
—
16
ns
• Slow slew rate
• 1.71≤ VDD < 2.7 V
• Fast slew rate
Notes
2.15
16
• Slow slew rate
Port rise and fall times
3, 5
High drive fast pins (normal/low drive enabled)
• 2.7≤ VDD ≤ 3.6 V
• Fast slew rate
—
0.7
—
15.65
• Slow slew rate
• 1.71≤ VDD < 2.7 V
• Fast slew rate
ns
ns
2.35
35.3
• Slow slew rate
Port rise and fall times
High drive fast pins (high drive enabled)
• 2.7≤ VDD ≤ 3.6 V
• Fast slew rate
—
3
—
16.5
• Slow slew rate
• 1.71≤ VDD < 2.7 V
• Fast slew rate
ns
ns
6.5
36.3
• Slow slew rate
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (normal/low drive) is 25pF. Fast slew rate is
enabled by clearing PORTx_PCRn[SRE].
4. Normal drive fast pins: All other GPIO pins that are not high drive fast pins.
5. High drive fast pins: PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7. High drive capability is enabled by
setting PORTx_PCRn[DSE]
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
18
NXP Semiconductors
Notes
1
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 12. Thermal attributes
Board type
Symbol
Single-layer (1S)
RθJA
Four-layer (2s2p)
Description
144
MAPBG
A1
144
LQFP
100
LQFP
Unit
Notes
Thermal resistance, junction to
ambient (natural convection)
—
51
51
°C/W
2
RθJA
Thermal resistance, junction to
ambient (natural convection)
—
42
38
°C/W
Single-layer (1S)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
42
41
°C/W
Four-layer (2s2p)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
36
32
°C/W
—
RθJB
Thermal resistance, junction to
board
—
30
23
°C/W
3
—
RθJC
Thermal resistance, junction to
case
—
11
10
°C/W
4
—
ΨJT
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
—
2
2
°C/W
5
1. Package Your Way
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
3. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
4. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
5. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
KV5x Data Sheet, Rev. 5, 03/2020
19
NXP Semiconductors
Peripheral operating requirements and behaviors
3.1.1 SWD Electricals
Table 13. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 3. Serial wire clock input timing
20
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 4. Serial wire data timing
3.1.2 Debug trace timing specifications
Table 14. Debug trace operating behaviors
Symbol
Description
Tcyc
Clock period
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
1.5
ns
Th
Data hold
2
1.0
ns
KV5x Data Sheet, Rev. 5, 03/2020
Min.
Max.
Unit
Frequency dependent
MHz
21
NXP Semiconductors
Peripheral operating requirements and behaviors
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
3.1.3 JTAG electricals
Table 15. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
28
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
22
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
Table 15. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J11
TCLK low to TDO data valid
—
19
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 16. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
30.6
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.0
—
ns
J11
TCLK low to TDO data valid
—
19.0
ns
J12
TCLK low to TDO high-Z
—
17.0
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
KV5x Data Sheet, Rev. 5, 03/2020
23
NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
24
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
± 0.5
±2
%fdco
1,
±1
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
(3/5) x
fints_t
—
—
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
Min.
Typ.
Max.
Unit
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
2, 3
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
4, 5
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
6
PLL
8
—
16
MHz
fvcoclk_2x
fpll_ref
VCO output frequency
220
—
480
MHz
fvcoclk
PLL output frequency
110
—
240
MHz
PLL quadrature output frequency
110
—
240
MHz
—
2.8
—
mA
—
4.7
—
mA
fvcoclk_90
PLL reference frequency range
Ipll
PLL operating current
• VCO @ 176 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 22)
Ipll
PLL operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 45)
Jcyc_pll
Jacc_pll
PLL period jitter (RMS)
7
7
8
• fvco = 48 MHz
—
120
—
ps
• fvco = 120 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
8
Table continues on the next page...
26
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Dunl
tpll_lock
Description
Min.
Typ.
Max.
Unit
• fvco = 48 MHz
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
± 4.47
—
± 5.97
Lock exit frequency tolerance
Lock detector detection time
F_MCGO Device Clock
UT
Frequency
• using
internal
RC
oscillator
• using
external
clock
source
10-6
—
—
150 ×
+ 1075(1/
fpll_ref)
0.04
100
MHz
0
240
Notes
%
s
9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1
Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
• 32 kHz
Notes
1
—
500
—
nA
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
27
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol
IDDOSC
Description
Min.
Typ.
Max.
Unit
• 4 MHz
—
200
—
μA
• 8 MHz
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 4 MHz
—
400
—
μA
• 8 MHz
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
Cy
XTAL load capacitance
—
—
—
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, lowpower mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
RS
Notes
2, 3
2, 3
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
Table continues on the next page...
28
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol
Description
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
Min.
Typ.
Max.
Unit
—
VDD
—
V
Notes
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2
Symbol
Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Min.
Typ.
Max.
Unit
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
1000
—
ms
fosc_lo
tcst
Description
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.4 Memories and memory interfaces
3.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
KV5x Data Sheet, Rev. 5, 03/2020
29
NXP Semiconductors
Peripheral operating requirements and behaviors
NOTE
All flash programerase functions can only be performed when
the MCU is in Normal Run mode. Programming or erasing
the flash in HSRUN mode is not allowed.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol
Description
thvpgm8
thversscr
thversall1m
Min.
Typ.
Max.
Unit
Notes
Program Phrase high-voltage time
—
7.5
18
μs
Erase Flash Sector high-voltage time
—
13
113
ms
1
Erase All Blocks high-voltage time for 1 MB
—
832
7232
ms
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec8k
Read 1s Section execution time (8 KB flash)
—
—
200
μs
1
tpgmchk
Program Check execution time
—
—
95
μs
1
trdrsrc
Read Resource execution time
—
—
40
μs
1
tpgm8
Program Phrase execution time
—
90
150
μs
tersscr
Erase Flash Sector execution time
—
15
115
ms
Program Section execution time (1 KB flash)
—
5
—
ms
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
trdonce
Read Once execution time
—
—
30
μs
Program Once execution time
—
90
—
μs
tersall
Erase All Blocks execution time
—
870
7400
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tersallu
Erase All Blocks Unsecure execution time
—
870
7400
ms
2
tpgmsec1k
tpgmonce
2
1
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
30
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
3.4.1.3
Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage flash
programming operation
—
3.5
7.5
mA
Average current adder during high voltage flash
erase operation
—
1.5
4.0
mA
Reliability specifications
Table 23. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 24. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
FB_CLK
MHz
1/FB_CLK
—
ns
FB1
Clock period
FB2
Address, data, and control output valid
—
11.8
ns
FB3
Address, data, and control output hold
1.0
—
ns
Notes
1
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
31
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 24. Flexbus limited voltage range switching specifications (continued)
Num
Description
Min.
Max.
Unit
FB4
Data and FB_TA input setup
11.9
—
ns
FB5
Data and FB_TA input hold
0.0
—
ns
Notes
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 25. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Frequency of operation
—
FB_CLK
MHz
1/FB_CLK
—
ns
Address, data, and control output valid
—
12.6
ns
FB3
Address, data, and control output hold
1.0
—
ns
FB4
Data and FB_TA input setup
12.5
—
ns
FB5
Data and FB_TA input hold
0
—
ns
FB1
Clock period
FB2
Notes
1
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
32
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
FB3
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
electricals_read.svg
FB4
FB_BEn
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
S0
S1
S2
S3
S0
Figure 11. FlexBus read timing diagram
KV5x Data Sheet, Rev. 5, 03/2020
33
NXP Semiconductors
Peripheral operating requirements and behaviors
Write Timing Parameters
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB_BEn
electricals_write.svg
FB4
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 12. FlexBus write timing diagram
3.6 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.7 Analog
34
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
3.7.1 12-bit SAR High Speed Analog-to-Digital Converter (HSADC)
parameters
Table 26. 12-bit HSADC electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Analog supply voltage
VDDA
1.71
—
3.6
V
Vrefh Supply Voltage
• VDDA ≥ 2V
Vrefh
VDDA
VDDA
V
VSSA
0.1
V
Vrefh
V
Recommended Operating Conditions
2.0
VDDA
• VDDA < 2V
Vrefl Supply Voltage
Vrefl
VSSA
Analog Input
Full-scale input range (single-ended mode)
Vrefl
Full-scale input range (differential mode)
2*(Vrefh - Vrefl)
V
Input signal common mode (only for
differential mode)
(Vrefh + Vrefl)/2
V
5
pF
Input sampling capacitance (no parasitic
capacitances included)
Cs
Current Consumption
Fs=5MSPS (Conversion in progress,
differential mode)1
• IDDA
µA
—
1150
—
—
85
—
• IDD
Fs=1MSPS (Conversion in progress,
differential mode)1
• IDDA
µA
—
260
—
—
19
—
• IDD
Fs=10kSPS (Conversion in progress,
differential mode)1
• IDDA
µA
—
19
—
—
2.9
—
• IDD
Fs=5MSPS (Conversion in progress, singleended mode)1
• IDDA
µA
—
1030
—
—
85
—
• IDD
Fs=1MSPS (Conversion in progress, singleended mode)1
• IDDA
µA
—
230
—
—
18
—
• IDD
Fs=10kSPS (Conversion in progress, singleended mode)1
µA
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
35
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 26. 12-bit HSADC electrical specifications (continued)
Characteristic
Symbol
• IDDA
• IDD
Fs=5MSPS (Conversion not in progress)
• IDDA
Min
Typ
Max
—
19
—
—
2.9
—
Unit
µA
• IDD
Fs=1MSPS (Conversion not in progress)
• IDDA
—
38
—
—
57
—
µA
• IDD
Fs=10kSPS (Conversion not in progress)
• IDDA
—
22
—
—
14
—
µA
• IDD
—
19
—
—
2.7
—
Timing Characteristics
Input clock frequency
fclk
0.14
70
80
MHz
Input clock frequency during calibration
fclk
0.14
—
60
MHz
Sampling
rate2
Fs
• ADCRES=11 (12 bits conversion result)
• ADCRES=10 (10 bits conversion result)
• ADCRES=01 (8 bits conversion result)
• ADCRES=00 (6 bits conversion result)
MSPS
0.01
5
5.71
0.012
5.83
6.66
0.014
7
8
0.0175
8.75
10
Conversion cycle2 (back to back)
Clock cycles
14
• ADCRES=11 (12 bits conversion result)
12
• ADCRES=10 (10 bits conversion result)
10
• ADCRES=01 (8 bits conversion result)
8
• ADCRES=00 (6 bits conversion result)
Data latency2
Clock cycles
12.5
• ADCRES=11 (12 bits conversion result)
10.5
• ADCRES=10 (10 bits conversion result)
8.5
• ADCRES=01 (8 bits conversion result)
6.5
• ADCRES=00 (6 bits conversion result)
Accuracy (DC or Absolute)
Integral non-Linearity
INL
+/- 3.0
LSB
Differential non-Linearity
DNL
+/- 1.0
LSB
Table continues on the next page...
36
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
Table 26. 12-bit HSADC electrical specifications (continued)
Characteristic
Symbol
Signal-to-noise and distortion
ratio3
Min
Typ
SINAD
Max
Unit
65
dBFS
Offset error (calibration enabled)
+/- 2.0
LSB
Offset error (calibration disabled)
+/- 64
LSB
+/- 5
LSB
Total unadjusted error (calibration enabled)
TUE
1. Successive conversion mode
2. "ADCRES" refers to the resolution selection control signal
3. Value measured with a –0.5dBFS input signal and then extrapolated to full scale.
Table 27. HSADC Input Resolution Table
Typical
Input
Channels
CHN 0 - 5
Resolution
12-bit
10-bit
8-bit
Rin (k)
Min
Sampling
Time (ns)
Worst Case
Additional
clk cycles
(SAMPT_x
)
Total
Cycles
Min
Sampling
Time (ns)
Additional
clk cycles
(SAMPT_x
)
Total
Cycles
0.02
9
0
2
20
1
3
0.07
11
0
2
23
1
3
0.17
17
0
2
29
1
3
0.47
34
2
4
46
3
5
0.97
62
4
6
77
5
7
4.97
288
22
24
368
28
30
9.97
576
45
47
840
66
68
19.97
1179
93
95
1490
118
120
49.97
3139
250
252
3240
258
260
99.97
7679
613
615
6199
495
497
0.02
7
0
2
16
0
2
0.07
9
0
2
18
0
2
0.17
14
0
2
23
1
3
0.47
28
1
3
37
2
4
0.97
51
3
5
63
4
6
4.97
239
18
20
274
21
23
9.97
475
37
39
552
43
45
19.97
949
75
77
1177
93
95
49.97
2409
192
194
3240
258
260
99.97
4919
393
395
6199
495
497
0.02
6
0
2
12
0
2
0.07
8
0
2
14
0
2
0.17
11
0
2
18
0
2
0.47
23
1
3
30
1
3
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
37
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 27. HSADC Input Resolution Table (continued)
Typical
Input
Channels
Resolution
6-bit
All other
channels
12-bit
10-bit
8-bit
Rin (k)
Min
Sampling
Time (ns)
Worst Case
Additional
clk cycles
(SAMPT_x
)
Total
Cycles
Min
Sampling
Time (ns)
Additional
clk cycles
(SAMPT_x
)
Total
Cycles
0.97
41
2
4
50
3
5
4.97
192
14
16
216
16
18
9.97
380
29
31
425
66
68
19.97
758
60
62
852
67
69
49.97
1909
152
154
2209
176
178
99.97
3819
305
307
4875
389
391
0.02
4
0
2
9
0
2
0.07
6
0
2
10
0
2
0.17
9
0
2
13
0
2
0.47
17
0
2
23
1
3
0.97
31
1
3
38
2
4
4.97
144
11
13
162
12
14
9.97
286
22
24
318
24
26
19.97
571
45
47
630
49
51
49.97
1429
113
115
1579
125
127
99.97
2859
228
230
3189
254
256
0.1
41
2
4
75
5
7
0.6
69
5
7
114
8
10
4.6
296
23
25
494
39
41
9.6
584
46
48
919
73
75
19.6
1189
94
96
1669
133
135
49.6
3169
253
255
3589
286
288
99.6
7689
614
616
6869
549
551
0.1
34
2
4
59
4
6
0.6
57
4
6
89
6
8
4.6
244
19
21
331
25
27
9.6
480
37
39
665
52
54
19.6
953
75
77
1669
133
135
49.6
2409
192
194
3589
286
288
99.6
4929
393
395
6869
549
551
0.1
27
1
3
47
3
5
0.6
46
3
5
70
5
7
4.6
196
15
17
255
19
21
9.6
384
30
32
491
38
40
Table continues on the next page...
38
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
Table 27. HSADC Input Resolution Table (continued)
Typical
Input
Channels
Resolution
6-bit
Rin (k)
Min
Sampling
Time (ns)
Worst Case
Additional
clk cycles
(SAMPT_x
)
Total
Cycles
Min
Sampling
Time (ns)
Additional
clk cycles
(SAMPT_x
)
Total
Cycles
19.6
761
60
62
977
77
79
49.6
1909
152
154
2619
209
211
99.6
3819
305
307
6869
549
551
0.1
21
1
3
36
2
4
0.6
35
2
4
53
3
5
4.6
148
11
13
191
14
16
9.6
290
22
24
365
28
30
19.6
573
45
47
714
56
58
49.6
1439
114
116
1789
142
144
99.6
2859
228
230
3629
289
291
3.7.2 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 1 and Table 29 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.7.2.1
16-bit ADC operating conditions
Table 28. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD –
VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS –
VSSA)
-100
0
+100
mV
2
VREFH
ADC reference voltage
high
1.13
VDDA
VDDA
V
VREFL
ADC reference voltage
low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
Table continues on the next page...
KV5x Data Sheet, Rev. 5, 03/2020
39
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC operating conditions (continued)
Symbol
CADIN
RADIN
RAS
Description
Input capacitance
Min.
Typ.1
Max.
Unit
• 16-bit mode
—
8
10
pF
• 8-bit / 10-bit /
12-bit modes
—
4
5
—
2
5
Conditions
Input series resistance
Notes
kΩ
Analog source
resistance (external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion clock
frequency
≤ 13-bit mode
1.0
—
24.0
MHz
4
fADCK
ADC conversion clock
frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion rate
≤ 13-bit modes
No ADC hardware
averaging
3
5
20.000
—
818.330
ksps
Continuous
conversions
enabled, subsequent
conversion time
Crate
ADC conversion rate
16-bit mode
No ADC hardware
averaging
5
37.037
—
461.467
ksps
Continuous
conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
40
NXP Semiconductors
KV5x Data Sheet, Rev. 5, 03/2020
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 13. ADC input impedance equivalency diagram
3.7.2.2
16-bit ADC electrical characteristics
Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
IDDA_ADC Supply current
ADC asynchronous
clock source
fADACK
Sample Time
TUE
DNL
INL
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
•
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