NXP Semiconductors
Data Sheet: Advance Information
MKW40Z/30Z/20Z Data Sheet
Document Number MKW40Z160
Rev. 1.2, 05/2018
MKW40Z160 MKW30Z160
MKW20Z160
A Bluetooth® Low Energy and IEEE®
802.15.4 System on a Chip (SoC)
Supports the following:
MKW40Z160VHT4, MKW30Z160VHM4,
MKW20Z160VHT4
Key features
• Multi-Standard Radio
– 2.4 GHz Bluetooth Low Energy version 4.1
compliant
– IEEE Standard 802.15.4 2011 compliant
– Typical Receiver Sensitivity (BLE) = -91 dBm
– Typical Receiver Sensitivity (802.15.4) = -102 dBm
– Programmable Transmitter Output Power: -18 dBm
to +5 dBm
– Low external component counts for low cost
application
• MCU and Memories
– Up to 48 MHz ARM® Cortex-M0+ core
– On-chip 160 KB Flash memory
– On-chip 20 KB SRAM
• Low Power Consumption
– Typical Rx Current: 6.5 mA (DCDC in buck mode,
3.6 V supply)
– Typical Tx Current: 8.4 mA (DCDC in buck mode,
3.6 V supply) for a 0 dBm output
– Low Power Mode (VLLS0) Current: 206 nA
• Clocks
– 32 MHz Crystal Oscillator
– 32 kHz Crystal Oscillator
• System peripherals
– Nine low-power modes to provide power
optimization based on application requirements
– DCDC Converter supporting Buck, Boost, and
Bypass modes
– DMA Controller
– COP Software watchdog
– SWD Interface and Micro Trace buffer
– Bit Manipulation Engine (BME)
• Human-machine interface
– Touch Sensing Input
– General-purpose input/output
• Analog modules
– 16-bit Analog-to-Digital Converter (ADC)
– 12-bit Digital-to-Analog Converter (DAC)
– 6-bit High Speed Analog Comparator (CMP)
• Timers
– 16-bit low-power timer (LPTMR)
– 3 Timers Modules(TPM): One 4 channels TPM and
Two 2 channels TPMs
– Programmable Interrupt Timer (PIT)
– Real-Time Clock (RTC)
• Communication interfaces
– 2 SPI modules
– 2 I2C modules
– Low Power UART module
– Carrier Modulator Timer (CMT)
• Security
– AES-128 Accelerator (AESA)
– True Random Number Generator (TRNG)
• Operating Characteristics
– DCDC Converter supporting Buck, Boost, and
Bypass modes
– Temperature range (ambient): -40 to 85°C
This document contains information on a pre-production product. Specifications
and pre-production information herein are subject to change without notice.
Table of Contents
1
Ordering information......................................................................... 4
2
Feature Descriptions...........................................................................4
6.2.8
6.3 Switching electrical specifications............................................ 34
2.1 Block diagram............................................................................4
6.3.1
Device clock specifications..........................................34
2.2 Radio features............................................................................ 5
6.3.2
General switching specifications................................. 34
2.3 Microcontroller features............................................................ 6
3
4
6.4.1
Thermal operating requirements.................................. 35
2.5 Peripheral features..................................................................... 9
6.4.2
Thermal attributes........................................................ 35
Transceiver Description..................................................................... 13
6.5 Peripheral operating requirements and behaviors......................36
3.1 Key Specifications..................................................................... 14
6.5.1
Core modules............................................................... 36
3.2 Frequency Plan for Bluetooth Low Energy............................... 14
6.5.2
System modules........................................................... 37
3.3 Frequency Plan for 802.15.4 and 802.15.4j (MBAN)............... 16
6.5.3
Clock modules............................................................. 38
3.4 Transceiver Functions................................................................17
6.5.4
Memories and memory interfaces................................39
System and Power Management........................................................ 17
6.5.5
Security and integrity modules.................................... 41
4.1 Power Management................................................................... 17
6.5.6
Analog..........................................................................41
DCDC Converter......................................................... 18
6.5.7
Timers.......................................................................... 50
4.2 Modes of Operation................................................................... 18
6.5.8
Communication interfaces........................................... 50
6.5.9
Human-machine interfaces (HMI)............................... 55
4.2.1
6
6.4 Thermal specifications...............................................................35
2.4 System features..........................................................................7
4.1.1
5
Capacitance attributes.................................................. 33
Power modes................................................................18
Transceiver Electrical Characteristics................................................21
7
KW40Z Electrical Characteristics......................................................55
5.1 Recommended radio operating conditions................................ 21
7.1 DCDC Converter Recommended Electrical Characteristics..... 56
5.2 Receiver Feature Summary........................................................21
7.2 Ratings....................................................................................... 57
5.3 Transmit and PLL Feature Summary........................................ 23
7.2.1
Thermal handling ratings............................................. 57
MCU Electrical Characteristics..........................................................24
7.2.2
Moisture handling ratings............................................ 58
6.1 AC electrical characteristics...................................................... 24
7.2.3
ESD handling ratings................................................... 58
6.2 Nonswitching electrical specifications...................................... 24
7.2.4
Voltage and current operating ratings..........................58
6.2.1
Voltage and current operating requirements................24
8
6.2.2
LVD and POR operating requirements........................25
8.1 Pinouts....................................................................................... 59
6.2.3
Voltage and current operating behaviors..................... 26
8.2 Signal Multiplexing and Pin Assignments................................ 60
6.2.4
Power mode transition operating behaviors.................27
6.2.5
Power consumption operating behaviors..................... 27
9.1 Obtaining package dimensions.................................................. 63
6.2.6
Diagram: Typical IDD_RUN operating behavior........32
10 Revision History.................................................................................63
6.2.7
Designing with radiated emissions in mind................. 33
9
Pin Diagrams and Pin Assignments................................................... 59
Package Information.......................................................................... 63
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
2
NXP Semiconductors
Introduction
The KW40Z/30Z/20Z (called KW40Z throughout this document) is an ultra low-power,
highly integrated single-chip device that enables Bluetooth low energy (BLE) or IEEE
Standard 802.15.4 RF connectivity for portable, extremely low-power embedded
systems. Applications include portable health care devices, wearable sports and fitness
devices, AV remote controls, computer keyboards and mice, gaming controllers, access
control, security systems, smart energy and home area networks.
The KW40Z SoC integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz
range supporting a range of FSK/GFSK and O-QPSK modulations, an ARM Cortex-M0+
CPU, 160 KB Flash and 20 KB SRAM, BLE Link Layer hardware, 802.15.4 packet
processor hardware and peripherals optimized to meet the requirements of the target
applications.
The KW40Z SoC’s radio frequency transceiver is compliant with Bluetooth version 4.1
for Low Energy (aka Bluetooth Smart), and the IEEE standard 802.15.4-2011 using OQPSK in the 2.4 GHz ISM band.
The KW40Z SoC can be used in applications as a "BlackBox" modem by simply adding
BLE or IEEE Std. 802.15.4 connectivity to an existing embedded controller system, or
used as a stand-alone smart wireless sensor with embedded application where no host
controller is required.
NXP provides fully certified protocol stacks and application profiles to support KW40Z.
The KW40Z Flash and SRAM memory are available for applications and communication
protocols using a choice of NXP or 3rd party software development tools.
The RF section of the KW40Z SoC is optimized to require very few external
components, achieving the smallest RF footprint possible on a printed circuit board.
Extremely long battery life is achieved though efficiency of code execution in the CortexM0+ CPU core and the multiple low power operating modes of the KW40Z SoC.
Additionally, an integrated DC-DC converter enables a wide operating range from 0.9 V
to 3.6 V. The DC-DC in Buck mode enables KW40Z to operate from a single coin cell
battery with a significant reduction of peak Rx and Tx current consumption. The DC-DC
in boost mode enables a single alkaline battery to be used throughout its entire useful
voltage range of 0.9 V to 1.795 V.
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
3
Ordering information
1 Ordering information
Table 1. Orderable parts details
Device
Operating Temp
Range (TA)
Package
Description
MKW20Z160VHT4(R)
-40 to 85°C
48-pin Laminate
QFN
IEEE 802.15.4
MKW30Z160VHM4(R)
-40 to 85°C
32-pin Laminate
QFN
Bluetooth Low Energy Only
MKW40Z160VHT4(R)
-40 to 85°C
48-pin Laminate
QFN
Bluetooth Low Energy or IEEE 802.15.4
2 Feature Descriptions
This section provides a simplified block diagram and highlights the KW40Z SoC
features.
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
4
NXP Semiconductors
Feature Descriptions
2.1 Block diagram
Figure 1. KW40Z/KW30Z/KW20Z simplified block diagram
2.2 Radio features
Operating frequencies:
• 2.4 GHz ISM band (2400-2483.5 MHz)
• MBAN 2360-2400 MHz
Supported standards:
•
•
•
•
Bluetooth v4.1 Low Energy compliant 1 Mbps GFSK modulation
IEEE Std. 802.15.4-2011 compliant O-QPSK modulation
NXP Thread Networking Stack
Bluetooth Low Energy(BLE) Application Profiles
Receiver performance:
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
5
Feature Descriptions
• Receive sensitivity of -91 dBm for BLE
• Receive sensitivity of -102 dBm typical for IEEE Std. 802.15.4
Other features:
• Programmable transmit output power from -18 dBm to +5 dBm with DC/DC bypass
and buck modes of operation
• Bluetooth Low Energy Link Layer hardware
• Hardware acceleration for IEEE Std. 802.15.4 packet processing
• 32 MHz crystal reference oscillator
• Supports antenna diversity option for IEEE Std. 802.15.4
• Supports dual PAN for IEEE Std. 802.15.4 with hardware-assisted address matching
acceleration
• Differential RF port shared by transmit and receive
• Low external component count
• Supports transceiver range extension using external PA and/or LNA
2.3 Microcontroller features
ARM Cortex-M0+ CPU
• Up to 48 MHz CPU
• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline
microarchitecture for reduced power consumption and improved architectural
performance (cycles per instruction)
• Supports up to 32 interrupt request sources
• Binary compatible instruction set architecture with the Cortex-M0 core
• Thumb instruction set combines high code density with 32-bit performance
• Serial Wire Debug (SWD) reduces the number of pins required for debugging
• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using
system RAM as the destination memory
Nested Vectored Interrupt Controller (NVIC)
• 32 vectored interrupts, 4 programmable priority levels
• Includes a single non-maskable interrupt
Wake-up Interrupt Controller (WIC)
• Supports interrupt handling when system clocking is disabled in low power modes
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
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NXP Semiconductors
Feature Descriptions
• Takes over and emulates the NVIC behavior when correctly primed by the NVIC on
entry to very-deep-sleep
• A rudimentary interrupt masking system with no prioritization logic signals for
wake-up as soon as a non-masked interrupt is detected
Debug Controller
•
•
•
•
Two-wire Serial Wire Debug (SWD) interface
Hardware breakpoint unit for 2 code addresses
Hardware watchpoint unit for 2 data items
Micro Trace Buffer for program tracing
On-Chip Memory
• 160 KB Flash
• Firmware distribution protection. Flash can be marked execute-only on a persector (4KB) basis to prevent firmware contents from being read by 3rd parties
• Flash implemented as one 128 KB block and one 32 KB block. Code can
execute or read from one block while the other block is being erased or
programmed
• 20 KB SRAM
• Security circuitry to prevent unauthorized access to RAM and flash contents through
the debugger
2.4 System features
Power Management Control Unit (PMC)
•
•
•
•
•
•
•
•
•
•
Programmable power saving modes
Available wake-up from power saving modes via internal and external sources
Integrated Power-on Reset (POR)
Integrated Low Voltage Detect (LVD) with reset (brownout) capability
Selectable LVD trip points
Programmable Low Voltage Warning (LVW) interrupt capability
Individual peripheral clocks can be gated off to reduce current consumption
Internal Buffered bandgap reference voltage
Factory programmed trim for bandgap and LVD
1 kHz Low Power Oscillator (LPO)
DC-DC Converter
• Internal switch mode power supply supporting Buck, Boost, and Bypass operating
modes
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
7
Feature Descriptions
• Buck operation supports external voltage sources of 2.1 V to 3.6 V. This reduces
peak current consumption during Rx and Tx by ~25%, ideal for single coin-cell
battery operation (typical CR2032 cell).
• Boost operation supports external voltage sources of 0.9 V to 1.795 V, which is
efficiently increased to the static internal core voltage level, ideal for single battery
operation (typical AA or AAA alkaline cell).
• When DCDC is not used, the device supports an external voltage range of 1.45 V to
3.6 V (1.45 - 3.6 V on VDD_RF1, VDD_RF2, VDD_XTAL and
VDD_1P45OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1 and VDDA pins)
• An external inductor is required to support the Buck or Boost modes
• The DCDC Converter 1.8 V output current drive for external devices (MCU in RUN
mode, Radio is enabled, other peripherals are disabled)
• Up to 44 mA in buck mode with VDD_1P8 = 1.8 V
• Up to 31.4 mA in buck mode with VDD_1P8 = 3.0 V
DMA Controller
• Four independently programmable DMA controller channels provides the means to
directly transfer data between system memory and I/O peripherals
• DMA controller is capable of functioning in run and wait modes of operation
• Dual-address transfers via 32-bit master connection to the system bus
• Data transfers in 8-, 16-, or 32-bit blocks
• Continuous-mode or cycle-steal transfers from software or peripheral initiation
DMA Channel Multiplexer (DMA MUX)
• 4 independently selectable DMA channel routers
• 2 periodic trigger sources available
• Each channel router can be assigned to 1 of the peripheral DMA sources
COP Watchdog Module
• Independent clock source input (independent from CPU/bus clock)
• Choice between two clock sources
• LPO oscillator
• Bus clock
System Clocks
• 32 MHz crystal reference oscillator provides clock for the radio, and is the main
clock option for the MCU
• 32.768 kHz crystal reference oscillator used to maintain precise Bluetooth radio time
in low power modes
• Multipurpose Clock Generator (MCG)
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
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NXP Semiconductors
Feature Descriptions
• Internal reference clocks — Can be used as a clock source for other on-chip
peripherals
• On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy
across full temperature range
• On-chip 4MHz oscillator with 5% accuracy across full temperature range
• Frequency-locked loop (FLL) controlled by internal or external reference
• 20 MHz to 48 MHz FLL output
Unique Identifiers
• 10 bytes of the Unique ID represents a unique identifier for each chip
• 40 bits of unique MAC address can be used to generate BLE or 802.15.4 device
address
2.5 Peripheral features
16-bit Analog-to-Digital Converter (ADC)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Linear successive approximation algorithm with 16-bit resolution
Output formatted in 16-, 12-, 10-, or 8-bit right justified format
Single or continuous conversion
Configurable sample time and conversion speed / power
Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
Input clock selection
Operation in low power modes for lower noise operation
Asynchronous clock source for lower noise operation
Selectable asynchronous hardware conversion trigger
Automatic compare with interrupt for less-than, or greater than, or equal to
programmable value
Temperature sensor
Battery voltage measurement
Hardware average function
Selectable voltage reverence
Self-calibration mode
12-Bit Digital-to-Analog Converter (DAC)
• 12-bit resolution
• Guaranteed 6-sigma monotonicity over input word
• High- and low-speed conversions
• 1 μs conversion rate for high speed, 2 μs for low speed
• Power-down mode
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
9
Feature Descriptions
• Automatic mode allows the DAC to generate its own output waveforms including
square, triangle, and sawtooth
• Automatic mode allows programmable period, update rate, and range
• DMA support with configurable watermark level
High-Speed Analog Comparator (CMP)
• 6-bit DAC programmable reference generator output
• Up to eight selectable comparator inputs; each input can be compared with any input
by any polarity sequence
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of
comparator output
• Two performance modes:
• Shorter propagation delay at the expense of higher power
• Low power, with longer propagation delay
• Operational in all MCU power modes
Low Power Timer (LPTMR)
• One channel
• Operation as timer or pulse counter
• Selectable clock for prescaler/glitch filter
• 1 kHz internal LPO
• External low power crystal oscillator
• Internal reference clock
• Configurable glitch filter or prescaler
• Interrupt generated on timer compare
• Hardware trigger generated on timer compare
• Functional in all power modes
Timer/PWM (TPM)
•
•
•
•
•
•
•
•
•
TPM0: 4 channels, TPM1 and TPM2: 2 channels each
Selectable source clock
Programmable prescaler
16-bit counter supporting free-running or initial/final value, and counting is up or updown
Input capture, output compare, and edge-aligned and center-aligned PWM modes
Input capture and output compare modes
Generation of hardware triggers
TPM1 and TPM2: Quadrature decoder with input filters
Global time base mode shares single time base across multiple TPM instances
Programmable Interrupt Timer (PIT)
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
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NXP Semiconductors
Feature Descriptions
• Up to 2 interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by system clock frequency
Real-Time Clock (RTC)
• 32-bit seconds counter with 32-bit alarm
• Can be invalidated on detection of tamper detect
• 16-bit prescaler with compensation
• Register write protection
• Hard Lock requires MCU POR to enable write access
• Soft lock requires system reset to enable write/read access
• Capable of waking up the system from low power modes
Inter-Integrated Circuit (I2C)
•
•
•
•
•
•
•
•
•
•
•
Two channels
Compatible with I2C bus standard and SMBus Specification Version 2 features
Up to 1 Mbps operation
Multi-master operation
Software programmable for one of 64 different serial clock frequencies
Programmable slave address and glitch input filter
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Bus busy detection broadcast and 10-bit address extension
Address matching causes wake-up when processor is in low power mode
LPUART
•
•
•
•
•
•
•
•
•
•
•
•
One channel
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
13-bit baud rate selection with fractional divide of 32
Programmable 8-bit or 9-bit data format
Programmable 1 or 2 stop bits
Separately enabled transmitter and receiver
Programmable transmitter output polarity
Programmable receive input polarity
13-bit break character option
11-bit break character detection option
Two receiver wakeup methods:
• Idle line wakeup
• Address mark wakeup
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
11
Feature Descriptions
•
•
•
•
•
•
•
•
Address match feature in receiver to reduce address mark wakeup ISR overhead
Interrupt or DMA driven operation
Receiver framing error detection
Hardware parity generation and checking
Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection
Operation in low power modes
Hardware Flow Control RTS\CTS
Functional in Stop/VLPS modes
Serial Peripheral Interface (DSPI)
•
•
•
•
•
•
•
•
•
•
Two independent SPI channels
Master and slave mode
Full-duplex, three-wire synchronous transfers
Programmable transmit bit rate
Double-buffered transmit and receive data registers
Serial clock phase and polarity options
Slave select output
Control of SPI operation during wait mode
Selectable MSB-first or LSB-first shifting
Support for both transmit and receive by DMA
Carrier Modulator Timer (CMT)
• Four modes of operation
• Time; with independent control of high and low times
• Baseband
• Frequency shift key (FSK)
• Direct software control of CMT_IRO signal
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divider
• Interrupt on end of cycle
• Ability to disable CMT_IRO signal and use as timer interrupt
General Purpose Input/Output (GPIO)
•
•
•
•
Hysteresis and configurable pull up device on all input pins
Independent pin value register to read logic level on digital pin
All GPIO pins can generate IRQ and wakeup events
Configurable drive strength on some output pins
Touch Sensor Input (TSI)
• Support up to 16 external electrodes
• Automatic detection of electrode capacitance across all operational power modes
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
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Transceiver Description
•
•
•
•
•
•
•
•
Internal reference oscillator for high-accuracy measurement
Configurable software or hardware scan trigger
Fully support NXP touch sensing software (TSS) library
Capability to wake MCU from low power modes
Compensate for temperature and supply voltage variations
High sensitivity change with 16-bit resolution register
Configurable up to 4096 scan times
Support DMA data transfer
Keyboard Interface
• GPIO can be configured to function as a interrupt driven keyboard scanning matrix
• In the 48pin package there are a total of 28 digital pins
• In the 32pin package there are a total of 15 digital pins
• These pins can be configured as needed by the application as GPIO, UART, SPI,
I2C, ADC, timer I/O as well as other functions
AES Accelerator (AESA)
• The Advanced Encryption Standard Accelerator (AESA) is a stand-alone symmetric
encryption accelerator supporting 128- bit key and data size and the following
modes:
• Electronic Codebook (ECB)
• Cipher Block Chaining (CBC)
• Counter (CTR)
• CTR & CBC-MAC (CCM and CCM*)
• Cipher-base MAC (CMAC)
• Extended Cipher Block Chaining Message Authentication Code (XCBC-MAC)
• The AESA supports all BLE and IEEE 802.15.4 packet sizes
• The AESA supports DMA and interrupt-driven operation
True Random Number Generator (TRNG)
• The TRNG is an entropy source
• The TRNG output is intended to be read and used as an input to a deterministic
random number generator
• The deterministic random number general will be implemented in software
• A FIPS 180 compliant solution can be realized using the TRNG together with a FIPS
compliant determinstic random number generator and SoC-level security
3 Transceiver Description
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
13
Transceiver Description
•
•
•
•
•
Direction Conversion Receiver
Constant Envelope Transmitter
2.36 GHz to 2.483 GHz PLL Range
Low Transmit and Receive Current Consumption
Low BOM
3.1 Key Specifications
The KW40Z SoC meets or exceeds all Bluetooth Low Energy v4.1 and IEEE 802.15.4
performance specifications applicable to 2.4 GHz ISM and MBAN (Medical Band Area
Network) bands. Key specification for the KW40Z are:
Frequency Band:
• ISM Band: 2400 to 2483.5 MHz
• MBAN Band: 2360 to 2400 MHz
Bluetooth Low Energy v4.1 modulation scheme:
•
•
•
•
Symbol rate: 1000 kbps
Modulation: GFSK
Receiver sensitivity: -91 dBm, typical
Programmable transmitter output power: -18 dBm to +5 dBm
IEEE Standard 802.15.4 2.4 GHz modulation scheme:
•
•
•
•
•
•
•
Chip rate: 2000 kbps
Data rate: 250 kbps
Symbol rate: 62.5 kbps
Modulation: OQPSK
Receiver sensitivity: -102 dBm, typical (@1% PER for 20 byte payload packet)
Differential bidirectional RF input/output port with integrated transmit/receive switch
Programmable transmitter output power: -18 dBm to +5 dBm
3.2 Frequency Plan for Bluetooth Low Energy
This section describes the frequency plan / channels associated with 2.4GHz ISM and
MBAN bands for Bluetooth Low Energy.
2.4GHz ISM Channel numbering:
• Fc=2402 + K * 2 MHz, K=0,.........,39.
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
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NXP Semiconductors
Transceiver Description
MBAN Channel numbering:
• Fc=2363 + 5*K in MHz, for K=0,.....,6)
• Fc=2367 + 5*(K-7) in MHz, for K=7,8.....,13)
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Freq (MHz)
Channel
Freq (MHz)
Channel
Freq (MHz)
0
2402
0
2360
28
2390
1
2404
1
2361
29
2391
2
2406
2
2362
30
2392
3
2408
3
2363
31
2393
4
2410
4
2364
32
2394
5
2412
5
2365
33
2395
6
2414
6
2366
34
2396
7
2416
7
2367
35
2397
8
2418
8
2368
36
2398
9
2420
9
2369
0
2402
10
2422
10
2370
1
2404
11
2424
11
2371
2
2406
12
2426
12
2372
3
2408
13
2428
13
2373
4
2410
14
2430
14
2374
5
2412
15
2432
15
2375
6
2414
16
2434
16
2376
7
2416
17
2436
17
2377
8
2418
18
2438
18
2378
9
2420
19
2440
19
2379
10
2422
20
2442
20
2380
11
2424
21
2444
21
2381
12
2426
22
2446
22
2382
13
2428
23
2448
23
2383
14
2430
24
2450
24
2384
15
2432
25
2452
25
2385
16
2434
26
2454
26
2386
17
2436
27
2456
27
2387
18
2438
28
2458
28
2388
19
2440
29
2460
29
2389
20
2442
30
2462
30
2390
21
2444
31
2464
31
2391
22
2446
32
2466
32
2392
23
2448
Table continues on the next page...
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
15
Transceiver Description
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Freq (MHz)
Channel
Freq (MHz)
Channel
Freq (MHz)
33
2468
33
2393
24
2450
34
2470
34
2394
25
2452
35
2472
35
2395
26
2454
36
2474
36
2396
27
2456
37
2476
37
2397
37
2476
38
2478
38
2398
38
2478
39
2480
39
2399
39
2480
1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
2. Per FCC guideline rules, IEEE (R) 802.15.1 and Bluetooth Low Energy V4.0 single mode operation is allowed in these
channels.
3.3 Frequency Plan for 802.15.4 and 802.15.4j (MBAN)
This section describes the frequency plan / channels associated with 2.4GHz ISM and
MBAN bands for 802.15.4.
2.4GHz ISM Channel numbering:
• Fc=2402.0 + 5*(K-11) MHz, K=11, 12, ..,26.
MBAN Channel numbering:
• Fc=2363.0 + 5*K in MHz, for K=0,.....,6)
• Fc=2367.0 + 5*(K-7) in MHz, for K=7,.....,14)
Table 3. 2.4 GHz ISM and MBAN frequency plan and channel designations
MBAN1
2.4 GHz ISM
Channel #
Frequency (MHz)
Channel #
Frequency (MHz)
11
2405
0
2363
12
2410
1
2368
13
2415
2
2373
14
2420
3
2378
15
2425
4
2383
16
2430
5
2388
17
2435
6
2393
18
2440
7
2367
Table continues on the next page...
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
16
NXP Semiconductors
System and Power Management
Table 3. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
MBAN1
2.4 GHz ISM
Channel #
Frequency (MHz)
Channel #
Frequency (MHz)
19
2445
8
2372
20
2450
9
2377
21
2455
10
2382
22
2460
11
2387
23
2465
12
2392
24
2470
13
2397
25
2475
14
2395
26
2480
1. Usable channel spacing to assit in co-existence.
3.4 Transceiver Functions
Receive
• The receiver architecture is Zero IF (ZIF) where the received signal after passing
through RF front end is down-converted to a baseband signal. The signal is filtered
and amplified before it is fed to a sigma-delta analog-to-digital converter. The digital
signal is then decimated to a baseband clock frequency before it is digitally
processed, demodulated and passed on to packet processing.
Transmit
• The transmitter transmits O-QPSK or GFSK/FSK modulation having power and
channel selection adjustment per user application. After the channel of operation is
determined, coarse and fine tuning is executed within the Frac-N PLL to engage
signal lock. After signal lock is established, the modulated buffered signal is then
routed to a multi-stage amplifier for transmission. The differential signals at the
output of the PA (RF_P, RF_N) are converted as single ended (SE) signals with off
chip components as required.
4 System and Power Management
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
17
System and Power Management
4.1 Power Management
The KW40Z SoC includes internal power management features that can be used to
control the power usage. The power management of the KW40Z includes power
management controller (PMC) and a DCDC converter which can operate in a buck, boost
or bypass configuration. The PMC is designed such that the RF radio will remain in stateretention while the core is in various stop modes. It can make sure the device can stay in
low current consumption mode while the RF radio can wakeup quick enough for
communication.
4.1.1 DCDC Converter
The features of the DCDC converter include the following:
• Single inductor, multiple outputs
• Buck and boost modes (pin selectable; CFG=VDCDC_IN -> buck; CFG=GND ->
boost)
• Continuous or pulsed operation (hardware/software configurable)
• Power switch input to allow external control of power up, and to select bypass mode
• Output signal to indicate power stable. Purpose is for the rest of the chip to use as a
POR
• Scaled battery output voltage suitable for SAR ADC utilization
• Internal oscillator for support when the reference oscillator is not present
• 1.8V output is capable to supply external device: max 38.9mA (V1P8 = 1.8V,
VDCDC_IN = 3.0V) and 20.9mA (V1P8 = 3.0V, VDCDC_IN = 3.0V), with MCU in
RUN mode, peripherals are disabled
4.2 Modes of Operation
The ARM Cortex-M0+ core in the KW40Z SoC has three primary modes of operation:
Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop
mode. Wait modes are similar to ARM sleep modes. Stop modes are similar to ARM
deep sleep modes. The very low power run (VLPR) operation mode can drastically
reduce runtime power when the maximum bus frequency is note required to handle the
application needs.
The WFI instruction invokes both wait and stop modes for KW40Z. The primary modes
are augmented in a number of ways to provide lower power based on application needs.
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
18
NXP Semiconductors
System and Power Management
4.2.1 Power modes
The power management controller (PMC) provides multiple power options to allow the
user to optimize power consumption for the level of functionality needed.
Depending on the stop requirements of the user application, a variety of stop modes are
available that provide state retention, partial power down or full power down of certain
logic and/or memory. I/O states are held in all modes of operation. The following table
compares the various power modes available.
For each run mode there is a corresponding wait and stop mode. Wait modes are similar
to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode.
The very low power run (VLPR) operating mode can drastically reduce runtime power
when the maximum bus frequency is not required to handle the application needs.
The three primary modes of operation are run, wait and stop. The WFI instruction
invokes both wait and stop modes for the chip. The primary modes are augmented in a
number of ways to provide lower power based on application needs.
Table 4. Power modes (At 25 deg C)
Power mode
Description
Normal Run (all
peripherals clock off)
Allows maximum performance of chip.
CPU
recovery
method
Radio
—
Radio can be active
Normal Wait - via WFI Allows peripherals to function, while allowing CPU to
go to sleep reducing power.
Interrupt
Normal Stop - via WFI Places chip in static state. Lowest power mode that
retains all registers while maintaining LVD protection.
Interrupt
PStop2 (Partial Stop
2)
Core and system clocks are gated. Bus clock remains
active. Masters and slaves clocked by bus clock
reamin in Run or VLPRun mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
Interrupt
PStop1 (Partial Stop
1)
Core, system clocks and bus clock are gated. All bus
masters and slaves enter Stop mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
Interrupt
VLPR (Very Low
Power Run) (all
peripherals off)
Reduced frequency (1MHz) Flash access mode,
regulator in low power mode, LVD off. Internal
oscillator can provide low power 4 MHz source for
core. (Values @2MHz core/ 1MHz bus and flash,
module off, execution from flash).
—
Biasing is disabled when DCDC is configured for
continuous mode in VLPR/W
VLPW (Very Low
Similar to VLPR, with CPU in sleep to further reduce
Power Wait) - via WFI power. (Values @4MHz core/ 1MHz bus, module off)
(all peripherals off)
Biasing is disabled when DCDC is configured for
continous mode in VLPR/W
Radio operation is possible
only when DCDC is
configured for continuous
mode.1 However, there may
be insufficient MIPS with a
4MHz MCU to support much
in the way of radio operation.
Interrupt
Table continues on the next page...
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
19
System and Power Management
Table 4. Power modes (At 25 deg C) (continued)
Power mode
Description
CPU
recovery
method
VLPS (Very Low
Power Stop) via WFI
Places MCU in static state with LVD operation off.
Lowest power mode with ADC and all pin interrupts
functional. LPTMR, RTC, CMP, TSI can be
operational.
Interrupt
Radio
Biasing is disabled when DCDC is configured for
continuous mode in VLPS
LLS3 (Low Leakage
Stop)
State retention power mode. LLWU, LPTMR, RTC,
CMP, TSI can be operational. All of the radio Sea of
Gates(SOG) logic is in state retention
Wakeup
Interrupt
LLS2 (Low Leakage
Stop)
State retention power mode. LLWU, LPTMR, RTC,
CMP, TSI can be operational. Only 4KBytes of RAM
retained.All of the radio SOG logic is in state retention
Wakeup
Interrupt
VLLS3 (Very Low
Leakage Stop3)
Full SRAM retention. LLWU, LPTMR, RTC, CMP, TSI
can be operational. All of the radio SOG logic is in
state retention
Wakeup
Reset
VLLS2 (Very Low
Leakage Stop2)
Partial SRAM retention. 4KBytes of RAM retained.
LLWU, LPTMR, RTC, CMP, TSI can be
operational.All of the radio SOG logic is in state
retention
Wakeup
Reset
VLLS1 (Very Low
Leakage Stop1) with
RTC + 32kHz OSC
All SRAM powered off. The 32-byte system register
file remains powered for customer-critical data.
LLWU, LPTMR, RTC, CMP can be operational. Radio
logic is power gated.
Wakeup
Reset
VLLS1 (Very Low
Leakage Stop1) with
LPTMR + LPO
All SRAM powered off. The 32-byte system register
file remains powered for customer-critical data.
LLWU, LPTMR, RTC, CMP, TSI can be operational.
Wakeup
Reset
VLLS0 (Very Low
Leakage Stop0) with
Brown-out Detection
VLLS0 is not supported with DCDC
Wakeup
Reset
VLLS0 (Very Low
Leakage Stop0)
VLLS0 is not supported with DCDC buck/boost
configuration but is supported with bypass
configuration
The 32-byte system register file remains powered for
customer-critical data. Disable all analog modules in
PMC and retains I/O state and DGO state. LPO
disabled, POR brown-out detection enabled, Pin
interrupt only. Radio logic is power gated.
Radio SOG is in state
retention in LLSx. The BTLL
DSM2 logic can be active
using the 32kHz clock
Radio SOG is in state
retention in VLLS3/2. The
BTLL DSM logic can be active
using the 32kHz clock
Radio operation not
supported. The Radio SOG is
power-gated in VLLS1/0.
Radio state is lost at VLLS1
and lower power states
Radio operation not
supported. The Radio digital
is power-gated in VLLS1/0
Wakeup
Reset
The 32-byte system register file remains powered for
customer-critical data. Disable all analog modules in
PMC and retains I/O state and DGO state. LPO
disabled, POR brown-out detection disabled, Pin
interrupt only. Radio logic is power gated.
1. Biasing is disabled, but the Flash is in a low power mode for VLPx, so this configuration can realize some power savings
over use of Run/Wait/Stop
2. DSM refers to BTLL's deepsleep mode. DSM does not refer to the ARM sleep deep mode.
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
20
NXP Semiconductors
Transceiver Electrical Characteristics
5 Transceiver Electrical Characteristics
5.1 Recommended radio operating conditions
Table 5. Recommended operating conditions
Characteristic
Symbol
Min
Typ
Max
Unit
VDDRF1, VDDRF2,
VDDXTAL
1.45
2.7
3.6
Vdc
Input Frequency
fin
2.360
—
2.480
GHz
Ambient Temperature Range
TA
-40
25
85
°C
Logic Input Voltage Low
VIL
0
—
30%
VDDINT
V
RF and Analog Power Supply Voltage
1
Logic Input Voltage High
VIH
70%
VDDINT
—
VDDINT
SPI Clock Rate
fSPI
—
—
16.0
MHz
RF Input Power
Pmax
—
—
0
dBm
Crystal Reference Oscillator Frequency (±40 ppm over
operating conditions to meet the 802.15.4 Standard.)
fref
V
32 MHz only
1. VDDINT is the internal LDO regulated voltage supplying various circuit blocks, VDDINT=1.2 V
5.2 Receiver Feature Summary
Table 6. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise
noted)
Characteristic1
Symbol
Min.
Typ.
Max.
Supply current power down on VDD_RFx supplies
Ipdn
—
200
1000
nA
Supply current Rx On with DC-DC converter enable
(Buck; Vbat = 3.6V)
IRxon
—
6.5
—
mA
Supply current Rx On with DC-DC converter disabled
(Bypass) 2
IRxon
—
15.4
—
mA
fin
2.360
—
2.4835
GHz
Input RF Frequency
BLE Rx Sensitivity
3
IEEE 802.15.4 Rx Sensitivity 4
Noise Figure for max gain mode @ typical sensitivity
Receiver Signal Strength Indicator Range
Receiver Signal Strength Indicator Resolution
Unit
SENSBLE
—
-91
—
dBm
SENS15.4
—
-102
—
dBm
NFHG
—
6.5
—
dB
RSSIRange
-96
—
0
dBm
RSSIRes
—
1
—
dB
Table continues on the next page...
MKW40Z/30Z/20Z Data Sheet, Rev. 1.2, 05/2018
NXP Semiconductors
21
Transceiver Electrical Characteristics
Table 6. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
BLE Co-channel Interference (Wanted signal at -67 dBm ,
BER
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