MM908E622ACPEK

Freescale Semiconductor Technical Data Document Number: MM908E622 Rev. 3.0, 4/2012 Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror 908E622 QUAD HALF-BRIDGE, TRIPLE HIGH SIDE SWITCH AND EC GLASS CIRCUITRY WITH EMBEDDED MCU AND LIN The 908E622 is an integrated single package solution that includes a high-performance HC08 microcontroller with a SMARTMOS analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), a 10 bit analog-to-digital converter (ADC), internal serial peripheral interface (SPI), and an internal clock generator module (ICG). The analog control die provides four halfbridge and three high side outputs with diagnostic functions, an EC glass driver circuit, a Hall effect sensor input, analog inputs, voltage regulator, window watchdog, and local interconnect network (LIN) physical layer. The single package solution, together with LIN, provides optimal application performance adjustments and space saving PCB design. It is well-suited for the control of automotive high-end mirrors. EK SUFFIX 98ASA10712D 54-PIN SOICW-EP Features • • • • • • • • • • • High performance M68HC908EY16 core 16 KB of on-chip flash memory, 512 B of RAM Two 16-bit, two-channel timers LIN physical layer interface Autonomous MCU watchdog / MCU supervision One analog input with switchable current source Four low RDS(ON) half-bridge outputs Three low RDS(ON) high side outputs EC glass driver circuitry Wake-up and 2 or 3-pin Hall effect sensor input 12 microcontroller I / Os ORDERING INFORMATION Device (Add an R2 suffix for Tape and reel orders) Temperature Range (TA) Package MM908E622ACPEK - 40 to 85 °C 54 SOICW-EP VSP1:8] LIN L0 VDDA/VREFH EVDD 4.7 μF HB1 VDD 100 nF VSSA/VREFL HB2 EVSS VSS HB3 RST A RST HB4 IRQ A HS1 IRQ HS2 PTA0/BD0 HS3 PTA1/KBD1 μC PortA PTA2/KBD2 HS1 PTA3/KBD3 PTA4/KBD4 ECR PTB3/AD3 EC μC PortB PTB4/AD4 HVDD PTB5/AD5 A0 PTC2/MCLK A0CST μC PortC PTC3/OSC2 PTC4/OSC1 H0 Internally Connected PTD0/TACH0 μC PortD TESTMODE PTD1/TACH1 GND[1:4] EP μC PortE Internally Connected PTE1/RXD 908E622 >22 μF Wake-up Input M M 4 x Half-bridge Outputs M High Side Output 1 High Side Output 2 High Side Output 3 High Side Output 1 EC - Glass Control Switched 5.0 V Output Analog Input with Current Source Analog Input Current Source Trim Two 3-pin Hall Sensor Input Pull to GND for User Mode Figure 1. 908E622 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2005-2012. All rights reserved. 100 nF 2 DDRA PORT A SPSCK PTA5/SPSCK PTB0/AD0 MOSI PTC1/MOSI ADOUT MISO SS PWM PTC0/MISO PTA6/SS PTD0/TACH0 TXD PTE0/TXD IRQ_A PORT D PORT E DDRD DDRE Analog Multiplexer SPI & CONTROL Autonomous Watchdog Reset Control LIN Physical Layer Figure 2. 908E622 Simplified Internal Block Diagram PTE0/TXD PTE1/RXD PTD0/TACH0 PTD1/TACH1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO BEMF Module Prescaler Module Arbiter Module Periodic Wake-up Timebase Module Configuration Register Module Serial Peripheral Interface Module Computer Operating Properly Module Enhanced Serial Communication Interface Module 2-channel Timer Interface Module B PORT C DDRC FLSVPP PTD1/TACH1 Security Module Power-ON Reset Module RST PTC4/OSC1 Single External IRQ Module VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS IRQ 24 Internal System Integration Module PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 VDDA/VREFH PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 PTA4/KBD4 RST OSC2 Internal Clock OSC1 Generator Module User Flash Vector Space, 36 Bytes IRQ PTA3/KBD3 EVDD 2-channel Timer Interface Module A PTE1/RXD RXD PTD0/TACH0 PTE1/RXD RST_A PTA2/KBD2 EVSS 5-Bit Keyboard Interrupt Module LIN PTA1/KBD1 PTA0/KBD0 VSSA/VREFL VSS A0 A0CST H0 Hallport EC ECR HB4 HB3 HB2 HB1 Analog Port with Current Source EC glass Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic HS3 HS2 High Side Driver & Diagnostic High Side Driver & Diagnostic HS1[a:b] L0 HVDD VDD High Side Driver & Diagnostic Wakeup Port Switched VDD Driver & Diagnostic Voltage Regulator VSUP[1:8] Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), 1024 Bytes Single Breakpoint Break Module GND[1:4] M68HC08 CPU CPU ALU Registers INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM TESTMODE Internal Bus DDRB PORT B 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS Transparent Top View of Package PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 1 54 2 53 3 52 4 51 5 50 6 49 IRQ RST 7 48 8 47 (PTD0/TACH0/BEMF -> PWM) PTD1/TACH1 9 46 10 45 RST_A IRQ_A 11 44 12 43 LIN A0CST A0 GND1 HB4 VSUP1 GND2 HB3 VSUP2 EC ECR TESTMODE GND3 HB2 VSUP3 13 14 15 42 Exposed Pad 41 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VDDA/VREFH EVDD EVSS VSSA/VREFL (PTE1/RXD PWM) PWM signal This pin is an asynchronous external interrupt input pin. This pin is bi-directional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin is the PWM signal test pin. It internally connects the MCU PTD0/TACH0 pin with the Analog die PWM input. Note: Do not connect in the application. MCU 10 PTD1/TACH1 Port D I /Os This pin is a special function, bi-directional I /O port pin that is shared with other functional modules in the MCU. 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 20. Die Pin Pin Name Formal Name Definition MCU / Analog 44 (PTE1/ RXD 20 V VDDRUN2 4.75 5.0 5.25 IOUTRUN – 120 150 mA VLR – – 100 mV STOP Mode Output Voltage(13) VDDSTOP 4.75 5.0 5.25 V STOP Mode Total Output Current IOUTSTOP 150 500 1100 μA SYSTEM RESETS AND INTERRUPTS Low Voltage Reset (LVR) Low Voltage Interrupt (LVI) V High Voltage Interrupt (HVI) V High Temperature Interrupt (HTI)(11) Threshold TJ Hysteresis °C High Temperature Reset (HTR)(11) Threshold TJ Hysteresis °C VOLTAGE REGULATOR(12) Normal Mode Output Voltage(13) Normal Mode Total Output Current Load Regulation - IOUT = 60 mA, VSUP = 9.0 V, TJ = 125 °C V Notes 11. This parameter is guaranteed by process monitoring but is not production tested. 12. Specification with external low ESR ceramic capacitor 1.0 μF< C < 4.7 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Its not recommended to use capacitor values above 4.7 μF 13. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Recessive State, TXD HIGH, IOUT = 1.0 μA V LIN_REC VSUP -1 — — Dominant State, TXD LOW, 500 Ω External Pull-up Resistor V LIN_DOM — — 1.4 Normal Mode Pull-up Resistor to VSUP R PU 20 30 47 kΩ Stop, Sleep Mode Pull-up Current Source IPU — 20 — μA Output Current Shutdown Threshold IBLIM 100 230 280 mA Output Current Shutdown Timing IBLS 5.0 – 40 µs LIN PHYSICAL LAYER LIN Transceiver Output Voltage V Leakage Current to GND VSUP Disconnected, VBUS at 18 V IBUS – 1.0 10 µA Recessive state, 8.0 V ≤ VSUP ≤ 18 V, 8.0 V ≤ VBUS ≤ 18 V, VBUS ≥ VSUP IBUS-PAS-REC 0.0 3.0 20 µA GND Disconnected, VGND = VSUP, VBUS at -18 V IBUS-NOGND -1.0 – 1.0 mA Receiver Threshold Dominant VBUS_DOM – – 0.4 Receiver Threshold Recessive VBUS_REC 0.6 – – VBUS_CNT 0.475 0.5 0.525 VBUS_HYS – – 0.175 RDS(ON)-HS1 – 185 225 IHSOC1 6.0 – 9.0 A tOCB – 4-8 – µs CRRATIOHS1 0.84 1.2 1.56 V/A fPWMHS – – 25 kHz VHSF – 0.9 – V ILeakHS – P0 = 0. The parity bit is only evaluated during write operations and ignored for read operations. Master Address Byte A4 - A0 Bit X includes the address of the desired register. not used R/W Master Data Byte includes the information if it is a read or a write operation. • If R/W = 1 (read operation), second byte of master contains no valid information, slave just transmits back register data. • If R/W = 0 (write operation), master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to write operation, write data is latched in the SMARTMOS registers on rising edge of SS. This byte includes data to be written or no valid data during a read operation. Slave Status Byte This byte always includes the contents of the system status register ($0C), independent if it is a write or read operation, or which register was selected. Slave Data Byte This byte includes the contents of selected register, during write operation in includes the register content prior to write operation. SPI REGISTER OVERVIEW Table 13 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER. Table 13. SPI Register Overview Addr Register Name R/W $00 System Control (SYSCTL) R $01 $02 $03 $04 $05 $06 $07 Half-bridge Output (HBOUT) High Side Output (HSOUT) Half-bridge Status and Control (HBSCTL) High Side Status and Control (HSSCTL) EC Status and Control (ECSCTL) EC Digital to Analog Control (ECDACC) H0/L0 Status and Control (HLSCTL) Bit 7 6 5 4 3 2 1 0 PSON 0 0 HTIS1 HTIS0 VIS SRS1 SRS0 STOP SLEEP HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L HVDDON 0 HS3PWM HS2PWM HS1PWM HS3ON HS2ON HS1ON CRM 0 0 0 HB4OCF HB3OCF HB2OCF HB1OCF HVDDOCF 0 0 0 0 HS3OCF HS2OCF HS1OCF ECON ECOLT ECRON 0 0 0 ECOCF ECOLF 0 0 ECDAC5 ECDAC4 ECDAC3 ECDAC2 ECDAC1 ECDAC0 L0F 0 0 H0OCF H0F H0EN H0PD H0MS W R W R W R W R W R W R W R W 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 47 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 13. SPI Register Overview $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 A0 and Multiplexer Control (A0MUCTL) Interrupt Mask (IMR) Interrupt Flag (IFR) Watchdog Control (WDCTL) System Status (SYSSTAT) Reset Status (RSR) System Test (SYSTEST) System Trim 1 (SYSTRIM1) System Trim 2 (SYSTRIM2) System Trim 3 (SYSTRIM3) R CSON CSSEL1 CSSEL0 CSA SS3 SS2 SS1 SS0 L0IE H0IE LINIE HTRD HTIE LVIE HVIE PSFIE L0IF H0IF LINIF 0 HTIF LVIF HVIF PSFIF WDRE WDP1 WDP0 0 0 0 0 0 W R W R W R WDRST W R LINCL HTIF VF H0F HVDDF HSF HBF ECF POR PINR WDR HTR LVR 0 LINWF L0WF W R W R reserved W R HVDDT1 HVDDT0 reserved reserved itrim3 itrim2 itrim1 itrim0 0 0 0 0 0 0 0 0 CRHB5 CRHB4 CRHB3 CRHB2 CRHB1 CRHB0 0 0 0 0 0 0 CRHS5 CRHS4 CRHS3 CRHS2 CRHS1 CRHS0 W R W R W CRHBHC1 CRHBHC0 0 0 CRHBHC3 CRHBHC2 Factory TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E622, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” ($FF) state: • $FD80:$FDDF Trim and Calibration Values • $FFFE :$FFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values The usage of the trim values located in the flash memory is explained by the following. Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller, without using any external components. The untrimmed frequency of the low frequency base clock (IBASE) will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate these dependencies, a ICG trim value is located at address $FDC2. After trimming, the ICG is in a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100 nF), and stabilized (4.7 μF) VDD = 5.0 V, TAMBIENT~25°C), and will vary over temperature and voltage (VDD), as indicated in the 68HC908EY16 datasheet. To trim the ICG, this value has to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to copied after every reset. Watchdog Period Range Value (AWD Trim) The window watchdog supervises device recovery (e.g. from code runaways). The application software has to clear the watchdog within the open window. Due to the high variation of the watchdog period, and therefore the reduced width of the watchdog window, a value is stored at address $FDCF. This value classifies the watchdog period into 3 ranges (Range 0, 1, 2). It allows the application software to select one of three time intervals to clear the watchdog based on the stored value. The classification is done in a way that the application software can have up to ±19% variation of the of optimal clear interval, e.g. caused by ICG variation. Effective Open Window Having a variation in the watchdog period in conjunction with a 50% open window, results in an effective open window, which can be calculated by: latest window open time: t_open = t_wd max / 2 earliest window closed time: t_closed = t_wd min 908E622 48 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Optimal Clear Interval t_opt = t_open + (t_open+t_closed) / 2 See Table 14 to select the optimal clear interval for the watchdog based on the Window No. and chosen period. The optimal clear interval, meaning the clear interval with the biggest possible variation to latest window open time, and to the earliest window closed time, can be calculated with the following formula: Table 14. Window Clear Interval Window Period Select Range bits Watchdog Period t_wd Effective Open Window Optimal Clear Interval $FDCF WDP1:0 min. max. Unit t_open t_closed Unit t_opt Unit max. variation 0 00 68 92 ms 46 68 ms 57 ms ±19.3% 01 34 46 23 34 28.5 10 17 23 11.5 17 14.25 11 8.5 11.5 5.75 8.5 7.125 00 92 124 62 92 ms ±19.5% 01 46 62 31 46 38.5 10 23 31 15.5 23 19.25 11 11.5 15.5 7.75 11.5 9.625 00 52 68 34 52 ms ±20.9% 01 26 34 17 26 21.5 10 13 17 8.5 13 10.75 11 6.5 8.5 4.25 6.5 5.375 1 2 ms ms Analog Die System Trim Values For improved application performance, and to ensure the outlined datasheet values, the analog die needs to be trimmed. For this purpose, 3 trim values are stored in the Flash memory at addresses $FDC4 - $FDC6. These values have to be copied into the analog die SPI registers: • copy $FDC4 into SYSTRIM1 register $0F • copy $FDC5 into SYSTRIM2 register $10 • copy $FDC6 into SYSTRIM3 register $11 Note: These values have to be copied to the respective SPI register after a reset, to ensure proper trimming of the device. Register Name and Address: SYSTEST - $0E Write Reset 77 ms 43 The System Test Register is reserved for production testing and is not allowed to be written into. System Trim Register 1 (SYSTRIM1) Register Name and Address: IBIAS - $0F Read Write Reset Bit7 6 HVD DT1 HVD DT0 0 0 5 4 3 2 1 Bit0 ITRI M3 ITRI M2 ITRI M1 ITRI M0 0 0 0 0 0 0 reser ved reser ved 0 0 Note: do not change (set) the reserved bits System Test Register (SYSTEST) Read ms HVDDT1:0 - HVDD Over-current Shutdown Delay Bits Bit7 6 5 4 3 2 1 Bit0 reser ved reser ved reser ved reser ved reser ved reser ved reser ved reser ved 0 0 0 0 0 0 0 0 These read/write bits allow changing the filter time (for capacitive load) for the HVDD over-current detection. Reset clears the HVDDT1:0 bits an sets the delay to the maximum value. Note: do not write to the reserved bits 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 49 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 15. HVDD Over-current Shutdown Selection Bits Table 17. Current Recopy Trim for HB1:2 (CSA=0) HVDDT1 HVDDT0 typical Delay CRHBHC1 CRHBHC0 Adjustment 0 0 950μs 0 0 0 0 1 536μs 0 1 -10% 1 0 234μs 1 0 5% 1 1 78μs 1 1 10% ITRIM3:0 - IRef Trim Bits CRHB5:3 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming the internal current references IRef (also A0, A0CST). The provided trim values have to be copied into these bits after every reset. Reset clears the ITRIM3:0 bits. Table 16. IRef Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB3 and HB4 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB5:3 bits. Table 18. Current Recopy Trim for HB3:4 (CSA=1) itrim3 itrim2 itrim2 itrim0 Adjustment CRHB5 CRHB4 CRHB3 Adjustment 0 0 0 0 0 0 0 0 0 0 0 0 1 2% 0 0 1 -5% 0 0 1 0 4% 0 1 0 -10% 0 0 1 1 8% 0 1 1 -15% 0 1 0 0 12% 1 0 0 reserved 0 1 0 1 -2% 1 0 1 5% 0 1 1 0 -4% 1 1 0 10% 0 1 1 1 -8% 1 1 1 15% 1 0 0 0 -12% CRHB2:0 - Current Recopy HB1:2 Trim Bits These write only bits are for trimming of the current recopy of the half-bridge HB1 and HB2 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB2:0 bits. System Trim Register 2 (SYSTRIM2) Register Name and Address: IFBHBTRIM - $10 Bit7 6 5 4 3 2 1 Bit0 Read 0 0 0 0 0 0 0 0 Write CRH BHC 1 CRH BHC 0 CRH B5 CRH B4 CRH B3 CRH B2 CRH B1 CRH B0 0 0 0 Reset 0 0 0 0 0 CRHBHC1:0 - Current Recopy HB1:2 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB1 and HB2 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC1:0 bits. Table 19. Current Recopy Trim for HB1:2 (CSA=1) CRHB2 CRHB1 CRHB0 Adjustment 0 0 0 0 0 0 1 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 1 0 1 5% 1 1 0 10% 1 1 1 15% 908E622 50 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS System Trim Register 3 (SYSTRIM3) Table 21. Current Recopy Trim for HS2:3 Register Name and Address: IFBHSTRIM - $11 Bit7 6 5 4 3 2 1 Bit0 Read 0 0 0 0 0 0 0 0 Write CRH BHC 3 CRH BHC 2 CRH S5 CRH S4 CRH S3 CRH S2 CRH S1 CRH S0 0 0 0 0 0 0 0 0 Reset CRHBHC3:2 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB3 and HB4 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC3:2 bits. Table 20. Current Recopy Trim for HB3:4 (CSA=0) CRHS5 CRHS4 CRHS3 Adjustment 0 0 0 0 0 0 1 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 1 0 1 5% 1 1 0 10% 1 1 1 15% CRHS2:0 - Current Recopy HS1 Trim Bits These write only bits are for trimming the current recopy of the high side HS1. The provided Trim values have to be copied into these bits after every reset. Reset clears the CRHS2:0 bits. CRHBHC3 CRHBHC2 Adjustment 0 0 0 0 1 -10% CRHS2 CRHS1 CRHS0 Adjustment 1 0 5% 0 0 0 0 1 1 10% 0 0 1 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 1 0 1 5% 1 1 0 10% 1 1 1 15% CRHS5:3 - Current Recopy HS2:3 Trim Bits These write only bits are for trimming the current recopy of the high side HS2 and HS3. The provided trim values have to be copied into these bits after every reset. Reset clears the CRHS5:3 bits. Table 22. Current Recopy Trim for HS1 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 51 TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E622 has the MC68HC908EY16 MCU embedded, typically all the development tools available for the MCU also apply for this device. However, due to the additional analog die circuitry and the nominal +12 V supply voltage, some additional items have to be considered: • nominal 12 V rather than 5.0 or 3.0 V supply • high voltage VTST might be applied not only to IRQ pin, but IRQ_A pin • MCU monitoring (Normal request timeout) has to be disabled For a detailed information on the MCU related development support see the MC68HC908EY16 datasheet section development support. The programming is principally possible at two stages in the manufacturing process, first on chip level, before the IC is soldered onto a pcb board, and second after the IC is soldered onto the pcb board. Chip Level Programming At the Chip level, the easiest way is to only power the MCU with +5.0 V (see Figure 32), and not to provide the analog chip with VSUP. In this setup, all the analog pins should be left open (e.g. VSUP[1:8]), and interconnections between the MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 datasheet - section development support. VSUP[1:8] VDD GND[1:4] VSS +5V VDDA/VREFH RST EVDD RST_A +5V 1 1µF 16 + 4 C1- GND C2+ V+ + 5 RS232 DB-9 VCC + 3 1µF C1+ 100nF C2- MAX232 V- 7 T2OUT 3 8 R2IN +5V 1µF 9.8304MHz CLOCK 6 +5V + TESTMODE CLK PTB4/AD4 T2IN 10 6 3 2 10k PTC4/OSC1 1µF 74HC125 5 EVSS + 2 R2OUT 9 MM908E622 IRQ_A 15 4.7µF VSSA/VREFL 1µF 10k 74HC125 2 IRQ VTST 5 4 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 1 Figure 32. Normal Monitor Mode Circuit (MCU only) Of course its also possible to supply the whole system with PCB Level Programming VSUP instead (12 V), as described in Figure 33, page 53. If the IC is soldered onto the pcb board, its typically not possible to separately power the MCU with +5.0 V. The whole system has to be powered up and providing VSUP (see Figure 33). 908E622 52 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS . VDD VSUP 47µF + 100nF VSUP[1:8] VDD GND[1:4] VSS VDDA/VREFH RST EVDD RST_A 100nF VDD 1 1µF VCC 16 + + 3 4 1µF C1+ VTST C1- GND C2+ V+ + 5 RS232 DB-9 C2- MAX232 7 T2OUT 3 8 R2IN VDD 1µF 10k 9.8304MHz CLOCK VDD TESTMODE CLK 10k PTC4/OSC1 1µF PTB4/AD4 10 6 74HC125 R2OUT 9 EVSS + 2 + T2IN MM908E622 IRQ_A 10k 74HC125 2 4.7µF VSSA/VREFL 1µF 15 6 V- IRQ 10k 5 DATA PTA1/KBD1 PTA0/KBD0 10k 4 PTB3/AD3 3 2 1 5 Figure 33. Normal Monitor Mode Circuit Table 23 summarizes the possible configurations and the necessary setups. Table 23. Monitor Mode Signal Requirements and Options Mode IRQ RST Normal Monitor Forced Monitor VTST VDD TEST MODE Reset Vector 1 X 1 $FFFF (blank) VDD VDD Serial Communication Mode Selection PTA0 PTA1 PTB3 PTB4 1 0 0 1 1 0 X VDD VDD 0 not $FFFF (not blank) X X X ICG COP OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 ON disabled disabled — Nominal 1.6MHz Nominal 6300 ON enabled enabled — Nominal 1.6MHz Nominal 6300 X GND User Communication Speed Normal Request Bus Baud Time-out External Clock Frequency Rate X Notes 34. PTA0 must have a pullup resistor to VDD in monitor mode 35. 36. 37. 38. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don’t care VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V EMC/EMI RECOMMENDATIONS VSUP Pins (VSUP[1:8]) This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale web site www.freescale.com. Its recommended to place a high quality ceramic decoupling capacitor close to the VSUP pins to improve EMC/EMI behavior. 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 53 TYPICAL APPLICATIONS LIN Pin For DPI (Direct Power Injection) and ESD (Electrostatic Discharge), it is recommended to place a high quality ceramic decoupling capacitor near the LIN pin. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. Voltage Regulator Output Pins (VDD and VSS) Use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. MCU Digital Supply Pins (EVDD and EVSS) Fast signal transitions on MCU pins place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. MCU Analog Supply Pins (VREFH/VDDA and VREFL/ VSSA) To avoid noise on the analog supply pins, its important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. Figure 34 and Figure 35 show the recommendations on schematics and layout level, and Table 24 indicates recommended external components and layout considerations. D1 VSUP[1:8] VSUP C1 + VDD C2 VSS VDDA/VREFH L1 LIN LIN EVDD V1 C5 C3 MM908E622 C4 EVSS GND[1:4] VSSA/VREFL Figure 34. EMC/EMI recommendations 908E622 54 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS 1 54 2 53 3 52 4 51 5 50 49 VDDA/VREFH 48 8 EVDD 47 9 EVSS 46 10 VSSA/VREFL 45 11 44 12 43 VDD 42 908E622 16 GND1 39 38 17 18 VSUP1 19 GND2 VSUP8 37 36 VSUP7 20 21 41 40 15 VSUP2 35 34 23 VSUP6 32 24 VSUP5 31 GND3 GND4 30 VSUP3 VSUP4 25 29 26 D1 28 VBAT V1 27 GND 33 22 C1 14 LIN VSS C2 C5 13 C4 7 C3 6 LIN L1 Figure 35. PCB Layout Recommendations . Table 24. Component Value Recommendation Component Recommended Value(39) D1 Comments / Signal routing reverse battery protection C1 Bulk Capacitor C2 100 nF, SMD Ceramic, Low ESR Close to VSUP pins with good ground return C3 100 nF, SMD Ceramic, Low ESR Close (