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INTEGRATED CIRCUITS
74F109
Positive J-K positive edge-triggered
flip-flops
Product specification
IC15 Data Handbook
1990 Oct 23
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
FEATURE
74F109
PIN CONFIGURATION
• Industrial temperature range available (–40°C to +85°C)
RD0
1
16
VCC
J0
2
15
RD1
K0
3
14
J1
CP0
4
13
K1
SD0
5
12
CP1
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K inputs must
be stable just one setup time prior to the low-to-high transition of the
clock for predictable operation. The JK design allows operation as a
D flip-flop by tying J and K inputs together. Although the clock input
is level sensitive, the positive transition of the clock pulse between
the 0.8V and 2.0V levels should be equal to or less than the clock to
output delay time for reliable operation.
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT
(TOTAL)
74F109
125MHz
12.3mA
Q0
6
11
SD1
Q0
7
10
Q1
GND
8
9
Q1
SF00135
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
PKG DWG #
16-pin plastic DIP
N74F109N
I74F109N
SOT38-4
16-pin plastic SO
N74F109D
I74F109D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
PINS
J inputs
DESCRIPTION
1.0/1.0
20µA/0.6mA
K0, K1
K inputs
1.0/1.0
20µA/0.6mA
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
20µA/0.6mA
SD0, SD1
Set inputs (active Low)
1.0/3.0
20µA/1.8mA
RD0, RD1
Reset inputs (active Low)
1.0/3.0
20µA/1.8mA
Data outputs
50/33
1.0mA/20mA
Q0, Q1, Q0, Q1
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
2 14
3 13
2
1J
4
J1
J0
3
K0 K1
4
CP0
5
SD0
1
1
RD0
5
12
CP1
11
SD1
15
RD1
14
13
15
6
7
10
1K
11
9
7
R
S
2J
12
Q0 Q0 Q1 Q1
6
C1
10
C2
2K
9
R
S
VCC = Pin 16
GND = Pin 8
SF00136
October 23, 1990
SF00137
2
853–0337 00783
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
LOGIC DIAGRAM
74F109
FUNCTION TABLE
INPUTS
Q
6, 10
7, 9
Q
3, 13
K
J
CP
SD
RD
2, 14
4, 12
5, 11
1, 15
OUTPUTS
OPERATING MODE
SD
RD
CP
J
K
Q
Q
L
H
X
X
X
H
L
Asynchronous set
H
L
X
X
X
L
H
Asynchronous reset
L
L
X
X
X
H
H
Undetermined*
H
H
↑
X
X
q
q
Hold
H
H
↑
h
l
q
q
Toggle
H
H
↑
h
h
H
L
Load ”1” (set)
H
H
↑
l
l
L
H
Load ”0” (reset)
H
H
↑
l
h
q
q
Hold ’no change”
NOTES:
H = High-voltage level
h = High-voltage level one setup time prior to low-to-high
clock transition
L = Low-voltage level
l = Low-voltage level one setup time prior to low-to-high
clock transition
q = Lower case indicate the state of the referenced output
prior to the low-to-high clock transition
X = Don’t care
↑ = Low-to-high clock transition
↑ = Not low-to-high clock transition
* = Both outputs will be high if both SD and RD go low
simultaneously
VCC = Pin 16
GND = Pin 8
SF00138
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage
–0.5 to +7.0
V
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in High output state
–0.5 to VCC
V
IOUT
Current applied to output in Low output state
Tamb
Operating free-air
free air temperature range
Tstg
Storage temperature range
40
mA
Commercial range
0 to +70
°C
Industrial range
–40 to +85
°C
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
NOM
MAX
5.0
5.5
VCC
Supply voltage
4.5
VIN
High-level input voltage
2.0
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
IOH
High-level output current
–1
mA
IOL
Low-level output current
20
mA
Tamb
Operating free-air
free air temperature range
October 23, 1990
V
V
Commercial range
0
+70
°C
Industrial range
–40
+85
°C
3
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
VOH
O
High level output voltage
High-level
IOH
O = MAX
VCC = MIN, VIL = MAX,
VIH = MIN
IOL = MAX
Low level output voltage
Low-level
VIK
Input clamp voltage
VCC = MIN, II = IIK
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0V
IIH
High-level input current
IOS
Low level input current
Low-level
Short-circuit output
MIN
VCC = MIN, VIL = MAX,
VIH = MIN
VOL
O
IIL
LIMITS
TEST CONDITIONS1
PARAMETER
±10%VCC
2.5
±5%VCC
2.7
TYP2
MAX
UNIT
V
3.4
V
±10%VCC
0.30
0.50
V
±5%VCC
0.30
0.50
V
–0.73
–1.2
V
100
µA
VCC = MAX, VI = 2.7V
20
µA
J, K, CPn
VCC = MAX, VI = 0.5V
–0.6
mA
SDn, RDn
VCC = MAX, VI = 0.5V
–1.8
mA
–150
mA
current3
VCC = MAX
-60
ICC
Supply current4 (total)
VCC = MAX
12.3
17
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
VCC = +5.0V
Tamb = +25°C
CL = 50pF
RL = 500Ω
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF
RL = 500Ω
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF
RL = 500Ω
PARAMETER
TEST
CONDITION
MIN
TYP
fMAX
Maximum clock frequency
Waveform 1
90
125
tPLH
tPHL
Propagation delay
CPn to Qn or Qn
Waveform 1
3.8
4.4
5.3
6.2
7.0
8.0
3.8
4.4
8.0
9.2
3.8
4.4
9.0
9.2
ns
tPLH
tPHL
Propagation delay
SDn, RD to Qn or Qn
Waveform 2, 3
3.2
3.5
5.2
7.0
7.0
9.0
3.2
3.5
8.0
10.5
2.8
3.5
9.0
10.5
ns
SYMBOL
MAX
MIN
MAX
90
MIN
UNIT
MAX
90
MHz
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
Tamb = +25°C
CL = 50pF
RL = 500Ω
MIN
TYP
MAX
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF
RL = 500Ω
MIN
MAX
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF
RL = 500Ω
MIN
UNIT
MAX
tsu (H)
tsu(L)
Setup time, high or low
Dn to CPn
Waveform 1
3.0
3.0
3.0
3.0
3.0
3.0
ns
th (H)
th (L)
Hold time, high or low
Dn to CPn
Waveform 1
1.0
1.0
1.0
1.0
1.0
1.0
ns
tw (H)
tw (L)
CP pulse width,
high or low
Waveform 1
4.0
5.0
4.0
5.0
4.0
5.0
ns
tw (L)
SDn or RDn pulse width,
low
Waveform 2
4.0
4.0
4.0
trec
Recovery time
SDn or RDn to CP
Waveform 3
2.0
2.0
2.0
October 23, 1990
4
ns
ns
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Jn, Kn
VM
tsu(L)
VM
VM
VM
tsu(H)
th(L)
th(H)
1/fmax
CPn
VM
VM
VM
tw(H)
tw(L)
tPLH
Qn
tPHL
VM
VM
tPLH
tPHL
VM
VM
Qn
SF00139
Waveform 1. Propagation Delay for Data to Output, Data Setup
Time and Hold Times, and Clock Width,and Maximum
Clock Frequency
SDn VM
tw(L)
VM
tw(L)
RDn
VM
VM
tPHL
tPLH
Qn
VM
VM
tPLH
tPHL
VM
VM
Qn
SF00050
Waveform 2. Propagation Delay for Set and Reset to Output,
Set and Reset Pulse Width
SDn or RDn
VM
trec
CPn
VM
SF00051
Waveform 3. Recovery Timer for Set or Reset to Clock
October 23, 1990
5
74F109
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
TEST CIRCUIT AND WAVEFORMS
VCC
NEGATIVE
PULSE
VIN
tw
90%
VM
D.U.T.
RT
CL
RL
AMP (V)
VM
10%
VOUT
PULSE
GENERATOR
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
AMP (V)
90%
90%
POSITIVE
PULSE
DEFINITIONS:
RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
VM
VM
10%
Test Circuit for Totem-Pole Outputs
10%
tw
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00006
October 23, 1990
6
Philips Semiconductors
Product specification
Positive J-K positive edge-triggered flip-flops
DIP16: plastic dual in-line package; 16 leads (300 mil)
1990 Oct 23
7
74F109
SOT38-4
Philips Semiconductors
Product specification
Positive J-K positive edge-triggered flip-flops
SO16: plastic small outline package; 16 leads; body width 3.9 mm
1990 Oct 23
8
74F109
SOT109-1
Philips Semiconductors
Product specification
Positive J-K positive edge-triggered flip-flops
NOTES
1990 Oct 23
9
74F109
Philips Semiconductors
Product specification
Positive J-K positive edge-triggered flip-flops
74F109
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
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Document order number:
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Date of release: 10-98
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