NX5P3201CUKAZ

NX5P3201 3 A USB power switch and 6 A high-side load switch Rev. 1 — 11 December 2015 Product data sheet 1. General description The NX5P3201 is an advanced dual power switch consisting of two independent switches. They are, an advanced 3 A bidirectional power switch (SWP) for USB OTG and charger port applications, and a high-side 6 A load switch (SW5). SWP includes an open-drain status indicator. It also consists of OverTemperature Protection (OTP), UnderVoltage LockOut (UVLO) and OverVoltage LockOut (OVLO) protection circuits. The OVLO circuit isolates the pin VBUS when more than 6.55 V is applied to pin VBUS via the USB connector. To prevent unnecessary switching due to ringing on pins VBUS or PMU, the UVLO circuits include a 15 ms turn-on delay. This deglitch function allows the applied voltage to stabilize above VUVLO before closing SWP. SW5 consists of OTP, Reverse Current Protection (RCP), and UVLO protection circuits. The UVLO isolates VBAT from VIN until VI exceeds VUVLO. If the voltage at VBAT exceeds VI by 30 mV, the RCP circuit isolates VBAT from VIN. It prevents damage to devices on the input side of the switch. Both switches include slew rate controlled inrush current reduction to prevent damage when switching high capacitive loads. 2. Features and benefits         28 V tolerant VBUS supply pin Wide supply voltage range from 3.4 V to 6.55 V for SWP and 2.7 V to 5.5 V for SW5 Automatic SWP operation ISW continuous current: 3 A for SWP and 6 A for SW5 Low ON resistance: 32 m (typical) for SWP and 8 m (typical) for SW5 Soft-start, slew rate controlled turn-on time Status indicator output Protection circuitry  Reverse current protection  Overtemperature protection  Overvoltage lockout  Undervoltage lockout  ESD protection:  IEC61000-4-2 contact discharge exceeds 8 kV for pin VBUS  HBM JS-001-2012 class 3 A exceeds 4 kV  IEC61000-4-5 surge test exceeds 100 V for pin VBUS  Specified from 40 C to +85 C ambient temperature NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 3. Applications  Smartphone and feature phones  Tablets and e-books 4. Ordering information Table 1. Ordering information Type number NX5P3201CUK Package Name Description Version WLCSP30 wafer level chip-scale package; 30 bumps; 2.26 2.56 0.51 mm (backside coating included) SOT1443-2 5. Marking Table 2. Marking codes Type number Marking code NX5P3201CUK 5P32C 6. Functional diagram SW5 VIN VBAT SWP VBUS PMU EN5 ENP ACOK aaa-018349 Fig 1. Logic symbol NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch REVERSE CURRENT PROTECTION SW5 VIN VBAT UVLO EN5 CONTROL OVERTEMPERATURE PROTECTION SWP VBUS PMU OVLO UVLO UVLO ENP CONTROL ACOK OVERTEMPERATURE PROTECTION GND aaa-018350 Fig 2. Block diagram (simplified schematic) 7. Pinning information 7.1 Pinning 1 2 3 4 5 6 1 2 3 4 5 6 A A VIN VBAT VBAT VBAT VBAT n.c. B B VIN VIN VIN VIN VBAT ACOK C C EN5 GND VBUS VBUS PMU PMU D D GND GND VBUS VBUS PMU PMU E E ENP GND VBUS VBUS VBUS PMU Transparent top view Transparent top view aaa-018352 aaa-018351 Fig 3. Pin configuration WLCSP30 package NX5P3201 Product data sheet Fig 4. Ball mapping for WLCSP30 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 7.2 Pin description Table 3. Pin description Symbol Pin Description VBUS C3, C4, D3, D4, E3, E4, E5 power switch (SWP) input/output PMU C5, C6, D5, D6, E6 power switch (SWP) input/output VIN A1, B1, B2, B3, B4 load switch (SW5) input VBAT A2, A3, A4, A5, B5 load switch (SW5) output ACOK B6 status indicator (open drain; active LOW) GND C2, D1, D2, E2 ground (0 V) EN5 C1 load switch (SW5) enable input (active HIGH) n.c. A6 not connected[1] ENP E1 power switch (SWP) enable input (active HIGH) [1] Internally pulled down to GND. 8. Functional description Table 4. Function table for power switch (SWP)[1] ENP VBUS PMU ACOK Operation mode H VUVLO < VBUS < VOVLO < VUVLO L enable; power switch (SWP) closed; USB charging mode H < VUVLO > VUVLO L enable; power switch (SWP) closed; USB OTG mode H < VUVLO < VUVLO Z undervoltage lockout; power switch (SWP) open H X X Z overtemperature protection; power switch (SWP) open H > VOVLO X Z overvoltage lockout; power switch (SWP) open L X X Z disable; power switch (SWP) open [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state; X = don’t care. Table 5. Function table for load switch (SW5)[1] EN5 VIN VBAT Operation mode H < VUVLO X undervoltage lockout; load switch (SW5) open H > VUVLO VI enable; load switch (SW5) closed; high current mode H X X overtemperature protection; load switch (SW5) open H VI < VBAT  35 mV X reverse bias current or backdrive current; load switch (SW5) open L X X disable; load switch (SW5) open [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8.1 Enable inputs If protection circuits corresponding to load switch (SW5) are inactive, the EN5 enable input controls the load switch (SW5). Similarly, if protection circuits corresponding to power switch (SWP) are inactive, the ENP enable input controls the power switch (SWP). NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 8.2 UnderVoltage LockOut (UVLO) The UVLO circuit disables SWP when VBUS and Vsup < VUVLO. Once either VBUS or Vsup exceeds VUVLO for 15 ms, and no other protection circuits are active, the ENP controls SWP. An UVLO circuit disables SW5 when VI < VUVLO. Once VI > VUVLO and no other protection circuits are active, EN5 controls the state of SW5. 8.3 OverVoltage LockOut (OVLO) When VBUS > 6.55 V, the OVLO circuit disables SWP and sets the ACOK output to high-impedance state. Once VBUS < 6.45 V and no other protection circuits are active, ACOK is set to LOW and ENP controls SWP. 8.4 OverTemperature Protection (OTP) If SWP exceeds 130 C, its OTP circuit disables it and sets the ACOK output to high-impedance state. Once the temperature decreases below 110 C and no other protection circuits are active, if ENP is HIGH, then ACOK is set to LOW. The OTP circuit of SW5 protects SW5. However, it does not control the ACOK output. When the OTP circuit is deactivated, EN5 determines the state of SW5. 8.5 ACOK output The ACOK output is an open-drain output that requires an external pull-up resistor. If SWP is closed, the ACOK output is set to LOW. If the OVLO, UVLO or OTP circuits of SWP are activated, or ENP is LOW, ACOK is set to a high-impedance state. An external pull-up resistor of value between 10 k to 200 k is connected to ACOK. 8.6 Reverse Current Protection (RCP) When EN5 is HIGH, if VI < (VBAT  35 mV) for longer than 4 ms, the RCP circuit disables SW5. Once VI > VBAT for longer than 4 ms and no other protection circuits are active, EN5 determines the state of SW5. 9. Application design-in information The NX5P3201 typically connects a USB port in a portable battery operated device. The ACOK signal requires an additional external pull-up resistor which should be connected to a voltage source matching the logic level of the controller. Slew rate controlled inrush current reduction circuits function during switching. Once a switch is enabled, any large current generated through a change in load is not recognized as inrush current. NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch NX5P3201 ACOK EN5 VIN ENP VBAT SW5 VBUS PMU SWP GND 1 μF 10 μF 10 μF 1 μF aaa-018353 Fig 5. Test setup for ESD conformance to electrostatic discharge immunity test 10. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter input voltage VI Conditions Min Max Unit on pin VBUS [1] 0.5 +29 V on pin PMU [1] 0.5 +6.75 V on pin VIN [1] 2.0 +6.0 V [1] 0.5 +6.0 V [2][3] 0.5 +6.0 V 50 - mA 50 - mA Tamb = 85 C; power switch (SWP) - 3 A Tamb = 85 C; load switch (SW5) - 6 A on pins EN5 and ENP VO output voltage on pins VBAT and ACOK IIK input clamping current on pins EN5 and ENP ISK switch clamping current on pins VIN, VBUS, PMU, and VBAT; VI < 0.5 V ISW switch current ISWM peak switch current Tj junction temperature Tstg storage temperature tp = 1 ms; fsw = 217 Hz (GSM calibration) - 9 A tp = 100 s; fsw = 217 Hz (with rising time 100 s) - 11 A 40 +125 C 65 +150 C - 400 mW [4] total power dissipation Ptot [1] If the switch clamping current rating is observed, the minimum and maximum switch voltage ratings may be exceeded. [2] If the input current rating is observed, the minimum input voltage rating may be exceeded. [3] EN5 can be connected to VIN. In this condition, the minimum input voltage value is 2.0 V for EN5. [4] The (absolute) maximum power dissipation depends on the junction temperature Tj. Higher power dissipation is allowed at lower ambient temperatures. The conditions to determine the specified values are Tamb = 85 C and the use of a two-layer PCB. NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 11. Recommended operating conditions Table 7. Operating conditions Symbol Parameter Conditions Min Max Unit VI input voltage on pin VBUS 3.4 28 V on pin VIN 2.7 5.5 V VO output voltage Tamb ambient temperature on pin PMU 3.4 5.5 V on pins EN5 and ENP 0 5.5 V on pins ACOK and VBAT 0 5.5 V 40 +85 C 12. Thermal characteristics Table 8. Symbol Rth(j-a) [1] Thermal characteristics Parameter Conditions [1] thermal resistance from junction to ambient Typ Unit 99 K/W Rth(j-a) is dependent upon board layout. To minimize Rth(j-a), all pins should have a solid connection to larger copper layer areas. In multi-layer PCBs, the second layer should be used to create a large heat spreader area below the device. Avoid using solder-stop varnish under the device. 13. Static characteristics Table 9. Static characteristics for power switch (SWP) VBUS or Vsup = 4.0 V to 5.5 V unless otherwise specified; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max Min Max VIH HIGH-level input voltage on pin ENP 1.2 - - 1.2 - V VIL LOW-level input voltage on pin ENP - - 0.4 - 0.4 V VOL LOW-level output on pin ACOK; IO = 4 mA voltage - - 0.35 - 0.4 V Iq quiescent current on pin VBUS SWP closed; IO = 0 A; see Figure 6 - 220 - - 350 A SWP open; ENP = LOW; VBUS = 0 V to 5.5 V - 8 - - 16 A SWP closed; IO = 0 A; see Figure 7 - 220 - - 260 A SWP open; ENP = LOW; Vsup = 0 V to 5.5 V - 8 - - 16 A VBUS output; ENP = LOW; Vsup = 5.5 V; VBUS = 0 V to 28 V - 26 - - 35 A PMU output; ENP = LOW; VBUS = 28 V; Vsup = 0 V to 5.5 V - 5 - - 10 A on pin PMU IS(OFF) OFF-state leakage current NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch Table 9. Static characteristics for power switch (SWP) …continued VBUS or Vsup = 4.0 V to 5.5 V unless otherwise specified; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max Min Max on pins VBUS and PMU - 3.2 - 3.0 3.4 V Vhys(UVLO) undervoltage lockout hysteresis voltage on pins VBUS and PMU - 100 - 90 110 mV VOVLO on pin VBUS - 6.55 - 6.2 6.9 V Vhys(OVLO) overvoltage lockout hysteresis voltage on pin VBUS - 100 - 90 110 mV CS(ON) on pins VBUS and PMU - - 1.0 - 1.0 nF VUVLO [1] undervoltage lockout voltage overvoltage lockout voltage ON-state capacitance All typical values are measured at VBUS or Vsup = 5.0 V unless otherwise specified. Table 10. Static characteristics for load switch (SW5) VI = 2.7 V to 5.5 V unless otherwise specified; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max Min Max VIH HIGH-level input voltage EN5 input - - - 2.0 - V VIL LOW-level input voltage EN5 input - - - - 0.6 V II input leakage current EN5 input; Ven(lsw) = 0 V to 5.5 V - - - - 0.1 A Vth(RCP) RCP threshold voltage Vth(RCP) = VBAT  VI - 30 - 10 55 mV - 35 - 10 60 mV - 2.5 - 2.35 2.7 V EN5 = HIGH; see Figure 8 - 90 - - 150 A Vth(RCP)hys RCP threshold voltage hysteresis VUVLO undervoltage lockout voltage on pin VIN; EN5 = HIGH Iq quiescent current on pin VIN; IO = 0 A EN5 = LOW; see Figure 8 - 10 - - 15 A IOFF power-off leakage current VBAT = 0 V to 5.5 V; VI = 0 V; see Figure 11 - - - - 5.0 A IS(OFF) OFF-state leakage current VBAT output; EN5 = LOW; VI = 5.5 V; VBAT = 0 V to 5.5 V; see Figure 12 - - - 4.5 +2.0 A CS(ON) ON-state capacitance on pins VIN and VBAT - - 0.5 - 0.5 nF [1] All typical values are measured at VI = 3.0 V unless otherwise specified. NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 13.1 Graphs DDD  ,T ,9%86 ȝ$           7DPEƒ&  VBUS = 5.5 V; IO = 0 A; ENP = HIGH. Fig 6. Iq versus temperature DDD  ,T ,308 ȝ$           7DPEƒ&  Vsup = 5.5 V; IO = 0 A; ENP = HIGH. Fig 7. NX5P3201 Product data sheet Iq versus temperature All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch aaa-018354 120 aaa-018355 120 (1) 100 Iq (μA) 80 106 Iq (μA) 92 (3) 60 (2) 78 (1) 40 64 20 (2) 0 -40 50 -15 10 35 60 85 Tamb (°C) 3 3.4 3.8 4.2 4.6 5 VI (V) VI = 5.0 V; IO = 0 A. IO = 0 A. (1) EN5 = HIGH (1) Tamb = 40 C (2) EN5 = LOW (2) Tamb = 25 C (3) Tamb = 85 C Fig 8. Iq versus temperature Fig 9. Iq versus VI (EN5 = HIGH) aaa-018356 12 10 Iq (μA) 8 (3) 6 (2) (1) 4 2 3 3.4 3.8 4.2 4.6 5 VI (V) IO = 0 A. (1) Tamb = 40 C (2) Tamb = 25 C (3) Tamb = 85 C Fig 10. Iq versus VI (EN5 = LOW) NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch aaa-018357 2 aaa-018358 0.2 IS(OFF) (μA) 0 IOFF (μA) 1.6 (1) (2) -0.2 1.2 -0.4 0.8 (3) (3) -0.6 0.4 -0.8 (1) (2) 0 -1 0 1.1 2.2 3.3 4.4 5.5 VBAT (V) 0 1.1 VI = 0 V. VI = 5.5 V. (1) Tamb = 40 C (1) Tamb = 40 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 85 C (3) Tamb = 85 C Fig 11. IOFF versus VBAT 2.2 3.3 4.4 5.5 VBAT (V) Fig 12. IS(OFF) versus VBAT 13.2 ON resistance Table 11. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter RON ON resistance Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ Max Min Max IL = 200 mA - 32 - - 50 m IL = 1.5 A - 32 - - 50 m IL = 200 mA - 8 - - 13 m IL = 1.5 A - 8 - - 13 m SWP; VI = VBUS or Vsup = 4.0 V to 5.5 V; see Figure 13, Figure 14, and Figure 16 SW5; VI = 3.0 V to 5.5 V; see Figure 13, Figure 15, and Figure 17 NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 13.3 ON resistance test circuit and waveforms VSW SW5/SWP IL GND VI aaa-018359 RON = VSW / IL. Fig 13. Test circuit for measuring ON resistance aaa-018360 45 RON (mΩ) aaa-018361 10 RON (Ω) 40 9.4 (2) (1) 35 8.8 (1) (2) 30 8.2 25 7.6 20 -40 -15 10 35 60 85 Tamb (°C) 7 -40 (3) -15 (1) VI = 4.0 V (1) VI = 3.0 V (2) VI = 5.0 V (2) VI = 4.0 V 10 35 60 85 Tamb (°C) (3) VI = 5.0 V Fig 14. ON resistance versus temperature (SWP) NX5P3201 Product data sheet Fig 15. ON resistance versus temperature (SW5) All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch aaa-018362 45 RON (mΩ) aaa-018363 10 (3) RON (Ω) (3) 40 9.4 35 8.8 (2) (2) 30 8.2 25 7.6 (1) 20 3.2 (1) 7 3.66 4.12 4.58 5.04 5.5 VBUS (V) 3 3.4 3.8 4.6 5 VI (V) (1) Tamb = 40 C (1) Tamb = 40 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 85 C (3) Tamb = 85 C Fig 16. ON resistance versus bus supply voltage (SWP) 4.2 Fig 17. ON resistance versus input voltage (SW5) 14. Dynamic characteristics Table 12. Dynamic characteristics for power switch (SWP) At recommended operating conditions; voltages are referenced to GND (ground = 0 V); RL = 100 ; CL = 0.1 F; unless otherwise specified; for test circuit, see Figure 18 and Figure 20. Symbol Parameter Tamb = 25 C Conditions Min Typ Max Min Max - 14 - 9 19 ms - 14 - 9 19 ms VBUS = 5.0 V - 2 - 1.5 3.0 ms Vsup = 5.0 V - 6 - 1.65 7 ms VBUS = 3.0 V - 3.5 - 2.2 6.0 s Vsup = 3.0 V - 5 - 4 5.5 s - 26.5 - - - ms tdeb debounce time VBUS to Vsup; 4.0 V < VBUS < 5.5 V tTLH LOW to HIGH output transition time on pins PMU and VBUS; CL = 100 F disable time on pins PMU and VBUS Vsup to VBUS; 4.0 V < Vsup < 5.5 V tdis tstart(soft) soft-start time NX5P3201 Product data sheet Tamb = 40 C to +85 C Unit on pins PMU and VBUS; VI = VBUS or Vsup = 5.0 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 13 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch Table 13. Dynamic characteristics for load switch (SW5) At recommended operating conditions; voltages are referenced to GND (ground = 0 V); RL = 100 ; CL = 0.1 F; unless otherwise specified; for test circuit, see Figure 19 and Figure 20. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max Min Max ten enable time pin EN5 to pin VBAT - 2.4 - 0.9 3.0 ms tdis disable time pin EN5 to pin VBAT - 50 - 40 55 s tTLH LOW to HIGH on pin VBAT; RL = 125 ; CL = 1 F output transition time - 4 - 1.8 4.5 ms tTHL HIGH to LOW on pin VBAT; RL = 40 ; CL = 100 F output transition time - 8.0 - - 8.5 ms [1] All typical values are measured at VI = 5.0 V. 14.1 Waveforms and test circuits OVLO UVLO VBUS tstart(soft) tTLH thermal shutdown 90 % 90 % 10 % PMU tdeb tdeb tdis tdeb aaa-018364 Fig 18. SWP switching time VI EN5 VM GND tdis ten VOH VY VY VBAT GND VX VX tTLH tTHL aaa-018365 Measurement points are given in Table 14. Logic level: VOH is the typical output voltage that occurs with the output load. Fig 19. SW5 switching time NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 14 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch Table 14. Measurement points Input Output VI VM VX VY 5.0 V 0.5  VI 0.1  VOH 0.9  VOH EN5 SWP VIN G V I RL CL VEXT RL VIN CL VEXT aaa-018366 Test data is given in Table 15. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. Fig 20. Test circuits for measuring switching times Table 15. NX5P3201 Product data sheet Test data Supply voltage Input Load VEXT VI CL RL 3.0 V to 5.5 V 2.0 V 0.1 F 100  All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 15 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch aaa-018367 6 VBUS, Vsup (V) 5 (2) (1) 480 Iq (mA) 400 aaa-018368 6 VBUS, Vsup (V) 5 (2) (1) 360 Iq (mA) 300 4 320 4 240 3 240 3 180 2 160 2 120 80 1 0 0 1 (3) 0 0 8 16 24 32 40 (3) 60 0 0 8 16 24 32 t (ms) t (ms) RL = 100 ; CL = 100 F; Tamb = 25 C. RL = 100 ; CL = 100 F; Tamb = 25 C. (1) Vsup (1) VBUS (2) VBUS (2) Vsup (3) Iq on pin VBUS (3) Iq on pin PMU Fig 21. Waveform showing the enable time versus inrush current (SWP) aaa-018369 6 Ven(lsw), VBAT (V) 5 40 60 Iq (mA) 50 (2) 4 Fig 22. Waveform showing the enable time versus inrush current (SWP) aaa-018370 6 Ven(lsw),VBAT (V) 5 40 4 30 3 (1) 3 (3) (1) 2 20 2 1 10 1 0 0 0 0 1.2 2.4 3.6 4.8 6 (2) 0 120 t (ms) RL = 100 ; CL = 0.1 F; Tamb = 25 C. 240 360 480 600 t (μs) RL = 100 ; CL = 0.1 F; Tamb = 25 C. (1) VBAT (1) VBAT (2) Ven(lsw) (2) Ven(lsw) (3) Iq on pin VIN Fig 23. Waveform showing the enable time versus inrush current (SW5) NX5P3201 Product data sheet Fig 24. Waveform showing the disable time (SW5) All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 16 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 15. Package outline WLCSP30: wafer level chip-scale package; 30 bumps; 2.26 x 2.56 x 0.51 mm (backside coating included) B D SOT1443-2 A ball A1 index area A2 A E A1 detail X e1 e Øv Øw b C A B C C y 1/2 e E e D e2 C B A ball A1 index area 1 3 2 4 5 6 X 0 2 mm scale Dimensions (mm are the original dimensions) Unit mm A max 0.55 nom 0.51 min 0.47 A1 A2 b D E e e1 e2 0.23 0.20 0.17 0.34 0.31 0.29 0.29 0.26 0.23 2.59 2.56 2.53 2.29 2.26 2.23 0.4 2.0 1.6 v w y 0.05 0.015 0.03 Note: Backside coating 40 μm Outline version SOT1443-2 sot1443-2_po References IEC JEDEC JEITA European projection Issue date 15-06-10 15-06-11 --- Fig 25. Package outline SOT1443-2 (WLCSP30) NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 17 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 16. Soldering of WLCSP packages 16.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface mount reflow soldering description”. Wave soldering is not suitable for this package. All NXP WLCSP packages are lead-free. 16.2 Board mounting Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself 16.3 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 26) than a SnPb process, thus reducing the process window • Solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16. Table 16. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 26. NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 18 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to application note AN10365 “Surface mount reflow soldering description”. 16.3.1 Stand off The stand off between the substrate and the chip is determined by: • The amount of printed solder on the substrate • The size of the solder land on the substrate • The bump height on the chip The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip. 16.3.2 Quality of solder joint A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids. 16.3.3 Rework In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again. NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 19 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note AN10365 “Surface mount reflow soldering description”. 16.3.4 Cleaning Cleaning can be done after reflow soldering. 17. Abbreviations Table 17. Abbreviations Acronym Description ESD ElectroStatic Discharge HBM Human Body Model OTP OverTemperature Protection OVLO OverVoltage LockOut PCB Printed-Circuit Board RCP Reverse Current Protection USB OTG Universal Serial Bus On-The-Go UVLO UnderVoltage LockOut WLCSP Wafer Level Chip Scale Package 18. Revision history Table 18. Revision history Document ID Release date Data sheet status Change notice Supersedes NX5P3201 v.1 20151211 Product data sheet - - NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 20 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. NX5P3201 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 21 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 22 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 21. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Function table for power switch (SWP)[1] . . . . . .4 Function table for load switch (SW5)[1] . . . . . . . .4 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6 Operating conditions. . . . . . . . . . . . . . . . . . . . . .7 Thermal characteristics. . . . . . . . . . . . . . . . . . . .7 Static characteristics for power switch (SWP) . .7 Static characteristics for load switch (SW5) . . . .8 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics for power switch (SWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Dynamic characteristics for load switch (SW5).14 Measurement points . . . . . . . . . . . . . . . . . . . . .15 Test data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Lead-free process (from J-STD-020D) . . . . . .18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .20 Revision history . . . . . . . . . . . . . . . . . . . . . . . .20 NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 23 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 22. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Block diagram (simplified schematic). . . . . . . . . . .3 Pin configuration WLCSP30 package . . . . . . . . . .3 Ball mapping for WLCSP30 . . . . . . . . . . . . . . . . . .3 Test setup for ESD conformance to electrostatic discharge immunity test . . . . . . . . . . . . . . . . . . . . .6 Iq versus temperature . . . . . . . . . . . . . . . . . . . . . .9 Iq versus temperature . . . . . . . . . . . . . . . . . . . . . .9 Iq versus temperature . . . . . . . . . . . . . . . . . . . . .10 Iq versus VI (EN5 = HIGH) . . . . . . . . . . . . . . . . . .10 Iq versus VI (EN5 = LOW) . . . . . . . . . . . . . . . . . .10 IOFF versus VBAT . . . . . . . . . . . . . . . . . . . . . . . . . 11 IS(OFF) versus VBAT . . . . . . . . . . . . . . . . . . . . . . . . 11 Test circuit for measuring ON resistance . . . . . . .12 ON resistance versus temperature (SWP). . . . . .12 ON resistance versus temperature (SW5) . . . . . .12 ON resistance versus bus supply voltage (SWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 ON resistance versus input voltage (SW5) . . . . .13 SWP switching time . . . . . . . . . . . . . . . . . . . . . . .14 SW5 switching time . . . . . . . . . . . . . . . . . . . . . . .14 Test circuits for measuring switching times . . . . .15 Waveform showing the enable time versus inrush current (SWP) . . . . . . . . . . . . . . . . . . . . . .16 Waveform showing the enable time versus inrush current (SWP) . . . . . . . . . . . . . . . . . . . . . .16 Waveform showing the enable time versus inrush current (SW5) . . . . . . . . . . . . . . . . . . . . . .16 Waveform showing the disable time (SW5) . . . . .16 Package outline SOT1443-2 (WLCSP30) . . . . . .17 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 NX5P3201 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 December 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 24 of 25 NX5P3201 NXP Semiconductors 3 A USB power switch and 6 A high-side load switch 23. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 9 10 11 12 13 13.1 13.2 13.3 14 14.1 15 16 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 4 UnderVoltage LockOut (UVLO) . . . . . . . . . . . . 5 OverVoltage LockOut (OVLO) . . . . . . . . . . . . . 5 OverTemperature Protection (OTP) . . . . . . . . . 5 ACOK output . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reverse Current Protection (RCP) . . . . . . . . . . 5 Application design-in information . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Thermal characteristics . . . . . . . . . . . . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . 11 ON resistance test circuit and waveforms . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Waveforms and test circuits . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering of WLCSP packages. . . . . . . . . . . . 18 Introduction to soldering WLCSP packages . . 18 Board mounting . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Quality of solder joint . . . . . . . . . . . . . . . . . . . 19 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17 18 19 19.1 19.2 19.3 19.4 20 21 22 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 21 21 21 22 22 23 24 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 December 2015 Document identifier: NX5P3201