OL2385
Industrial RF transceiver
Rev. 1.0 — 15 June 2016
Product data sheet
COMPANY PUBLIC
1. General information
1.1 General description
The device is a fully integrated single-chip transceiver intended for use in an industrial
environment.
The device incorporates several commonly used building blocks including a crystal
stabilized oscillator, a fractional-N based Phase Locked Loop (PLL) for accurate
frequency selection in both TX and RX, Low Noise Amplifier (LNA), attenuator for
Automatic Gain Control (AGC), I/Q down-mixer and two high resolution Analog to Digital
Converters (ADC).The conversion into the digital domain is done in an early phase,
enabling a software defined radio like approach.
By transforming signals in the digital domain in an early phase, one highly configurable
RX channel is available including channel mixer, channel filter, ASK/FSK demodulator,
clock-data recovery, bit processor and a micro-controller memory interface (DMA)
allowing the micro-controller to complete the data handling and handshaking.
The device has an embedded RISC micro-controller optimized for high performance and
low power as well as an EROM for customer applications. The device also includes a
medium power UHF transmit system with a high dynamic range of -35dBm to +14dBm
which makes it ideal for the use in narrow band communication systems. The TX system
allows transmission with data rates up to 400 kbit/s NRZ.
Power ramping and splatter avoidance filters are included to ensure that the transmit
spectrum fulfills all the common standards in Europe, USA and Asia. The phase noise of
the transmitter supports ARIB operation.
The device includes a series of timers to allow for autonomous polling and wake-up
applications. The TX and RX data buffers are located in the RAM with autonomous direct
memory access (DMA), reducing the 'real-time' overhead for the accompanying
micro-controller. The device can be interfaced via SPI, UART or LIN protocol compatible
UART. Simplified programming of the device is facilitated by the HAL (Hardware
Abstraction Layer).
The transceiver is configured to operate with low active and standby power consumption,
ideal for battery powered applications.
OL2385
NXP Semiconductors
Industrial RF transceiver
2. Features and benefits
OL2385
Product data sheet
COMPANY PUBLIC
Single IC for worldwide usage in bands between 160 MHz and 960 MHz
Wide dynamic range with AGC to achieve excellent blocking performance
I/Q down conversion with digital IF processing and automatic gain compensation
Integrated I/Q phase and amplitude mismatch compensation
Receiver path with 2 multiplexed antenna inputs enables different antenna matching
Advanced signal monitoring and data management for fast and reliable signal
detection and processing
High dynamic range RSSI measurement
Programmable PA with digitally controlled power ramping and shaping
Operation up to 400 kbit/s 4FSK for high data rate applications
RX and TX data buffer in RAM with independent DMA channels
Integrated temperature sensor for crystal temperature drift compensation
Support of high accuracy external temperature sensor for ARIB systems
Integrated 16-bit extended micro RISC kernel for system on chip solutions with up to
32kByte EROM
10 independent DMA channels for powerful data transfer and configuration
Integrated copy machine for fast data transfer
Coprocessor for bit manipulation and code redundancy cycle calculation (CRC)
Several timers for firmware development including 3 general purpose timers, 3 RX
channel timers, low power mode polling timer and watch dog timer
Clock driver for micro controller crystal sharing
Controlled via SPI, UART, LIN compatible UART
10 bit ADC sensor interface with up to 100kSps sampling rate
Tool chain (compiler, assembler, linker, debugger) with in circuit debug capability
API available to simplify custom firmware development
IREC evaluation and demonstration kit available for basic RF operation
Remote control protocol (RCP) to operate RF without custom firmware via SPI/UART
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© NXP Semiconductors N.V. 2016. All rights reserved.
Rev. 1.0 — 15 June 2016
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NXP Semiconductors
Industrial RF transceiver
3. Applications
The IC supports the following system applications:
Smart Metering (sub-GHz Zigbee, wireless M-bus)
Home and building security and automation (KNX-RF)
Remote control devices
Wireless medical applications
Wireless sensor network
Industrial monitoring and control
Low Power Wide Area networks (SigFox)
OL2385
Product data sheet
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Rev. 1.0 — 15 June 2016
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Industrial RF transceiver
4. Quick reference data
Table 1.
Quick reference data
Parameter
Conditions
Min
Typ
Max
Unit
960
MHz
1
General
1.1
UHF Carrier Frequency
1.2
Power Down Current
1.3
Supply Voltage
1.9
5.5
V
1.4
Operating Temperature
-40
+85
°C
2
Transmitter
2.1
Supply Current
2.2
Max Output Power
2.3
Phase Noise @ 100 kHz Offset
3
Receiver
3.1
Supply Current
3.2
Data Rate
3.3
Sensitivity
158
700
nA
XTAL
0.25
mA
Tx @ 0 dBm
9
mA
Tx @ 14dBm
29
mA
14
dBm
169 MHz band
-120
dBc/Hz
434 MHz band
-117
dBc/Hz
868 MHz band
-109
dBc/Hz
925 MHz band
-108
dBc/Hz
@ 45 kHz BW
11
mA
@ 10 kHz BW
11
mA
400
kbit/s
ASK/OOK @ 10 kHz BW
-123
dBm
3.3.1
FSK @ 50 kHz BW
-112
dBm
3.3.2
FSK @ 10 kHz BW
-124
dBm
868 MHz
>50
dB
3.5
Adjacent channel rejection
3.6
Image channel rejection (calibrated)
3.7
Channel Filter Band Width
3.8
RSSI
3.10
60
4
Dynamic Range @ 10kHz BW
120
Variation
-3
dB
360
kHz
dB
3
dB
4
Micro-controller
4.1
EROM
32
kByte
4.2
Customer RAM
7
kByte
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Product data sheet
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5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
OL2385AHN/00100[1]
HVQFN48
Plastic thermal enhanced very thin quad flat package; no leads; 48
SOT619-13
terminals; body 7 x 7 x 0.85 mm; terminal pitch 0.5 mm; wettable flanks
OL2385AHN/001A0[2]
HVQFN48
Plastic thermal enhanced very thin quad flat package; no leads; 48
SOT619-13
terminals; body 7 x 7 x 0.85 mm; terminal pitch 0.5 mm; wettable flanks
OL2385AHN/001B0[3]
HVQFN48
Plastic thermal enhanced very thin quad flat package; no leads; 48
SOT619-13
terminals; body 7 x 7 x 0.85 mm; terminal pitch 0.5 mm; wettable flanks
OL2385AHN/001C0[4]
HVQFN48
Plastic thermal enhanced very thin quad flat package; no leads; 48
SOT619-13
terminals; body 7 x 7 x 0.85 mm; terminal pitch 0.5 mm; wettable flanks
[1]
OL2385
Product data sheet
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Version
Generic version without preflashed software
[2]
SigFox software stack preflashed
[3]
WMBus 2013 software stack preflashed
[4]
sub-GHz ZigBee MAC layer software stack preflashed
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Industrial RF transceiver
6. Marking
Table 3.
Marking information
Line
Example
Description
A
OL2385
2385 = Type number
B
*******
ID: *****xx (* = Diffusion lot number + x = Assembly ID); In case the number of
digits exceeds 7, ID is truncated by sequentially removing positions from left to
right.
C
ZSDyww*
Z = Manufacturer Code SSMC
S = Assembly Centre Kaohsiung
D = RoHS2006
yww = Date Code (Y = year, W = calendar week)
* = Release Status
X = customer engineering sample (CES)
Y = customer qualification sample (CQS)
_ = released samples (RFS)
D
2385ABrrff
2385 = Type number
A = std version
B = BOM version
rr = Rom Code version
ff = SW version
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Product data sheet
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OL2385
NXP Semiconductors
Industrial RF transceiver
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7. Block diagram
Block diagram
OL2385
Product data sheet
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Industrial RF transceiver
8. Pinning information
The circuit is packaged in a HVQFN48 with wettable flanks.
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Fig 2.
Pinout HVQFN48
8.1.1 Pin 1 keep out area
For the purpose of package orientation, so called "pin 1" identification is included. This
can either be as an additional small pin / pad as shown in design 1 (left) of Figure 3, or a
notch in the die pad as shown in design 2 (right) of Figure 3.
Note that the pin 1 identifier is electrically connected to the ground plate.
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Rev. 1.0 — 15 June 2016
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Industrial RF transceiver
Fig 3.
Pin 1 keep out area
8.2 Pin description
Table 4.
Pinning description
Symbol
Pin
Description
1
RF receiver input B (internally multiplexed with RF receiver input A)
2
Ground
TRXSWITCH_RX
3
TRX switch (interface to RX part)
GND_RF [6]
4
Ground
TRXSWITCH_ANT
5
TRX switch (interface to antenna)
6
Ground - connected to exposed die pad area
TRXSWITCH_TX
7
TRX switch (interface to TX part)
GND_PA_RF
8
Ground
9
Power amplifier output
GND_PA
10
Ground
VREGPA
11
Regulated power amplifier supply, requires external choke to TXOUT
VDD_PA
12
Power supply for PA block in transmit path
VDD_XO
13
Power supply for crystal oscillator
XTAL_N
14
Crystal oscillator input
GND_XO
15
Ground
XTAL_P
16
Crystal oscillator output
GND_LO
17
Ground
VDD_LO
18
Power supply for local oscillator
GND_LO
19
Ground
GND_DIG
20
Ground (digital)
VDD_3VOUT
21
3 V output voltage of the 5 V to 3 V LDO
VDD_5VIN
22
5 V input voltage of the 5 V to 3 V LDO
RF_IN_B
GND_RF
GND_RF
TXOUT
[6]
[2][6]
[7]
VDD_DIG
23
Power supply for digital part
P16
24
GPIO, wake-up, USART0, USART1
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Industrial RF transceiver
Table 4.
Pinning description
Symbol
Pin
Description
P15
25
GPIO, timer input, timer output, USART0, USART1
P14
26
GPIO, timer output, USART0, USART1
P13
27
GPIO, USART0
P12
28
GPIO, wake-up, timer input, USART0, USART1
P11
29
GPIO, fail safe wake-up, timer input, USART0, USART1
P10
30
GPIO, fail safe wake-up, timer output, RX and TX clock output
31
Power supply for digital I/Os
VDD_IO
[8]
32
Reset input (active low), internal pull-up resistor
MSDA [9]
33
Monitor and debug interface serial data (input/output; internal pull-up in input mode)
MSCL [10]
34
Monitor and debug interface serial clock (output)
P17
35
GPIO, wake-up, timer input, timer output, RX data output, TX data input, USART0,
USART1
P20
36
GPIO, wake-up, timer output, USART1
P21
37
GPIO, GP ADC input NEG
P22
38
GPIO, wake-up, GP ADC input POS, timer output
P23
39
GPIO, wake-up, GP ADC reference voltage, USART1
TEST [1]
40
Test pin (must be connected to ground in the application)
41
LDO output voltage
42
Ground (digital)
RST_N
VDD_DIGL
[3][4][5]
GND_DIG
GND_ADC
43
Ground
IFN_SENSE_IN
44
Selectable ADC negative input / pin used for test purposes
IFP_DCBUS
45
Selectable ADC positive input / pin used for test purposes
VDD_ADC
46
Power supply for ADC in receiver chain
VDD_RF
47
Power supply for receive path
RF_IN_A
48
RF receiver input A (internally multiplexed with RF receiver input B)
[1]
Pin TEST must be connected to ground in the application.
[2]
The exposed die pad area must be connected to ground.
[3]
VDD_DIGL is the internal supply of the digital part and shall only be externally connected to a blocking
capacitor 15 nF (nominal).
[4]
VDD_DIGL must neither be pulled to high voltages nor to GND
[5]
Do not use VDD_DIGL to supply external devices
[6]
All GND_RF are connected internally
[7]
TXOUT is not to be supplied externally except for an inductor connected to VREGPA
[8]
RST_N shall be connected only with a 4.7 kΩ resistor in series.
[9]
MSDA features an on-chip pull-up resistor to VDD_IO and may be left open or terminated to VDD_IO, as
desired.
[10] MSCL is an output and shall be unconnected in the application.
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9. Design information
9.1 Introduction
The device can be used in many applications where the flexibility of the micro-controller in
combination with the dedicated receive and transmit hardware are exploited. The range of
applications of such a device span from simple transmitter applications triggered by a key
press to complex half duplex RF multi protocol transceivers. In order to describe the
wealth of features and possibilities it is necessary to describe more detailed the key
functional blocks of the device. Functions, such as power management and wake-up
procedures (where the micro-controller is not controlling the process directly), permeate
the complete device and are described in the coming sections. The main functions are the
micro-controller subsystem, including the frequency generation system (the core of all RF
functionality), the transmitter system and the receiver systems.
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9.2 Power management
9.2.1 Modes of operation
The device supports operation in a 3 V, 5 V or a mixed 3 V and 5 V environment
supporting the following supply use cases:
1. Device and digital interface supplied with regulated 5 V supply
– Digital signaling between all devices in the system is done at 5 V level.
2. Device and digital interface supplied with regulated 3 V (3.3 V) supply
– Digital signaling between all devices in the system is done at 3 V (3.3 V) level.
3. Device supplied with regulated 3 V (3.3 V) supply and digital interface supplied with
regulated 5 V supply
– Digital signaling between all devices in the system is done at 5 V level.
4. Device and digital interface supplied with a single primary lithium battery cell (3.6 V …
1.9 V)
– Digital signaling between all devices in the system is done at the unregulated
battery voltage level.
5. Supply with a single rechargeable battery cell (4.2 V … 3.0 V) and an accompanied
voltage regulator (3.6 V … 2.5 V)
– Device is supplied with the regulated voltage.
– Digital signaling between all devices in the system is done at the unregulated
battery voltage level.
Connection diagrams for these different use cases are depicted in Figure 4.
9.2.2 External power supply domains
Several power supply pins are present to provide the required supply isolation between
various RF, analogue and digital blocks (external power supply domains). The power
supply pins have to be directly connected to a regulator output or a battery. External
supply switches are not required.
Adequate blocking capacitors have to be connected to the external supply pins.
Table 5.
External power supply domains
Power supply pin
Voltage range
Description
VDD_IO, GND_IO
3 V, 5 V
Main power supply domain of the device; supplies the I/O port pins, the
power-on reset circuit and an internal low-power regulator which
supplies the power state logic, the I/O port control latches, the polling
timer and the watchdog.
VDD_LO, GND_LO
3V
Power supply for the local oscillator (fractional-N PLL).
VDD_XO, GND_XO
3V
Power supply for the crystal oscillator.
VDD_RF, GND_RF
3V
Power supply for the radio frontend including the LNA, the input
attenuators and the mixer for receive mode.
VDD_PA, GND_PA
3V
Power supply for the power amplifier regulator output and the power
amplifier control for transmit mode.
VDD_ADC, GND_ADC
3V
Power supply for the sigma-delta ADCs in the radio receiver.
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Table 5.
External power supply domains
Power supply pin
Voltage range
Description
VDD_DIG, GND_DIG
3V
Power supply for the digital part.
VDD_5VIN
5V
Supply voltage input for the internal power regulator. This regulator
generates the required supply voltage for the device’s VDD supply pins
in the 3 V domains.
VDD_3VOUT
3V
Regulated supply voltage output of the internal power regulator.
[1]
Voltage ranges are given here only for information purpose. Please refer to the electrical characteristics for
detailed voltage range specification.
The external power supply domains with the associated power supply pins are briefly
described in the Table 5.
The package HVQFN has an exposed die pad at the back which is intended as heat sink
and additional ground connection.
The device includes an internal power regulator which can be used to generate a voltage
less than 3.6 V when such a voltage is not available. This regulator utilizes the two supply
pins VDD_5VIN and VDD_3VOUT. The regulator is only on if the device is in power
supply state ACTIVE. In all other power supply states the regulator is off. VDD_5VIN can
be supplied permanently and the input voltage must be greater than 3.6 V.
The application has to ensure that the current drawn from the internal power regulator
does not exceed the maximum limit given in the section electrical characteristics. If this
limit is exceeded all supply voltage pins in the 3 V domain must be connected to an
external voltage regulator. It is not allowed to supply parts of the device with the internal
and other ones with an external 3 V supply.
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Connection of external power supply domains for different power supply use cases
9.2.3 Recommended external capacitors in the supply domains
• The device is supplied by an external supply with 3V or 3.3V:
– Pin 21 VDD_3VOUT: open, not connected
– Pin 22 VDD_5VIN: connected to GND
– Pin 31 VDD_IO: 10nF (±20%) capacitor
– Pin 41 VDD_DIGL: 15nF (±20%) capacitor (mandatory)
– Pin 47 VDD_RF: 10nF (±20%) capacitor
– Pin 12 VDD_PA: 10nF (±20%) capacitor
– Pin 23 VDD_DIG: 10nF (±20%) capacitor
– Pin 18 VDD_LO: 22nF (±20%) capacitor
– Pin 13 VDD_XO: 68nF (±20%) capacitor
– Pin 46 VDD_ADC: 10nF (±20%) capacitor
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• The device is supplied by an external supply with 5V and the internal 5V to 3V
regulator is used:
– Pin 21 VDD_3VOUT: 10nF capacitor (±20%)
– Pin 22 VDD_5VIN: connected to external 5 V supply, 100nF (±20%) capacitor plus
optional 2.2µF capacitor
– Pin 31 VDD_IO: 10nF (±20%) capacitor
– Pin 41 VDD_DIGL: 15nF (±20%) capacitor (mandatory)
– Pin 47 VDD_RF: 10nF (±20%) capacitor
– Pin 12 VDD_PA: 10nF (±20%) capacitor
– Pin 23 VDD_DIG: 10nF (±20%) capacitor
– Pin 18 VDD_LO: 22nF (±20%) capacitor
– Pin 13 VDD_XO: 68nF (±20%) capacitor
– Pin 46 VDD_ADC: 10nF (±20%) capacitor
9.2.4 Power supply states
The device supports four different power states:
•
•
•
•
RESET state
POWER-OFF state
ACTIVE state
STANDBY state
The state diagram for the functional power supply states is given in Figure 5:
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Product data sheet
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All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Rev. 1.0 — 15 June 2016
15 of 85
OL2385
NXP Semiconductors
Industrial RF transceiver
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