QorIQ Communications Platforms
P Series
QorIQ P1015 and P1024
communications processors
Overview
The P1015 and P1024 processors are
the two QorIQ platforms deliver an impressive
Freescale QorIQ communications platforms are
perfectly suited for multi-service gateways,
4.5x aggregate frequency range.
the next-generation evolution of our leading
PowerQUICC communications processors.
Built using high-performance Power
Ethernet switch controllers, wireless LAN
The P1015 and P1024 platforms both feature
access points and high-performance general-
the e500 Power Architecture core and
purpose control processor applications with
peripherals, and are fully software compatible
Architecture® cores, QorIQ platforms enable
tight thermal constraints.
a new era of networking innovation where the
The P1015 and P1024 processors are pin-
enables you to create a product with multiple
reliability, security and quality of service for
compatible with the QorIQ P1016, P1025
performance points with a common software
every connection matters.
products, and software compatible with the
architecture. The P1024 dual-core processor
P1011/P1020 and P2010/P2020 offering a six-
supports both symmetric and asymmetric
chip range of cost-effective solutions. Scaling
processing, enabling you to further optimize
from a single core at 400 MHz (P1015) to a
your design with the same applications running
dual core at 1.2 GHz per core (P2020),
on each core or serialize your application using
QorIQ P1015 and P1024
Communications Processors
The QorIQ P1 family, which includes the P1015
with the existing PowerQUICC processors. This
the cores for different processing tasks.
and P1024 communications processors, offers
the value of smart integration and efficient
power for a wide variety of applications in the
networking, telecom, defense and industrial
markets. Based on 45 nm technology for low
power, the P1015 and P1024 processors
provide single- and dual-core options from
400 MHz to 667 MHz, together with advanced
P1024
Block
Diagram
QorIQ
QorIQP1015
P1015and
and
P1024
Block
Diagram
Not on P1015
Security
Acceleration
XOR
Power Architecture®
e500 Core
32 KB
32 KB
L1 I Cache L1 D Cache
256 KB
L2 Cache
Power Architecture
e500 Core
32 KB
32 KB
L1 I Cache L1 D Cache
security and a rich set of interfaces.
DDR3 SDRAM
Controller
DUART, 2x I2C, Timers,
Interrupt Control,
SD/MMC, SPI,
2x USB 2.0/ULPI
Coherency Module
Enhanced Local Bus
Controller (eLBC)
System Bus
TDM
3x
Gigabit
Ethernet
On-Chip Network
2x PCI Express® 4-ch. DMA Controller
4-lane SerDes
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)
Accelerators and Memory Control
Networking Elements
Basic Peripherals and Interconnect
The P1015 and P1024 processors have an
A multi-service router or business gateway
advanced set of features for ease of use.
requires a combination of high performance
The 256 KB L2 cache offers incremental
and a rich set of peripherals to support
configuration to partition the cache between
the data path throughputs and required
the two cores or to configure it as SRAM or
system functionality. The P1015 and P1024
• Two SGMII interfaces
stashing memory. The integrated security
devices offer a scalable platform to develop
engine supports the cryptographic algorithms
a range of products that can support the
• Two high-speed USB controllers (USB 2.0)
commonly used in IPsec, SSL, 3GPP and
same feature set. Integrated 10/100/1000
other networking and wireless security
Ethernet controllers with classification and
protocols. The memory controller offers future-
QoS capabilities are ideal for managing the
proofing against memory technology migration
data path traffic between the LAN and WAN
with support for DDR3. It also supports error
interface. PCI Express ports can provide
correction codes, a baseline requirement for
connectivity to IEEE 802.11n radio cards
any high-reliability system.
for wireless support, TDM for legacy phone
interfaces to support voice, the USB or SD/
The P1015 and P1024 processors integrate a
rich set of interfaces, including a multi-protocol
SerDes, Gigabit Ethernet, PCI Express® and
USB. The three 10/100/1000 Ethernet ports
support advanced packet parsing, flow control
and quality of service features, as well as IEEE
®
1588 time-stamping—all ideal for managing
the data path traffic between the LAN and
WAN interface. A TDM interface can support
voice for legacy phone applications. Four
SerDes lanes can be portioned across two PCI
Express ports and two SGMII ports. The PCI
Express ports can provide connectivity to IEEE
802.11n radio cards for wireless support. USB
or SD/MMC interfaces can be used to support
local storage. A second USB interface is also
available to support USB attached printers or
as a console port. Multiple memory connection
ports are available, including the 16-bit local
bus, two USB 2.0 controllers, eSDHC and SPI.
Target Applications
The P1015 and P1024 processors serve in
a wide variety of applications. The devices
are well-suited for various combinations of
data plane and control plane workloads in
networking and telecom applications. With an
available junction temperature range of –40º C
• Two PCI Express controllers
• Host and device support
• Enhanced host controller interface (EHCI)
• ULPI interface to PHY
• Enhanced secure digital host
controller (eSDHC)
• Serial peripheral interface
• Integrated security engine (SEC 3.3)
storage, the second USB interface is also
• Crypto algorithm support includes 3DES,
available to support USB attached printers
AES, RSA/ECC, MD5/SHA, ARC4, Snow
or as a console port. And the integrated
3G, and FIPS deterministic RNG
security engine can provide encrypted secure
communications for remote users with
VPN support.
Technical Specifications
• Dual (P1024) or single (P1015) highperformance Power Architecture
e500 cores
• 36-bit physical addressing
• Single pass encryption/message
authentication for common security
protocols (IPsec, SSL, SRTP, WiMAX)
• XOR acceleration
• 32-bit DDR3 SDRAM memory controller
with ECC support
• Programmable interrupt controller (PIC)
compliant with OpenPIC standard
• Double-precision floating-point support
• Four-channel DMA controller
• 32 KB L1 instruction cache and 32 KB L1
• Two I2C controllers, DUART, timers
data cache for each core
• 400 MHz to 667 MHz core clock frequency
• 256 KB L2 cache with ECC, also
configurable as SRAM and
stashing memory
• Enhanced local bus controller (eLBC)
• 16 general-purpose I/O signals
• Package: 561-pin wirebond power-BGA
(TEPBGA1)
• Three 10/100/1000 Mb/s enhanced threespeed Ethernet controllers (eTSECs)
• TCP/IP acceleration and
classification capabilities
• IEEE 1588 support
sensitive defense and industrial applications,
• Lossless flow control
from the environment. The devices’ primary
• RGMII, SGMII
target applications are networking and
• High-speed interfaces (not all
telecom linecards.
across controllers
MMC interfaces can be used to support local
to +125º C, the devices can be used in powerand outdoor environments less protected
• Four SerDes to 3.125 GHz multiplexed
available simultaneously)
For more information, please visit freescale.com/QorIQ
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QUICC Engine is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective
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Document Number: QP1024FS REV 2