P5040NSN7TMC

QorIQ Communications Platforms P Series QorIQ P5040 and P5021 communications processors Overview e5500 Core The QorIQ P5 family delivers scalable 64-bit The P5040 is based on the 64-bit e5500 processing with single-, dual- and quad-core Power Architecture® core. The e5500 devices. With frequencies scaling up to core uses a seven-stage pipeline for low 2.2 GHz, a tightly coupled cache hierarchy latency response to unpredictable code for low latency, and integrated hardware execution paths, boosting its single-threaded acceleration, the P5040 (quad-core) and performance. Key features: P5021 (dual-core) devices are ideally suited for compute intensive, power-conscious control plane applications. DPAA Hardware Accelerators The P5040 processor is designed for highperformance, power-constrained control plane applications. The P5040 processor provides an ideal combination of core performance, integrated accelerators and advanced I/O required for the following compute-intensive applications: • Enterprise equipment: Router, switch, services • Data center: Server appliance, SAN storage controller, iSCSI controller, FCoE bridging Buffer manager (BMAN) 64 buffer pools Queue manager (QMAN) Up to 224 queues Security (SEC) 17 Gb/s: 3 DES, AES RAID5/6 Engine Calculates parity for network attached storage and direct attached storage applications • Tightly coupled low latency cache Data Path Acceleration Architecture (DPAA) per core • Up to 2 MB of shared platform cache (L3) The P5040 processor integrates QorIQ • 3 DMIPS/MHz per core DPAA, an innovative multicore infrastructure for scheduling work to cores (physical and • Up to 64 GB of addressable memory space virtual), hardware accelerators and network • Hybrid 32-bit mode to support legacy interfaces. The FMAN, a primary element of the software and seamless transition to DPAA, parses headers from incoming packets 64-bit architecture and classifies and selects data buffers with optional policing and congestion management. Virtualization The FMAN passes its work to the QMAN, The P5040 processor includes support for which assigns it to cores or accelerators hardware-assisted virtualization. The e5500 with a multilevel scheduling hierarchy. The core offers an extra core privilege level P5040 processor also offers accelerators for (hypervisor). Virtualization software for the P5 cryptography and RAID5/6 offload. family includes kernel-based virtual machine, • Aerospace and defense Linux® containers, Freescale hypervisor and • Industrial computing: Single-board commercial virtualization software from Green computers, test/measurement, robotics 24 Gb/s classify, parse and distribute • Supports up to 2.2 GHz core frequencies hierarchy: 32 KB I/D (L1), 512 KB L2 Target Markets and Applications Frame manager (FMAN) Hills® Software and Enea®. QorIQ P5040/P5021 Processors QorIQ P5040/P5021 Processors *Only Available on P5040 Power Architecture® e5500 Core 512 KB Backside L2 Cache 32 KB D Cache 32 KB I Cache Security Fuse Processor PAMU PAMU eLBC Power Management SD/MMC Queue Mgr. SEC 5.2 2x DUART 4x I2C SPI, GPIO 64-bit DDR3/3L Memory Controller 1024 KB CoreNet Platform Cache 64-bit DDR3/3L Memory Controller CoreNet Coherency Fabric Security Monitor 2x USB 2.0 w/PHY 1024 KB CoreNet Platform Cache RAID 5/6 Engine Buffer Mgr. Peripheral Access PAMU Management Unit PAMU Frame Manager Frame Manager Parse, Classify, Distribute Parse, Classify, Distribute 10 GE 1GE 1GE 1GE 1GE 1GE 10 GE 1GE 1GE 1GE 1GE 1GE PCIe PCIe PCIe 20-Lane 5 GHz SerDes Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Accelerators and Memory Control Networking Elements Real-Time Debug 2x DMA Basic Peripherals and Interconnect SATA 2.0 Watchpoint Cross Trigger Perf. Monitor Trace Aurora  P5 Family Comparison Chart P5020/P5010 P5040/P5021 CPU cores 2x 64-bit e5500, 1x (P5010) 4x 64-bit e5500, 2x (P5021) Threads 2/1 (single thread per core) 4/2 (single thread per core) Max. core frequency 1.6 to 2 GHz 1.8 to 2.2 GHz L2 512 KB per core 512 KB per core L3/Platform 2 MB (P5020)/1 MB (P5010) 2 MB (both P5040 and P5021) DDR I/F 2x 64-bit DDR3 (up to 1333 MT/s) 1x 64-bit DDR3 (P5010) 2x 64-bit DDR3 (up to 1600 MT/s) PCI Express® 4x PCIe v2.0 3x PCIe v2.0 (incl. 1x 8) GbE, 10 GbE 5x 1 GbE, 1x 10 GbE 10x 1 GbE, 2x 10 GbE SRIO 2x SRIO v2.1 (supports type 9 and type 11 messaging) N/A SerDes lanes 18 lanes 20 lanes Package 1295-pin 37.5 x 37.5 mm FC-PBGA 1295-pin 37.5 x 37.5 mm FC-PBGA System Peripherals and Networking P5040/P5021 Features List Four (P5040) or two (P5021) single-threaded e5500 cores built on Power Architecture technology • Up to 2.2 GHz with 64-bit ISA support (Power Architecture V2.06 compliant) • Three levels of instruction: User, supervisor, hypervisor • Hybrid 32-bit mode to support legacy software and transition to 64-bit architecture CoreNet platform cache (CPC) • 2 MB configured as dual 1 MB blocks Hierarchical interconnect fabric • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints • QMAN fabric supporting packet-level queue management and quality of service scheduling Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support • Up to 1600 MT/s • Memory pre-fetch engine DPAA incorporating acceleration for the following functions • • • • SerDes lanes • 20 lanes at up to 5 Gb/s • Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces • Two 10 Gb/s Ethernet MACs • 10x 1 Gb/s Ethernet MACs High-speed peripheral interfaces • Three PCI Express 2.0 controllers • Serial ATA (SATA 2.0) controller Additional peripheral interfaces • QorIQ P5040 development system (P5040DS) available • • • • • • DMA • Dual four channel • QorIQ P5040 reference design board (P5040RDB) available Support for hardware virtualization and partitioning enforcement • Extra privileged level for hypervisor support QorIQ trust architecture 1.1 • Secure boot, secure debug, tamper detection, volatile key storage For networking, there are dual FMANs with dual 10 Gb/s and 10x 1 Gb/s MAC controllers that connect to PHYs, switches and backplanes over RGMII, SGMII and XAUI. High-speed system expansion is supported through three PCI Express v2.0 controllers that support a variety of lane widths. Other peripherals include SATA, SD/MMC, I2C, UART, SPI, NOR/NAND controller, GPIO and dual 1600 MT/s DDR3/3L controllers. Software and Tool Support • Enea: Real-time operating system support and virtualization software • Green Hills: Comprehensive portfolio of software and hardware development tools, trace tools, real-time operating systems and virtualization software • Mentor Graphics®: Commercial-grade Linux solution • QNX®: Real-time OS and development tool support Packet parsing, classification and distribution (FMAN) QMAN for scheduling, packet sequencing and congestion management Hardware BMAN for buffer allocation and de-allocation Cryptography acceleration (SEC 5.2) at up to 20 Gb/s Two High-Speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface Four I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2012, 2014 Freescale Semiconductor, Inc. Document Number: P50405021FS REV 4