PCF8576D
40 × 4 universal LCD driver for low multiplex rates
Rev. 15.1 — 1 September 2021
1
Product data sheet
General description
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
1
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be
easily cascaded for larger LCD applications. The PCF8576D is compatible with most
2
microcontrollers and communicates via the two-line bidirectional I C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
• PCF8576DT/2 should not be used for new design-ins. Replacement part is
PCF85176T/1 for industrial applications
• PCF8576DT/S400/2 should not be used for new design-ins. Replacement part is
PCA85176T/Q900/1 for automotive applications
For a selection of NXP LCD segment drivers, see Table 29.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 compliant (PCF8576DT/S400/2) for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
1
1
Selectable display bias configuration: static, ⁄2, or ⁄3
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
– Up to 20 7-segment numeric characters
– Up to 10 14-segment alphanumeric characters
– Any graphics of up to 160 segments/elements
40 × 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
– From 2.5 V for low-threshold LCDs
– Up to 6.5 V for high-threshold twisted nematic LCDs
Low power consumption
2
400 kHz I C-bus interface
May be cascaded for large LCD applications (up to 2 560 segments/elements possible)
1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
• No external components required
• Compatible with chip-on-glass and chip-on-board technology
• Manufactured in silicon gate CMOS process
3
Ordering information
Table 1. Ordering information
Type number
Topside mark Package
Name
Description
Version
PCF8576DT
TSSOP56
plastic thin shrink small outline package, 56 leads;
body width 6.1 mm
SOT364-1
PCF8576DT/
[2]
S400/2
PCF8576DT/
S400
TSSOP56
plastic thin shrink small outline package, 56 leads;
body width 6.1 mm
SOT364-1
PCF8576DU/DA/2
PC8576D-1
wire bond
die
bare die
59 bonding pads
PCF8576DU/DA
59 bumps
PCF8576DU/2DA
PCF8576DT/2
[1]
PCF8576DU/2DA/2 PC8576D-2
[1]
[2]
Not to be used for new designs. Replacement part is PCF85176T/1 for industrial applications.
Not to be used for new designs. Replacement part is PCF85176T/Q900/1 for automotive applications.
Standard packing quantities and other packaging data are available at www.nxp.com/
packages/.
3.1 Ordering options
Table 2. Ordering options
Type number
Orderable part number
Package
Packing method
Minimum
order
quantity
Temperature
PCF8576DT/2
PCF8576DT/2,118
TSSOP56
reel 13" q1 non dry
pack
2000
Tamb = -40 °C to +85 °C
TSSOP56
reel 13" q1 dry pack 2000
Tamb = -40 °C to +85 °C
PCF8576DT/S400/2 PCF8576DT/S400/2,1
TSSOP56
reel 13" q1 non dry
pack
2000
Tamb = -40 °C to +85 °C
PCF8576DU/DA/2
PCF8576DT/S400/2Y
PCF8576DU/DA/2,026
reel 13" q1 dry pack 2000
2" waffle carriers
8640
Tamb = -40 °C to +85 °C
Tamb = -40 °C to +85 °C
PCF8576DU/2DA/2
PCF8576DU/2DA/2,02
TSSOP56
wire bond
die
bare die
2" waffle carriers
Tamb = -40 °C to +85 °C
[1]
PCF8576DT/2,518
[2]
[1]
[2]
8640
See 202107021DN - drop in replacement is PCF8576DT/2,518 - this is documented in PCN202102010F01.
See 202107021DN - drop in replacement is PCF8576DT/S400/2Y - this is documented in PCN202102010F01.
PCF8576D
Product data sheet
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
4
Block diagram
BP0
BP2
BP1
BP3
S0 to S39
40
VLCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT
OUTPUTS
LCD
VOLTAGE
SELECTOR
VSS
CLK
DISPLAY
REGISTER
DISPLAY
CONTROLLER
LCD BIAS
GENERATOR
SYNC
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
OSC
OSCILLATOR
POWER-ON
RESET
INPUT
FILTERS
I2C-BUS
CONTROLLER
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY RAM
40 × 4-BIT
PCF8576D
COMMAND
DECODER
WRITE DATA
CONTROL
DATA POINTER AND
AUTO INCREMENT
VDD
SCL
SDA
SA0
SUBADDRESS
COUNTER
A0
A1
A2
001aai900
Figure 1. Block diagram of PCF8576D
PCF8576D
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
5
Pinning information
5.1 Pinning
BP2
1
56 BP0
BP1
2
55 VLCD
BP3
3
54 VSS
S0
4
53 SA0
S1
5
52 A2
S2
6
51 A1
S3
7
50 A0
S4
8
49 OSC
S5
9
48 VDD
S6 10
47 CLK
S7 11
46 SYNC
S8 12
45 SCL
S9 13
44 SDA
S10 14
S11 15
43 S39
PCF8576DT
42 S38
S12 16
41 S37
S13 17
40 S36
S14 18
39 S35
S15 19
38 S34
S16 20
37 S33
S17 21
36 S32
S18 22
35 S31
S19 23
34 S30
S20 24
33 S29
S21 25
32 S28
S22 26
31 S27
S23 27
30 S26
S24 28
29 S25
001aaf646
Top view. For mechanical details, see Figure 25.
Figure 2. Pinning diagram for PCF8576DT (TSSOP56)
PCF8576D
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PCF8576D
NXP Semiconductors
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
35
34
33
32
31
30
29
28
27
26
25
24
23
22
40 × 4 universal LCD driver for low multiplex rates
21
S3
S18
36
20
S2
S19
37
19
S1
S20
38
18
S0
S21
39
S22
40
17
BP3
S23
41
16
BP1
S24
42
15
BP2
S25
43
14
BP0
S26
44
13
VLCD
S27
45
S28
46
S29
47
12
VSS
S30
48
S31
49
11
SA0
S32
50
10
A2
S33
51
9
A1
53
54
55
56
57
58
59
1
2
3
4
5
6
7
8
S35
S36
S37
S38
S39
SDA
SDA
SDA
SCL
SCL
SYNC
CLK
VDD
OSC
A0
C1
52
S34
C2
PCF8576DU
001aag424
Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see Figure 26
and Figure 27.
Figure 3. Pinning diagram for PCF8576DU (bare die)
5.2 Pin description
Table 3. Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise
specified.
Symbol
PCF8576D
Product data sheet
Pin
Description
PCF8576DT
PCF8576DU
SDA
44
1, 58, 59
I C-bus serial data input and output
SCL
45
2, 3
I C-bus serial clock input
CLK
47
5
external clock input or output
VDD
48
6
supply voltage
SYNC
46
4
cascade synchronization input or output; if
not used it must be left open
OSC
49
7
internal oscillator enable input
2
2
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Table 3. Pin description...continued
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise
specified.
Symbol
Description
PCF8576DT
PCF8576DU
A0 to A2
50 to 52
8 to 10
subaddress inputs
SA0
53
11
I C-bus address input; bit 0
VSS
54
12
VLCD
55
13
LCD supply voltage
BP0, BP2,
BP1, BP3
56, 1, 2, 3
14 to 17
LCD backplane outputs
S0 to S39
4 to 43
18 to 57
LCD segment outputs
n.c.
-
-
not connected
[1]
6
Pin
2
[1]
ground supply voltage
The substrate (rear side of the die) is connected to VSS and should be electrically isolated .
Functional description
The PCF8576D is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up
to 40 segments.
The possible display configurations of the PCF8576D depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 4. All
of these configurations can be implemented in the typical system shown in Figure 5.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Figure 4. Example of displays suitable for PCF8576D
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Table 4. Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment
[1]
[2]
14-segment
Dot matrix:
segments/
elements
4
160
20
10
160 (4 × 40)
3
120
15
7
120 (3 × 40)
2
80
10
5
80 (2 × 40)
1
40
5
2
40 (1 × 40)
[1]
[2]
7 segment display has 8 segments/elements including the decimal point.
14 segment display has 16 segments/elements including decimal point and accent dot.
VDD
R≤
tr
2CB
VDD
VLCD
SDA
HOST
MICROPROCESSOR/
MICROCONTROLLER
40 segment drives
SCL
PCF8576D
OSC
4 backplanes
A0
A1
A2
LCD PANEL
(up to 160
elements)
SA0 VSS
VSS
mdb079
The resistance of the power lines must be kept to a minimum.
For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply
line must be routed separately between the chip and the connector.
Figure 5. Typical system configuration
2
The host microcontroller maintains the 2-line I C-bus communication channel with the
PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(VDD, VSS, and VLCD) and the LCD panel chosen for the application.
6.1 Power-On Reset (POR)
At power-on the PCF8576D resets to the following starting conditions:
•
•
•
•
•
•
•
All backplane and segment outputs are set to VLCD
1
The selected drive mode is: 1:4 multiplex with ⁄3 bias
Blinking is switched off
Input and output bank selectors are reset
2
The I C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E = 0, see Table 11)
2
Remark: Do not transfer data on the I C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
6.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
1
by switch if the ⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected. The LCD voltage can be temperature compensated externally using the supply
to pin VLCD.
6.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with
the selected LCD drive configuration. The operation of the voltage selector is controlled
by the mode-set command from the command decoder. The biasing configurations that
apply to the preferred modes of operation, together with the biasing characteristics as
functions of VLCD and the resulting discrimination ratios (D) are given in Table 5.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage
across a segment. It can be thought of as a measurement of contrast.
Table 5. Biasing characteristics
LCD drive
mode
Number of:
static
1
Backplanes Levels
1:2 multiplex 2
1:2 multiplex 2
1:3 multiplex 3
1:4 multiplex 4
LCD bias
configuration
2
static
0
1
∞
3
1
0.354
0.791
2.236
4
1
0.333
0.745
2.236
4
1
0.333
0.638
1.915
4
1
0.333
0.577
1.732
⁄2
⁄3
⁄3
⁄3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast.
In the static drive mode a suitable choice is VLCD > 3Vth(off).
1
Multiplex drive modes of 1:3 and 1:4 with ⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by
, where the values for a are
1
a = 1 for ⁄2 bias
1
a = 2 for ⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
(3)
1
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with ⁄2 bias
1
is
and the discrimination for an LCD drive mode of 1:4 multiplex with ⁄2 bias
is
.
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage
VLCD as follows:
•
•
1
1:3 multiplex ( ⁄2 bias):
1
1:4 multiplex ( ⁄2 bias):
1
These compare with
when ⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
6.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 6. For a good contrast performance, the following rules should be followed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the
selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
100 %
Relative Transmission
90 %
10 %
Vth(off)
OFF
SEGMENT
Vth(on)
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
013aaa494
Figure 6. Electro-optical characteristic: relative transmission curve of the liquid
6.4 LCD drive mode waveforms
6.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 7.
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
- VLCD
VLCD
state 2
0V
- VLCD
1.
2.
3.
4.
(b) Resultant waveforms
at LCD segment.
mgl745
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = VSn+1(t) - VBP0(t).
Voff(RMS) = 0 V.
Figure 7. Static drive mode waveforms
6.4.2 1:2 Multiplex drive mode
The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This
1
1
mode allows fractional LCD bias voltages of ⁄2 bias or ⁄3 bias as shown in Figure 8 and
Figure 9.
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
Tfr
VLCD
BP0
LCD segments
VLCD / 2
VSS
state 1
VLCD
BP1
state 2
VLCD / 2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD / 2
state 1
0V
- VLCD / 2
- VLCD
VLCD
VLCD / 2
state 2
0V
- VLCD / 2
- VLCD
1.
2.
3.
4.
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn+1(t) - VBP1(t).
Voff(RMS) = 0.354VLCD.
mgl746
1
Figure 8. Waveforms for the 1:2 multiplex drive mode with ⁄2 bias
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
Tfr
VLCD
BP0
BP1
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
2VLCD / 3
state 2
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
Sn+1
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
state 1
VLCD / 3
0V
- VLCD / 3
- 2VLCD / 3
- VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
1.
2.
3.
4.
0V
- VLCD / 3
- 2VLCD / 3
- VLCD
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn+1(t) - VBP1(t).
Voff(RMS) = 0.333VLCD.
mgl747
1
Figure 9. Waveforms for the 1:2 multiplex drive mode with ⁄3 bias
6.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies
(see Figure 10).
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40 × 4 universal LCD driver for low multiplex rates
BP0
VLCD
2VLCD / 3
Tfr
LCD segments
VLCD / 3
VSS
state 1
VLCD
BP1
BP2
Sn
Sn+1
Sn+2
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
state 1
2VLCD / 3
VLCD / 3
0V
- VLCD / 3
- 2VLCD / 3
- VLCD
VLCD
2VLCD / 3
state 2
VLCD / 3
0V
- VLCD / 3
- 2VLCD / 3
- VLCD
1.
2.
3.
4.
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn+1(t) - VBP1(t).
Voff(RMS) = 0.333VLCD.
mgl748
1
Figure 10. Waveforms for the 1:3 multiplex drive mode with ⁄3 bias
6.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see
Figure 11).
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
Tfr
BP0
VLCD
2VLCD / 3
LCD segments
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP2
BP3
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
Sn+2
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+3
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
state 1
2VLCD / 3
VLCD / 3
0V
- VLCD / 3
- 2VLCD / 3
- VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
- VLCD / 3
- 2VLCD / 3
- VLCD
1.
2.
3.
4.
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn+1(t) - VBP1(t).
Voff(RMS) = 0.333VLCD.
mgl749
1
Figure 11. Waveforms for the 1:4 multiplex drive mode with ⁄3 bias
6.5 Oscillator
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
6.5.1 Internal clock
The internal logic of the PCF8576D and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used
as the clock signal for several PCF8576Ds in the system that are connected in cascade.
6.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD
frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
6.6 Timing
The PCF8576D timing controls the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the correct timing relationship between each PCF8576D in
the system is maintained by the synchronization signal at pin SYNC. The timing also
generates the LCD frame signal whose frequency is derived from the clock frequency.
The frame signal frequency is a fixed division of the clock frequency from either the
internal or an external clock: .
6.7 Display register
The display latch holds the display data while the corresponding multiplex signals are
generated.
6.8 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
6.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must
be connected directly to the LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than four backplane outputs are
required, the unused outputs can be left open-circuit.
• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the
same signals and may also be paired to increase the drive capabilities.
• In static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
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6.10 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD segments/elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 12, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the
first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1,
BP2, and BP3 respectively.
display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
35
36
37
38
39
0
display RAM bits
1
(rows)/
backplane outputs
2
(BP)
3
mbe525
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Figure 12. Display RAM bit map
When display data is transmitted to the PCF8576D, the received display bytes are
stored in the display RAM in accordance with the selected LCD drive mode. The data
is stored as it arrives and depending on the current multiplex drive mode the bits are
stored singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example
of a 7-segment display showing all drive modes is given in Figure 13; the RAM filling
organization depicted applies equally to other LCD types.
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40 × 4 universal LCD driver for low multiplex rates
drive mode
LCD segments
Sn+2
static
Sn+3
a
multiplex
e
c
Sn
Sn+1
BP0
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
DP
b
f
e
Sn+2
BP1
c
DP
d
Sn+1
b
f
Sn
BP1
c
a
b
BP0
g
e
BP1
c
d
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
MSB
LSB
c b a
f
g e d DP
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
n
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
MSB
a b
LSB
f
g e c d DP
n
rows
display RAM 0 b
rows/backplane
1 DP
outputs (BP)
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
f
Sn+1
BP2
DP
d
multiplex
n+3
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
g
Sn
n+2
BP0
a
e
n+1
columns
display RAM address/segment outputs (s)
byte1
byte2
g
Sn+2
transmitted display byte
n
BP0
a
multiplex
1:4
Sn+1
Sn
Sn+7
d
Sn+3
1:3
b
g
Sn+6
1:2
display RAM filling order
columns
display RAM address/segment outputs (s)
byte1
f
Sn+4
Sn+5
LCD backplanes
DP
BP2
n
rows
display RAM 0 a
rows/backplane
1 c
BP3 outputs (BP) 2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged.
2
Figure 13. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I C-bus
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40 × 4 universal LCD driver for low multiplex rates
The following applies to Figure 13:
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0
and 1 as four successive 2-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 6.10.3).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
6.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 12). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 13. After each byte is stored, the content of the data
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
•
•
•
•
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
2
If an I C-bus data access terminates early then the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
6.10.2 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is
defined by the device-select command (see Table 13). If the content of the subaddress
counter and the hardware subaddress do not match then data storage is inhibited but the
data pointer is incremented as if data storage had taken place. The subaddress counter
is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576D occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on
2
the I C-bus interface.
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6.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 13 as
well).
Table 6. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the
display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 7.
Table 7. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
c1/d7 d4
d1/e7 e4
:
1
a6
a3
a0/b6 b3
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
2
a5
a2
b5
b2
c5
c2
d5
d2
e5
e2
:
3
-
-
-
-
-
-
-
-
-
-
:
3
4
5
6
7
8
9
:
In the case described in Table 7 the RAM has to be written entirely and BP2/S2, BP2/
S5, BP2/S8 etc. have to be connected to segments/elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and
b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some segments/elements remain unused or can be used, but it has to be considered in
the module layout process as well as in the driver software design.
6.10.4 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. If the PCF8576D is part of a cascade the
additional bits fall into the next device that also generates the acknowledge signal. If the
PCF8576D is a single device or the last device in a cascade the additional bits will be
discarded and no acknowledge signal will be generated.
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6.10.5 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The PCF8576D includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the
contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2
multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1.
This gives the provision for preparing display information in an alternative bank and to be
able to switch to it once it is assembled.
6.10.6 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive
mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command
(see Table 14). The input bank selector functions independently to the output bank
selector.
6.11 Blinking
The display blinking capabilities of the PCF8576D are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 15). The blink
frequencies are derived from the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 15).
An additional feature is for an arbitrary selection of LCD segments/elements to blink. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups
of LCD segments/elements can blink by selectively changing the display RAM data at
fixed time intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 11).
Table 8. Blinking frequencies
PCF8576D
Product data sheet
[1]
Blink mode
Normal operating mode ratio
Nominal blink frequency
off
-
blinking off
1
2 Hz
2
1 Hz
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Table 8. Blinking frequencies...continued
Blink mode
[1]
Normal operating mode ratio
Nominal blink frequency
3
[1]
0.5 Hz
Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator frequency
(fclk) of 1536 Hz (see Section 12).
6.12 Command decoder
2
The command decoder identifies command bytes that arrive on the I C-bus. The
commands available to the PCF8576D are defined in Table 9.
Table 9. Definition of PCF8576D commands
Command
Operation code
Bit
7
6
Reference
5
4
3
2
1
E
B
M[1:0]
mode-set
C
1
0
load-data-pointer
C
0
P[5:0]
device-select
C
1
1
0
0
A[2:0]
bank-select
C
1
1
1
1
0
I
blink-select
C
1
1
1
0
AB
BF[1:0]
[1]
-
[1]
0
Table 11
Table 12
Table 13
O
Table 14
Table 15
Not used.
All available commands carry a continuation bit C in their most significant bit position
as shown in Figure 19. When this bit is set logic 1, it indicates that the next byte of the
transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that
the command byte is the last in the transfer. Further bytes will be regarded as display
data (see Table 10).
Table 10. C bit description
Bit
Symbol
7
C
Value
Description
continue bit
0
last control byte in the transfer; next byte will be
regarded as display data
1
control bytes continue; next byte will be a command too
Table 11. Mode-set command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6, 5
-
10
fixed value
4
-
-
unused
3
E
[1]
display status
0
1
2
PCF8576D
Product data sheet
B
[2]
[3]
disabled (blank)
enabled
[4]
LCD bias configuration
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Table 11. Mode-set command bit description...continued
Bit
Symbol
Value
0
Description
[2]
1
1 to 0
⁄3 bias
1
⁄2 bias
LCD drive mode selection
M[1:0]
01
static; BP0
10
1:2 multiplex; BP0, BP1
11
00
[1]
[2]
[3]
[4]
1
1:3 multiplex; BP0, BP1, BP2
[2]
1:4 multiplex; BP0, BP1, BP2, BP3
The possibility to disable the display allows implementation of blinking under external control.
Default value.
The display is disabled by setting all backplane and segment outputs to VLCD.
Not applicable for static drive mode.
Table 12. Load-data-pointer command bit description
See Section 6.10.1.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6
-
0
5 to 0
[1]
P[5:0]
fixed value
[1]
000000
100111
to 6 bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
Default value.
Table 13. Device-select command bit description
See Section 6.10.2.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6 to 3
-
1100
2 to 0
[1]
A[2:0]
[1]
000
fixed value
to 111 3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware subaddresses
Default value.
Table 14. Bank-select command bit description
See Section 6.10.5 and Section 6.10.6.
Bit
Symbol
Value
Description
Static
PCF8576D
Product data sheet
7
C
0, 1
see Table 10
6 to 2
-
11110
fixed value
1
I
1:2 multiplex
[1]
input bank selection; storage of arriving display data
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Table 14. Bank-select command bit description...continued
See Section 6.10.5 and Section 6.10.6.
Bit
Symbol
Value
Description
Static
0
[2]
1
0
[1]
RAM row 0
RAM rows 0 and 1
RAM row 2
RAM rows 2 and 3
output bank selection; retrieval of LCD display data
O
0
[2]
1
[1]
[2]
1:2 multiplex
RAM row 0
RAM rows 0 and 1
RAM row 2
RAM rows 2 and 3
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
Default value.
Table 15. Blink-select command bit description
See Section 6.11.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6 to 3
-
1110
fixed value
2
AB
blink mode selection
0
[1]
1
1 to 0
alternate RAM bank blinking
[3]
blink frequency selection
BF[1:0]
00
[1]
[2]
[3]
[2]
normal blinking
[1]
off
01
1
10
2
11
3
Default value.
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
6.13 Display controller
The display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display data into the display RAM in the correct filling
order.
7
2
Characteristics of the I C-bus
2
The I C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor when connected to the
output stages of a device. Data transfer may be initiated only when the bus is not busy.
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7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal (see Figure 14).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Figure 14. Bit transfer
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the
START condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P.
The START and STOP conditions are illustrated in Figure 15.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc 622
Figure 15. Definition of START and STOP conditions
7.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the controller and the devices which
are controlled by the controller are the targets. The system configuration is shown in
Figure 16.
CONTROLLER
TRANSMITTER/
RECEIVER
TARGET
RECEIVER
TARGET
TRANSMITTER/
RECEIVER
CONTROLLER
TRANSMITTER
CONTROLLER
TRANSMITTER/
RECEIVER
SDA
SCL
mga807
Figure 16. System configuration
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7.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A target receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A controller receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the target transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A controller receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the target. In this event, the
transmitter must leave the data line HIGH to enable the controller to generate a STOP
condition.
2
Acknowledgement on the I C-bus is illustrated in Figure 17.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL
from controller
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
2
Figure 17. Acknowledgement of the I C-bus
2
7.5 I C-bus controller
2
2
The PCF8576D acts as an I C-bus target receiver. It does not initiate I C-bus transfers or
2
transmit data to an I C-bus controller receiver. The only data output from the PCF8576D
are the acknowledge signals of the selected devices. Device selection depends on
2
the I C-bus target address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so
2
that no two devices with a common I C-bus target address have the same hardware
subaddress.
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7.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
2
7.7 I C-bus protocol
2
Two I C-bus target addresses (0111 000 and 0111 001) are used to address the
2
PCF8576D. The entire I C-bus target address byte is shown in Table 16.
2
Table 16. I C controller address byte
controller address
7
Bit
6
5
4
3
2
0
1
MSB
0
LSB
1
1
1
0
0
SA0
R/W
The PCF8576D is a write-only device and will not respond to a read access, therefore bit
0 should always be logic 0. Bit 1 of the target address byte that a PCF8576D will respond
to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
2
Having two reserved target addresses allows the following on the same I C-bus:
• Up to 16 PCF8576D for very large LCD applications
• The use of two types of LCD multiplex drive
2
The I C-bus protocol is shown in Figure 18. The sequence is initiated with a START
2
condition (S) from the I C-bus controller which is followed by one of two possible
PCF8576D target addresses available. All PCF8576Ds whose SA0 inputs correspond to
2
bit 0 of the target address respond by asserting an acknowledge in parallel. This I C-bus
transfer is ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.
R/W
acknowledge
by A0, A1 and A2
selected
PCF8576D only
acknowledge by
all addressed
PCF8576Ds
target address
S
S 0 1 1 1 0 0 A 0 A C
0
1 byte
COMMAND
A
n ≥ 1 byte(s)
DISPLAY DATA
A
P
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
mdb078
2
Figure 18. I C-bus protocol
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8576D.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 19). The command bytes are also acknowledged by all addressed
PCF8576D on the bus.
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
MSB
C
LSB
REST OF OPCODE
msa833
Figure 19. Format of command byte
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and
the subaddress counter. Both data pointer and subaddress counter are automatically
updated and the data directed to the intended PCF8576D device.
An acknowledgement after each byte is asserted only by the PCF8576Ds that are
2
addressed via address lines A0, A1, and A2. After the last display byte, the I C-bus
controller asserts a STOP condition (P). Alternately a START may be asserted to restart
2
an I C-bus access.
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
8
Internal circuitry
VDD
VDD
VSS
VSS
SA0
VDD
CLK
SCL
VSS
VDD
VSS
OSC
VSS
VDD
SDA
SYNC
VSS
VSS
VDD
A0, A1, T1
VSS
VLCD
BP0, BP1,
BP2, BP3
VSS
VLCD
VLCD
S0 to S39
VSS
VSS
mdb076
Figure 20. Device protection circuits
9
Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
CAUTION
Static voltages across the liquid crystal display can build up when the LCD
supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice
versa. This may cause unwanted display artifacts. To avoid such artifacts,
VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the
IC to malfunction. The IC must be protected against light. The protection must
be applied to all sides of the IC.
10 Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VDD
supply voltage
-0.5
+6.5
V
VLCD
LCD supply voltage
-0.5
+7.5
V
VI
input voltage
on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0 to A2
-0.5
+6.5
V
VO
output voltage
on each of the pins S0 to
S39, BP0 to BP3
-0.5
+7.5
V
II
input current
-10
+10
mA
IO
output current
-10
+10
mA
IDD
supply current
-50
+50
mA
IDD(LCD)
LCD supply current
-50
+50
mA
ISS
ground supply current
-50
+50
mA
Ptot
total power dissipation
-
400
mW
Po
output power
Conditions
-
100
mW
HBM
[1]
-
±5 000
V
MM
[2]
-
±200
V
CDM
[3]
-
±1 500
V
latch-up current
[4]
-
200
mA
Tstg
storage temperature
[5]
-65
+150
°C
Tamb
ambient temperature
-40
+85
°C
VESD
Ilu
[1]
[2]
[3]
[4]
[5]
electrostatic discharge
voltage
operating device
Pass level; Human Body Model (HBM) according to [1].
Pass level; Machine Model (MM), according to [2].
Pass level; Charged-Device Model (CDM), according to [3].
Pass level; latch-up testing according to [4] at maximum ambient temperature (Tamb(max)).
According to the store and transport requirements (see [6]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to
75 %.
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
11 Static characteristics
Table 18. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
VLCD
IDD
1.8
-
5.5
V
LCD supply voltage
[1]
2.5
-
6.5
V
supply current
[2]
-
3.5
7
μA
-
2.7
-
μA
-
23
32
μA
-
13
-
μA
1.0
1.3
1.6
V
VSS
-
0.3VDD
V
0.7VDD
-
VDD
V
on pins CLK and SYNC
1
-
-
mA
on pin SDA
3
-
-
mA
fclk(ext) = 1536 Hz
VDD = 3.0 V; Tamb = 25
°C
IDD(LCD)
LCD supply current
fclk(ext) = 1536 Hz
[2]
VDD(LCD) = 3.0 V; Tamb =
25 °C
[3]
Logic
VP(POR)
power-on reset supply
voltage
VIL
LOW-level input voltage
on pins CLK, SYNC, OSC,
A0 to A2, SA0, SCL, SDA
VIH
HIGH-level input voltage
on pins CLK, SYNC, OSC,
A0 to A2, SA0, SCL, SDA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V; VDD = 5 V
[4][5]
IOH(CLK)
HIGH-level output current
on pin CLK
output source current;
VOH = 4.6 V; VDD = 5 V
1
-
-
mA
IL
leakage current
VI = VDD or VSS;
on pins CLK, SCL, SDA, A0
to A2 and SA0
-1
-
+1
μA
IL(OSC)
leakage current on pin
OSC
VI = VDD
-1
-
+1
μA
CI
input capacitance
-
-
7
pF
-100
-
+100
mV
on pins BP0 to BP3
-
1.5
-
kΩ
on pins S0 to S39
-
6.0
-
kΩ
[6]
LCD outputs
ΔVO
output voltage variation
on pins BP0 to BP3 and
S0 to S39
RO
output resistance
VLCD = 5 V
[1]
[2]
[3]
[4]
[5]
[7]
1
VLCD > 3 V for ⁄3 bias.
2
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I C-bus inactive.
2
The I C-bus interface of PCF8576D is 5 V tolerant.
2
When tested, I C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 17.
Propagation delay of driver between clock (CLK) and LCD driving signals.
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
[6]
[7]
Periodically sampled, not 100 % tested.
Outputs measured one at a time.
12 Dynamic characteristics
Table 19. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1440
1850
2640
Hz
Clock
[1]
fclk(int)
internal clock frequency
fclk(ext)
external clock frequency
960
-
2640
Hz
tclk(H)
HIGH-level clock time
60
-
-
μs
tclk(L)
LOW-level clock time
60
-
-
μs
-
30
-
ns
1
-
-
μs
-
-
30
μs
Synchronization
tPD(SYNC_N) SYNC propagation delay
tSYNC_NL
tPD(drv)
2
I C-bus
SYNC LOW time
driver propagation delay
VLCD = 5 V
[2]
[3]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL
clock
1.3
-
-
μs
tHIGH
HIGH period of the SCL
clock
0.6
-
-
μs
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between
a STOP and START
condition
1.3
-
-
μs
tSU;STO
set-up time for STOP
condition
0.6
-
-
μs
tHD;STA
hold time (repeated)
START condition
0.6
-
-
μs
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
μs
tr
rise time of both SDA and
SCL signals
fSCL = 400 kHz
-
-
0.3
μs
fSCL < 125 kHz
-
-
1.0
μs
tf
fall time of both SDA and
SCL signals
-
-
0.3
μs
Cb
capacitive load for each
bus line
-
-
400
pF
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
Table 19. Dynamic characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
tw(spike)
[1]
[2]
[3]
Parameter
Conditions
2
spike pulse width
on the I C-bus
Min
Typ
Max
Unit
-
-
50
ns
Typical output duty factor: 50 % measured at the CLK output pin.
Not tested in production.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage
swing of VSS to VDD.
tclk(H)
1 / fCLK
tclk(L)
0.7 VDD
CLK
0.3 VDD
0.7 VDD
SYNC
0.3 VDD
tPD(SYNC_N)
tSYNC_NL
0.5 V
BP0 to BP3,
and S0 to S39
(VDD = 5 V)
0.5 V
tPD(drv)
001aai163
Figure 21. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
mga728
2
Figure 22. I C-bus timing waveforms
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
13 Application information
13.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the
2
same I C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
2
programmable I C-bus target address (SA0).
Table 20. Addressing cascaded PCF8576D
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0
0
0
8
0
0
1
9
0
1
0
10
0
1
1
11
1
0
0
12
1
0
1
13
1
1
0
14
1
1
1
15
2
1
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from
only one device in the cascade to be shared. This arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be throughplated to the backplane electrodes of the display. The other PCF8576D of the cascade
contribute additional segment outputs. The backplanes can either be connected together
to enhance the drive capability or some can be left open-circuit (such as the ones from
the target in Figure 23) or just some of the controller and some of the target will be taken
to facilitate the layout of the display.
All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.
This synchronization is guaranteed after the power-on reset. The only time that SYNC
is likely to be needed is if synchronization is lost accidentally, for example, by noise in
adverse electrical environments, or if the LCD multiplex drive mode is changed in an
application using several cascaded PCF8576Ds, as the drive mode cannot be changed
on all of the cascaded devices simultaneously. SYNC can be either an input or an output
signal; a SYNC output is implemented as an open-drain driver with an internal pull-up
resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and
monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
by the first PCF8576D to assert SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for each LCD drive mode is shown in Figure 24.
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 21.
Table 21. SYNC contact resistance
Number of devices
Maximum contact resistance
2
6 kΩ
3 to 5
2.2 kΩ
6 to 10
1.2 kΩ
10 to 16
700 Ω
The PCF8576D can be cascaded with the PCF8562. This allows optimal drive selection
for a given number of pixels to display. Figure 21 and Figure 22 show the timing of the
synchronization signals.
VDD
VLCD
6
SDA 1, 58, 59
SCL 2, 3
SYNC
4
CLK
13
40 segment drives
LCD PANEL
PCF8576DU
5
OSC 7
8
9
A0
10 11 12
A1 A2 SA0 VSS
BP0 to BP3
(open-circuit)
(up to 2560
elements)
VLCD
VDD
R≤
HOST
MICROPROCESSOR/
MICROCONTROLLER
tr
2CB
VDD
SDA
SCL
SYNC
CLK
OSC
6
1, 58, 59
13
40 segment drives
2, 3
4
PCF8576DU
5
4 backplanes
BP0 to BP3
7
mdb077
8
VSS
VLCD
A0
9
A1
10
11
A2
12
SA0 VSS
Figure 23. Cascaded PCF8576D configuration
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
Tfr =
1
ffr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Figure 24. Synchronization of the cascade for the various PCF8576D drive modes
14 Test information
The following quality information corresponds with the product type: PCF8576DT/S400/2
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
15 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3 )
A1
pin 1 index
A
θ
Lp
L
1
28
w M
bp
e
detail X
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Figure 25. Package outline SOT364-1 (TSSOP56) of PCF8576DT
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
16 Bare die outline
Wire bond die; 59 bonding pads
PCF8576DU/DA
D
A
35
(1)
22
21
36
x
0
e
E
0
y
X
51
9
C2
52
59 1
8
C1
P4
P3
P2
P1
detail X
0
0.5
1 mm
scale
Notes
1. Marking code: PC8576D-2
Outline
version
pcf8576du_da_do
References
IEC
JEDEC
JEITA
European
projection
Issue date
08-12-10
10-12-20
PCF8576DU/DA
Figure 26. Bare die outline PCF8576DU/DA (for dimensions see Table 23)
PCF8576D
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Bare die; 59 bumps
PCF8576DU/2DA
D
35
(1)
22
21
36
x
0
Y
e
E
0
y
51
9
C2
52
X
59 1
8
C1
L
A
b
detail X
A2
A1
detail Y
0
0.5
1 mm
scale
Notes
1. Marking code: PC8576D-2
Outline
version
pcf8576du_2da_do
References
IEC
JEDEC
JEITA
European
projection
Issue date
08-12-10
10-12-20
PCF8576DU/2DA
Figure 27. Bare die outline PCF8576DU/2DA (for dimensions see Table 24)
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Table 22. Dimensions of PCF8576DU/DA
Original dimensions are in mm.
Unit (mm)
A
D
E
e
max
-
-
-
nom
0.38
2.2
min
-
-
[1]
[2]
[3]
[1]
[2]
[3]
[2]
[3]
P1
P2
P3
P4
-
-
-
-
-
2.0
-
0.09
0.08
0.066
0.056
-
0.072
-
-
-
-
Dimension not drawn to scale.
Pad size.
Passivation opening.
Table 23. Dimensions of PCF8576DU/2DA
Original dimensions are in mm.
[1]
Unit (mm)
A
A1
A2
b
D
E
e
max
-
0.012
-
-
-
-
-
-
nom
0.40
0.015
0.381
0.052
2.2
2.0
-
0.077
min
-
0.018
-
-
-
-
0.072
-
[1]
L
Dimension not drawn to scale.
Table 24. Bonding pad location for PCF8576DU/x
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y =
0) of the chip (see Figure 3, Figure 26 and Figure 27).
PCF8576D
Product data sheet
Symbol
Pad
X (μm)
Y (μm)
Description
SDA
1
-34.38
-876.6
I C-bus serial data input/output
SCL
2
109.53
-876.6
I C-bus serial clock input
SCL
3
181.53
-876.6
SYNC
4
365.58
-876.6
cascade synchronization input/output
CLK
5
469.08
-876.6
external clock input/output
VDD
6
577.08
-876.6
supply voltage
OSC
7
740.88
-876.6
internal oscillator enable input
A0
8
835.83
-876.6
subaddress inputs
A1
9
1 005.48
-630.9
A2
10
1 005.48
-513.9
SA0
11
1 005.48
-396.9
I C-bus address input; bit 0
VSS
12
1 005.48
-221.4
ground supply voltage
VLCD
13
1 005.48
10.71
LCD supply voltage
BP0
14
1 005.48
156.51
LCD backplane outputs
BP2
15
1 005.48
232.74
BP1
16
1 005.48
308.97
BP3
17
1 005.48
385.2
2
2
2
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40 × 4 universal LCD driver for low multiplex rates
Table 24. Bonding pad location for PCF8576DU/x...continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y =
0) of the chip (see Figure 3, Figure 26 and Figure 27).
PCF8576D
Product data sheet
Symbol
Pad
X (μm)
Y (μm)
Description
S0
18
1 005.48
493.2
LCD segment outputs
S1
19
1 005.48
565.2
S2
20
1 005.48
637.2
S3
21
1 005.48
709.2
S4
22
347.22
876.6
S5
23
263.97
876.6
S6
24
180.72
876.6
S7
25
97.47
876.6
S8
26
14.22
876.6
S9
27
-69.03
876.6
S10
28
-152.28
876.6
S11
29
-235.53
876.6
S12
30
-318.78
876.6
S13
31
-402.03
876.6
S14
32
-485.28
876.6
S15
33
-568.53
876.6
S16
34
-651.78
876.6
S17
35
-735.03
876.6
S18
36
-1 005.5
625.59
S19
37
-1 005.5
541.62
S20
38
-1 005.5
458.19
S21
39
-1 005.5
374.76
S22
40
-1 005.5
291.33
S23
41
-1 005.5
207.9
S24
42
-1 005.5
124.47
S25
43
-1 005.5
41.04
S26
44
-1 005.5
-42.39
S27
45
-1 005.5
-125.8
S28
46
-1 005.5
-209.3
S29
47
-1 005.5
-292.7
S30
48
-1 005.5
-376.1
S31
49
-1 005.5
-459.5
S32
50
-1 005.5
-543
S33
51
-1 005.5
-625.6
S34
52
-735.03
-876.6
LCD segment outputs
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
Table 24. Bonding pad location for PCF8576DU/x...continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y =
0) of the chip (see Figure 3, Figure 26 and Figure 27).
Symbol
Pad
X (μm)
Y (μm)
S35
53
-663.03
-876.6
S36
54
-591.03
-876.6
S37
55
-519.03
-876.6
S38
56
-447.03
-876.6
S39
57
-375.03
-876.6
SDA
58
-196.38
-876.6
SDA
59
-106.38
-876.6
Description
2
I C-bus serial data input/output
Table 25. Alignment marks
All x/y coordinates represent the position of the center of each alignment mark with respect to the
center (x/y = 0) of the chip (see Figure 3, Figure 26 and Figure 27).
Symbol
Dimension
Location
X (μm)
Y (μm)
Diameter (μm)
C1
930.42
-870.3
72
C2
-829.98
-870.3
72
17 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
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Product data sheet
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PCF8576D
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40 × 4 universal LCD driver for low multiplex rates
18 Packing information
18.1 Tray information
C
J
A
H
A
1.1
2.1
1.2
2.2
3.1
x.1
B
A
1.3
K
F
E
1.y
D
y
G
x
F
E
C
O
N
L
M
SECTION A-A
X
detail X
Dimensions in mm
aaa-003344
Figure 28. Tray details
Table 26. Description of tray details
Tray details are shown in Figure 28.
Tray details
Dimensions
A
B
C
D
E
F
G
H
J
K
L
M
N
Unit
3.6
3.6
2.36
2.11
50.8
45.72
39.6
5.6
5.6
39.6
3.96
2.18
2.49
mm
Number of pockets
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Product data sheet
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40 × 4 universal LCD driver for low multiplex rates
Table 26. Description of tray details...continued
Tray details are shown in Figure 28.
Tray details
x direction
y direction
12
12
marking code
aaa-004969
Figure 29. Tray alignment
18.2 Tape and reel information
For tape and reel packing information, please see [5].
19 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
19.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
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• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
19.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 27 and Table 28
Table 27. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
PCF8576D
Product data sheet
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
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40 × 4 universal LCD driver for low multiplex rates
Table 28. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 30.
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
20 Appendix
20.1 LCD segment driver selection
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Table 29. Selection of LCD segment drivers
Type name
PCA8553DTT
PCA8546ATT
PCA8546BTT
PCA8547AHT
PCA8547BHT
PCF85134HL
PCA85134H
PCA8543AHL
PCF8545ATT
PCF8545BTT
PCF8536AT
PCF8536BT
PCA8536AT
PCA8536BT
PCF8537AH
PCF8537BH
PCA8537AH
PCA8537BH
PCA9620H
PCA9620U
PCF8576DU
PCF8576EUG
PCA8576FUG
PCF85133U
PCF8576D
Product data sheet
Number of elements at MUX
1:1
1:2
1:3
1:4
1:6
1:8
1:9
40
80
120
160
-
-
-
44
44
60
60
60
44
44
44
44
60
60
40
40
40
80
88
88
120
120
120
88
88
88
88
120
120
80
80
80
160
180
180
120
120
120
240
176
176
176
176
240
240
240
176
176
176
176
176
176
176
176
176
176
240
240
160
160
160
320
252
252
252
252
252
252
276
276
276
276
320
320
-
320
320
320
320
320
320
352
352
352
352
480
480
-
-
VDD (V)
VLCD (V)
ffr (Hz)
1.8 to 5.5
1.8 to 5.5
32 to 256
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 6.5
2.5 to 8
2.5 to 9
2.5 to 5.5
2.5 to 5.5
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 6.5
2.5 to 6.5
2.5 to 8
2.5 to 6.5
[1]
VLCD (V)
temperature
compensat.
Tamb (°C)
Interface
Package
AECQ100
N
N
-40 to 105
I C / SPI
2
TSSOP56
Y
2
[1]
N
N
-40 to 95
I C
TSSOP56
Y
[1]
N
N
-40 to 95
SPI
TSSOP56
Y
60 to 300
60 to 300
[1]
Y
Y
-40 to 95
I C
TQFP64
Y
[1]
Y
Y
-40 to 95
SPI
60 to 300
60 to 300
82
N
82
N
[1]
60 to 300
Y
N
N
Y
2
TQFP64
Y
-40 to 85
2
I C
LQFP80
N
-40 to 95
2
I C
LQFP80
Y
2
LQFP80
Y
2
-40 to 105
I C
[1]
N
N
-40 to 85
I C
TSSOP56
N
[1]
N
N
-40 to 85
SPI
TSSOP56
N
60 to 300
60 to 300
[1]
N
N
-40 to 85
I C
TSSOP56
N
[1]
N
N
-40 to 85
SPI
TSSOP56
N
60 to 300
60 to 300
2
[1]
N
N
-40 to 95
I C
TSSOP56
Y
[1]
N
N
-40 to 95
SPI
TSSOP56
Y
60 to 300
60 to 300
2
[1]
Y
Y
-40 to 85
I C
TQFP64
N
[1]
Y
Y
-40 to 85
SPI
TQFP64
N
60 to 300
60 to 300
2
[1]
Y
Y
-40 to 95
I C
TQFP64
Y
[1]
Y
Y
-40 to 95
SPI
60 to 300
60 to 300
[1]
60 to 300
[1]
60 to 300
77
Y
Y
N
77
N
200
82, 110
VLCD (V)
charge
pump
N
[2]
N
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Rev. 15.1 — 1 September 2021
Y
Y
N
N
N
N
2
TQFP64
Y
-40 to 105
2
I C
LQFP80
Y
-40 to 105
2
I C
Bare die
Y
-40 to 85
2
I C
Bare die
N
-40 to 85
2
I C
Bare die
N
2
I C
Bare die
Y
2
Bare die
N
-40 to 105
-40 to 85
I C
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Table 29. Selection of LCD segment drivers...continued
Type name
PCA85133U
PCA85233UG
PCF85132U
PCA8530DUG
PCA85132U
PCA85232U
PCF8538UG
PCA8538UG
[1]
[2]
Number of elements at MUX
1:1
1:2
1:3
1:4
1:6
1:8
1:9
80
160
240
320
-
-
-
80
160
102
160
160
102
102
160
320
204
320
320
204
204
240
480
480
480
-
320
640
408
640
640
408
408
612
612
816
816
918
918
VDD (V)
VLCD (V)
ffr (Hz)
1.8 to 5.5
2.5 to 8
82, 110
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 8
1.8 to 8
4 to 12
1.8 to 8
1.8 to 8
4 to 12
4 to 12
[2]
[2]
150, 220
60 to 90
[1]
VLCD (V)
temperature
compensat.
Tamb (°C)
Interface
N
N
-40 to 95
N
N
[1]
45 to 300
60 to 90
VLCD (V)
charge
pump
[1]
Y
N
[1]
117 to 176
[1]
45 to 300
[1]
45 to 300
N
Y
Y
N
N
Y
N
N
Y
Y
Package
AECQ100
I C
2
Bare die
Y
2
I C
Bare die
Y
2
I C
Bare die
N
2
Bare die
Y
-40 to 95
2
I C
Bare die
Y
-40 to 95
2
I C
Bare die
Y
-40 to 85
2
Bare die
N
2
Bare die
Y
-40 to 105
-40 to 85
-40 to 105
-40 to 105
I C / SPI
I C / SPI
I C / SPI
Software programmable.
Hardware selectable.
PCF8576D
Product data sheet
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40 × 4 universal LCD driver for low multiplex rates
21 Abbreviations
Table 30. Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
HBM
Human Body Model
ITO
Indium Tin Oxide
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
PCB
Printed Circuit Board
RAM
Random Access Memory
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface Mount Device
22 References
[1]
[2]
[3]
[4]
[5]
[6]
JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM)
JESD22-A115 Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
JESD22-C101 Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components
JESD78 IC Latch-Up Test
SOT364-1_118 TSSOP56; Reel pack; SMD, 13", packing information
UM10569 Store and transport requirements
23 Revision history
Table 31. Revision history
Document ID
Release date
Data sheet status
Change notice
PCF8576D v.15.1
20210901
Product data sheet
PCN202102010F01 PCF8576D v.15
Modifications:
• Updated ordering information. See PCN number in Change notice column.
• Updated text and Figures 16, 17, and 18, changing the terms "master" and "slave" to
"controller" and "target" to comply with NXP inclusive language policy.
PCF8576D v.15
20150212
PCF8576D
Product data sheet
Product data sheet
-
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Rev. 15.1 — 1 September 2021
Supersedes
PCF8576D v.14
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PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Table 31. Revision history...continued
Document ID
Release date
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Changed IDD(LCD) values in Table 18
• Changed Section 13.1 and Section 18.2
• Added Section 20.1
• Fixed typos
PCF8576D v.14
20130610
Product data sheet
-
PCF8576D v.13
PCF8576D v.13
20120510
Product data sheet
-
PCF8576D v.12
PCF8576D v.12
20120413
Product data sheet
-
PCF8576D v.11
PCF8576D v.11
20110627
Product data sheet
PCF8576D v.10
20110214
Product data sheet
-
PCF8576D_9
PCF8576D_9
20090825
Product data sheet
-
PCF8576D_8
PCF8576D_8
20090319
Product data sheet
-
PCF8576D_7
PCF8576D_7
20081218
Product data sheet
-
PCF8576D_6
PCF8576D_6
20081202
Product data sheet
-
PCF8576D_5
PCF8576D_5
20041222
Product specification
-
PCF8576D_4
PCF8576D_4
20041008
Product specification
-
PCF8576D_3
PCF8576D_3
20040617
Product specification
-
PCF8576D_2
PCF8576D_2
20030623
Product specification
-
PCF8576D_1
PCF8576D_1
20030401
Objective specification
-
-
PCF8576D
Product data sheet
Data sheet status
Change notice
Supersedes
PCF8576D v.10
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40 × 4 universal LCD driver for low multiplex rates
24 Legal information
24.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
24.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
PCF8576D
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 15.1 — 1 September 2021
© NXP B.V. 2021. All rights reserved.
51 / 54
PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing
and are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed,
these will be separately indicated in the data sheet. There are no postpacking tests performed on individual die or wafers. NXP Semiconductors
has no control of third party procedures in the sawing, handling, packing or
assembly of the die. Accordingly, NXP Semiconductors assumes no liability
for device functionality or performance of the die or systems after third party
sawing, handling, packing or assembly of the die. It is the responsibility of
the customer to test and qualify their application in which the die is used.
All die sales are conditioned upon and subject to the customer entering into
a written die sale agreement with NXP Semiconductors through its legal
department.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
PCF8576D
Product data sheet
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
24.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
2
I C-bus — logo is a trademark of NXP B.V.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 15.1 — 1 September 2021
© NXP B.V. 2021. All rights reserved.
52 / 54
PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Ordering information ..........................................2
Ordering options ................................................2
Pin description ...................................................5
Selection of possible display configurations ...... 7
Biasing characteristics .......................................8
Standard RAM filling in 1:3 multiplex drive
mode ............................................................... 20
Entire RAM filling by rewriting in 1:3
multiplex drive mode ....................................... 20
Blinking frequencies ........................................ 21
Definition of PCF8576D commands ................ 22
C bit description .............................................. 22
Mode-set command bit description ................. 22
Load-data-pointer command bit description .... 23
Device-select command bit description ........... 23
Bank-select command bit description ..............23
Blink-select command bit description .............. 24
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Tab. 31.
I2C controller address byte ............................. 27
Limiting values ................................................ 30
Static characteristics ....................................... 31
Dynamic characteristics .................................. 32
Addressing cascaded PCF8576D ................... 34
SYNC contact resistance ................................ 35
Dimensions of PCF8576DU/DA ...................... 40
Dimensions of PCF8576DU/2DA .................... 40
Bonding pad location for PCF8576DU/x ..........40
Alignment marks ............................................. 42
Description of tray details ................................43
SnPb eutectic process (from J-STD-020D) ..... 45
Lead-free process (from J-STD-020D) ............ 46
Selection of LCD segment drivers ...................47
Abbreviations ...................................................49
Revision history ...............................................49
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Definition of START and STOP conditions ...... 25
System configuration .......................................25
Acknowledgement of the I2C-bus ................... 26
I2C-bus protocol .............................................. 27
Format of command byte ................................ 28
Device protection circuits ................................ 29
Driver timing waveforms ..................................33
I2C-bus timing waveforms ...............................33
Cascaded PCF8576D configuration ................ 35
Synchronization of the cascade for the
various PCF8576D drive modes ..................... 36
Package outline SOT364-1 (TSSOP56) of
PCF8576DT .....................................................37
Bare die outline PCF8576DU/DA (for
dimensions see Table 23) ............................... 38
Bare die outline PCF8576DU/2DA (for
dimensions see Table 24) ............................... 39
Tray details ......................................................43
Tray alignment .................................................44
Temperature profiles for large and small
components ..................................................... 46
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Block diagram of PCF8576D .............................3
Pinning diagram for PCF8576DT
(TSSOP56) ........................................................ 4
Pinning diagram for PCF8576DU (bare die) ......5
Example of displays suitable for PCF8576D ..... 6
Typical system configuration ............................. 7
Electro-optical characteristic: relative
transmission curve of the liquid .......................10
Static drive mode waveforms .......................... 11
Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias .................................................... 12
Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias .................................................... 13
Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias .................................................... 14
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias .................................................... 15
Display RAM bit map ...................................... 17
Relationship between LCD layout, drive
mode, display RAM filling order and display
data transmitted over the I2C-bus ................... 18
Bit transfer .......................................................25
PCF8576D
Product data sheet
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
All information provided in this document is subject to legal disclaimers.
Rev. 15.1 — 1 September 2021
© NXP B.V. 2021. All rights reserved.
53 / 54
PCF8576D
NXP Semiconductors
40 × 4 universal LCD driver for low multiplex rates
Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.3.1
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.6
6.7
6.8
6.9
6.10
6.10.1
6.10.2
6.10.3
6.10.4
6.10.5
6.10.6
6.11
6.12
6.13
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
10
11
12
13
13.1
14
14.1
15
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 5
Functional description ........................................6
Power-On Reset (POR) .....................................7
LCD bias generator ........................................... 8
LCD voltage selector ......................................... 8
Electro-optical performance ............................... 9
LCD drive mode waveforms ............................ 10
Static drive mode .............................................10
1:2 Multiplex drive mode ................................. 11
1:3 Multiplex drive mode ................................. 13
1:4 Multiplex drive mode ................................. 14
Oscillator .......................................................... 15
Internal clock ................................................... 16
External clock .................................................. 16
Timing .............................................................. 16
Display register ................................................ 16
Segment outputs ............................................. 16
Backplane outputs ........................................... 16
Display RAM ....................................................17
Data pointer ..................................................... 19
Subaddress counter .........................................19
RAM writing in 1:3 multiplex drive mode ..........20
Writing over the RAM address boundary ......... 20
Output bank selector ....................................... 21
Input bank selector .......................................... 21
Blinking ............................................................ 21
Command decoder .......................................... 22
Display controller ............................................. 24
Characteristics of the I2C-bus ......................... 24
Bit transfer ....................................................... 25
START and STOP conditions .......................... 25
System configuration ....................................... 25
Acknowledge ....................................................26
I2C-bus controller ............................................ 26
Input filters ....................................................... 27
I2C-bus protocol .............................................. 27
Internal circuitry ................................................ 29
Safety notes .......................................................29
Limiting values .................................................. 30
Static characteristics ........................................ 31
Dynamic characteristics ...................................32
Application information .................................... 34
Cascaded operation .........................................34
Test information ................................................ 36
Quality information ...........................................36
Package outline .................................................37
16
17
18
18.1
18.2
19
19.1
19.2
19.3
19.4
20
20.1
21
22
23
24
Bare die outline .................................................38
Handling information ........................................ 42
Packing information ..........................................43
Tray information ...............................................43
Tape and reel information ................................44
Soldering of SMD packages .............................44
Introduction to soldering .................................. 44
Wave and reflow soldering .............................. 44
Wave soldering ................................................ 45
Reflow soldering .............................................. 45
Appendix ............................................................ 46
LCD segment driver selection ......................... 46
Abbreviations .................................................... 49
References ......................................................... 49
Revision history ................................................ 49
Legal information .............................................. 51
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 September 2021
Document identifier: PCF8576D
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