PCF8811

PCF8811 80 x 128 pixels matrix LCD driver Rev. 04 — 27 June 2008 Product data sheet 1. General description The PCF8811 is a low-power CMOS LCD controller driver, designed to drive a graphic display of 80 rows and 128 columns or a graphic display of 79 rows and 128 columns and an icon row of 128 symbols. All necessary functions for the display are provided in a single chip, including on-chip generation of the LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8811 can interface microcontrollers via a parallel bus, serial bus or I2C-bus interface. 2. Features I I I I I I I Single-chip LCD controller/driver 80 row and 128 column outputs Display data RAM 80 × 128 bit 128 icons (row 80 can be used for icons in extended command set and when icon rows are enabled) Low power consumption; suitable for battery operated systems An 8-bit parallel interface, 3 or 4-line Serial Peripheral Interface (SPI) and high-speed I2C-bus On-chip: N Configurable voltage multiplier generating LCD supply voltage VLCD; an external VLCD is also possible N Linear temperature compensation of VLCD; 8 programmable temperature coefficients (extended command set); one fixed temperature coefficient which can be set as default by OTP programming (basic command set) N Generation of intermediate LCD bias voltage N Oscillator requires no external components OTP calibration for VLCD and accurate frame frequency External reset input pad External clock input possible Multiplex rate: 1:16 to 1:80 in steps of 8 when no icon row is used, with the icon row steps of 16 can be used Logic supply voltage range VDD1 to VSS: N 1.7 V to 3.3 V High-voltage multiplier supply voltage range VDD2, VDD3 to VSS: N 1.8 V to 3.3 V Display supply voltage range VLCD to VSS: N 3 V to 9 V I I I I I I I NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver I Programmable bottom row pads mirroring; for compatibility with both Tape Carrier Packages (TCP) and Chip-On-Glass (COG) applications (extended command set) I Status read, which allows for chip recognition and content checking of some registers I Start address line which allows, for instance, the scrolling of the displayed image I Programmable display RAM pointers for variable display sizes I Slim chip layout, suited for COG applications I Temperature range: Tamb = −40 °C to +85 °C I CMOS compatible inputs 3. Applications I I I I Automotive displays Telecom equipment Portable instruments Point-of-sale terminals 4. Ordering information Table 1. Ordering information Package Name PCF8811U/2DA/1 PCF8811MU/2DA/1 Description chip with bumps in tray (not covered by Motif license agreement) chip with bumps in tray (sold under license from Motif) Version Type number PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 2 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 5. Block diagram VDD1 VDD2 VDD3 C0 to C127 R0 to R79 128 80 COLUMN DRIVERS ROW DRIVERS VLCDIN BIAS VOLTAGE GENERATOR DATA PROCESSING VSS1 VSS2 VOTPPROG VLCDSENSE VLCDOUT T1 T2 T3 T4 T5 MF[2:0] DS0 3 ORTHOGONAL FUNCTION GENERATOR RESET HIGH VOLTAGE GENERATOR DISPLAY DATA RAM 80 × 128 BITS OSCILLATOR RES OSC TIMING GENERATOR ADDRESS COUNTER DISPLAY ADDRESS COUNTER COMMAND DECODER PCF8811 I/O BUFFER PARALLEL/SERIAL/I2C-BUS INTERFACE 5 3 mgw732 DB7/SDATA DB5/SDO DB4 DB3/SA1 DB2/SA0 DB1 Fig 1. Block diagram of PCF8811 PCF8811_4 SCLH/SCE SDAHOUT DB6/SCLK VOS[4:0] PS[2:0] E/RD R/W SDAH EXT DB0 D/C © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 3 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 6. Pinning information 6.1 Pinning VLCDSENSE VLCDOUT VLCDIN VDD3 VDD2 VOS0 VOS1 VOS2 VOS3 VOS4 T3 T4 T1 T2 T5 PCF8811 DB7/SDATA DB6/SCLK DB5/SDO DB4 DB3/SA1 DB2/SA0 DB1 DB0 VDD(tie-off)(1) E/RD R/W/WR D/C RES VOTPPROG SCLH/SCE SDAHOUT SDAH VSS(tie-off)(1) PS2 PS1 PS0 EXT OSC DS0 MF0 MF1 MF2 40 VDD1 VSS2 VSS1 y x 0,0 mgw769 (1) VSS(tie-off) and VDD(tie-off) are used for local tie-offs. Fig 2. Bonding pad locations for PCF8811 (bottom view) PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 1 4 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Pad allocation table Symbol MF2 MF1 MF0 DS0 OSC EXT PS0 PS1 PS2 VSS(tie-off) SDAHOUT SDAH SCLH/SCE VOTPPROG RES D/C R/W/WR E/RD VDD(tie-off) DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SDO Pad 38 39 40 to 45 46 to 55 56 to 60 61 to 70 71 to 80 81 82 83 84 85 86 87 88 89 90 91 to 99 100 101 to 107 108 to 114 115 to 154 155 156 to 283 284 to 323 324 to 333 Symbol DB6/SCLK DB7/SDATA VDD1 VDD2 VDD3 VSS1 VSS2 T5 T2 T1 T4 T3 VOS4 VOS3 VOS2 VOS1 VOS0 VLCDOUT VLCDSENSE VLCDIN R79 to R40 R79[1] C0 to C127 R0 to R39 - Table 2. Pad 1 to 8 9 10 11 12 13 14 15 16 17 18 19 20 and 21 22 and 23 24 to 26 27 28 29 30 31 32 33 34 35 36 37 [1] Duplicate of R79. 12.409 mm 2.271 mm PCF8811 y center 90 µm pitch y x x center mgw768 001aag914 Fig 3. Alignment marker Fig 4. Chip dimensions PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 5 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Bonding pad and chip dimensions Row/Column side (µm) 51.84 min 42.84 × 105 29.9 × 98.5 (±3) 381 (±25) Fab 1 (mm)[1] Fab 2 (mm)[2] 12.41 2.27 Interface side (µm) 54.0 min 50 × 100 32.2 × 93.5 (±3) Table 3. Pad Pad pitch Pad size (aluminium) Bump dimensions Wafer thickness (excluding bumps) Die size X Die size Y [1] [2] 12.45 2.31 Fabrication 1 identification starts with nnnnnn, where n represents a number between 0 and 9. Fabrication 2 identification starts with AXnnnn, where X represents a letter and n represents a number between 0 and 9. Table 4. Pad 2 108 [1] Alignment marker position[1] X (µm) 5995 −5904 Y (µm) 1017 1017 For the position of each pad, see Table 5. 6.2 Pin description Table 5. Bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol MF2 MF1 MF0 DS0 OSC EXT PS0 PS1 PS2 VSS(tie-off) PCF8811_4 Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 X (µm) 6092.00 5995.00 5876.00 5822.00 5768.00 5714.00 5660.00 5390.00 5012.00 4850.00 4688.00 4526.00 4364.00 4094.00 3932.00 3770.00 3608.00 3446.00 Y (µm) 1030.00 1017.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 Description dummy_slanted alignment mark dummy dummy dummy dummy dummy dummy manufacturer device ID input manufacturer device ID input manufacturer device ID input device recognition input oscillator input extended command set input parallel/serial/I2C-bus data selection input parallel/serial/I2C-bus data selection input parallel/serial/I2C-bus data selection input © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 6 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol SDAHOUT SDAH SDAH SCLH/SCE SCLH/SCE VOTPPROG VOTPPROG VOTPPROG RES D/C R/W/WR E/RD VDD(tie-off) DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SDO DB6/SCLK DB7/SDATA VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 PCF8811_4 Pad 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 X (µm) 2960.00 2420.00 2366.00 1826.00 1772.00 1664.00 1610.00 1556.00 1448.00 1232.00 962.00 800.00 638.00 476.00 314.00 152.00 −10.00 −172.00 −334.00 −550.00 −712.00 −874.00 −928.00 −982.00 −1036.00 −1090.00 −1144.00 −1198.00 −1252.00 −1306.00 −1360.00 −1414.00 −1468.00 −1522.00 −1576.00 −1630.00 −1684.00 −1738.00 Y (µm) 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 Description I2C-bus data output I2C-bus data input I2C-bus data input I2C-bus clock input or chip enable active LOW (6800 interface) I2C-bus clock input or chip enable active LOW (6800 interface) supply voltage for OTP (can be combined with SCLH/SCE) supply voltage for OTP (can be combined with SCLH/SCE) supply voltage for OTP (can be combined with SCLH/SCE) external reset input data or command active LOW input read or write active LOW input (6800 interface) clock enable or read active LOW input (6800 interface) parallel data input/output parallel data input/output parallel data input/output or I2C-bus slave address input parallel data input/output or I2C-bus slave address input parallel data input/output parallel data input/output or serial data output parallel data input/output or serial clock input parallel data input/output or serial data input supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 7 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol VDD3 VDD3 VDD3 VDD3 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 T5 T2 T1 T4 T3 VOS4 VOS3 VOS2 VOS1 VOS0 VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT PCF8811_4 Pad 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 X (µm) −1792.00 −1846.00 −1900.00 −1954.00 −2062.00 −2116.00 −2170.00 −2224.00 −2278.00 −2332.00 −2386.00 −2440.00 −2494.00 −2548.00 −2602.00 −2656.00 −2710.00 −2764.00 −2818.00 −2872.00 −2926.00 −2980.00 −3034.00 −3088.00 −3250.00 −3304.00 −3466.00 −3628.00 −3790.00 −4060.00 −4222.00 −4384.00 −4654.00 −4816.00 −4924.00 −4978.00 −5032.00 −5086.00 −5140.00 Y (µm) 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 Description supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier supply voltage for the internal voltage multiplier ground ground ground ground ground ground ground ground ground ground ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier ground for voltage multiplier test input 5 test input 2 test input 1 test input 4 test input 3 VLCD offset input pad 4 VLCD offset input pad 3 VLCD offset input pad 2 VLCD offset input pad 1 VLCD offset input pad 0 voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 8 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSENSE VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN R79 R78 R77 R76 R75 R74 R73 R72 R71 R70 R69 R68 R67 R66 R65 R64 R63 R62 R61 R60 PCF8811_4 Pad 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 X (µm) −5194.00 −5248.00 −5302.00 −5356.00 −5410.00 −5464.00 −5518.00 −5572.00 −5626.00 −5680.00 −5734.00 −5788.00 −5904.00 −6004.00 −6058.00 −6112.00 −6129.24 −6077.40 −6025.56 −5973.72 −5921.88 −5870.04 −5818.20 −5766.36 −5714.52 −5662.68 −5610.84 −5559.00 −5507.16 −5455.32 −5403.48 −5351.64 −5299.80 −5247.96 −5196.12 −5144.28 −5092.44 −5040.60 −4988.76 Y (µm) 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1017.00 1030.00 1030.00 1030.00 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 Description voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier regulation input LCD supply voltage LCD supply voltage LCD supply voltage LCD supply voltage LCD supply voltage LCD supply voltage LCD supply voltage alignment mark dummy dummy dummy dummy dummy dummy LCD row driver output (R79 is the icon row when the icon row is enabled) LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 9 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol R59 R58 R57 R56 R55 R54 R53 R52 R51 R50 R49 R48 R47 R46 R45 R44 R43 R42 R41 R40 R80 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 PCF8811_4 Pad 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 X (µm) −4936.92 −4885.08 −4833.24 −4781.40 −4729.56 −4677.72 −4625.88 −4574.04 −4522.20 −4470.36 −4418.52 −4366.68 −4314.84 −4263.00 −4211.16 −4159.32 −4107.48 −4055.64 −4003.80 −3951.96 −3900.12 −3640.92 −3589.08 −3537.24 −3485.40 −3433.56 −3381.72 −3329.88 −3278.04 −3226.20 −3174.36 −3122.52 −3070.68 −3018.84 −2967.00 −2915.16 −2863.32 −2811.48 −2759.64 Y (µm) −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 Description LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output duplicate of R79 LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 10 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 PCF8811_4 Pad 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 X (µm) −2707.80 −2655.96 −2604.12 −2552.28 −2500.44 −2448.60 −2396.76 −2344.92 −2293.08 −2241.24 −2189.40 −2137.56 −2085.72 −2033.88 −1878.36 −1826.52 −1774.68 −1722.84 −1671.00 −1619.16 −1567.32 −1515.48 −1463.64 −1411.80 −1359.16 −1308.12 −1256.28 −1204.44 −1152.60 −1100.76 −1048.92 −997.08 −945.24 −893.40 −841.56 −789.72 −737.88 −686.04 −634.20 Y (µm) −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 Description LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 11 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 PCF8811_4 Pad 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 X (µm) −582.36 −530.52 −478.68 −426.84 −375.00 −323.16 −271.32 −115.80 −63.96 −12.12 39.72 91.56 143.40 195.24 247.08 298.92 350.76 402.60 454.44 506.28 558.12 609.96 661.80 713.64 765.48 817.32 869.16 921.00 972.84 1024.68 1076.52 1128.36 1180.20 1232.04 1283.88 1335.72 1387.56 1439.40 1491.24 Y (µm) −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 Description LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 12 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 R0 R1 R2 R3 R4 R5 R6 PCF8811_4 Pad 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 X (µm) 1646.76 1698.60 1750.44 1802.28 1854.12 1905.96 1957.80 2009.64 2061.48 2113.32 2165.16 2217.00 2268.84 2320.68 2372.52 2424.36 2476.20 2528.04 2579.88 2631.72 2683.56 2735.40 2787.24 2839.08 2890.92 2942.76 2994.60 3046.44 3098.28 3150.12 3201.96 3253.80 3461.16 3513.00 3564.84 3616.68 3668.52 3720.36 3772.20 Y (µm) −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 Description LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 13 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 PCF8811_4 Pad 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 X (µm) 3824.04 3875.88 3927.72 3979.56 4031.40 4083.24 4135.08 4186.92 4238.76 4290.60 4342.44 4394.28 4446.12 4497.96 4549.80 4601.64 4653.48 4705.32 4757.16 4809.00 4860.84 4912.68 4964.52 5016.36 5068.20 5120.04 5171.88 5223.72 5275.56 5327.40 5379.24 5431.08 5482.92 5638.44 5690.28 5742.12 5793.96 5845.80 5897.64 Y (µm) −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 −1032.50 Description LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output dummy dummy dummy dummy dummy dummy © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 14 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 2. Symbol Pad 330 331 332 333 X (µm) 5949.48 6001.32 6053.16 6105.00 Y (µm) −1032.50 −1032.50 −1032.50 −1032.50 Description dummy dummy dummy dummy 7. Functional description 7.1 Pad functions 7.1.1 R0 to R79: row driver outputs These pads output the display row signals. 7.1.2 C0 to C127: column driver signals These pads output the display column signals. 7.1.3 VSS1 and VSS2: negative power supply rails • VSS2 for voltage multiplier • These 2 supply rails must be connected together 7.1.4 VDD1 to VDD3: positive power supply rails • VDD2 and VDD3 are the supply voltages for the internal voltage multiplier • VDD2 and VDD3 have the same voltage and may be connected together outside of the chip; see Section 17 • VDD1 is used as supply for the rest of the chip • VDD1 can be connected together with VDD2 and VDD3 • If the internal voltage multiplier is not used then pads VDD2 and VDD3 must be connected to VDD1; see Section 17 • In the case that VDD1, VDD2 and VDD3 are connected together, care must be taken with respect to the supply voltage range; see Section 14 7.1.5 VOTPPROG: OTP power supply Supply voltage for the OTP programming; see Section 18. VOTPPROG can be combined with the SCLH/SCE pad in order to reduce the external connections. 7.1.6 VLCDOUT, VLCDIN, and VLCDSENSE: LCD power supply Positive power supply for the liquid crystal display. • If the internal VLCD multiplier is used, then all three inputs must be connected together • If VLCD multiplier is disabled and an external voltage is supplied to VLCDIN, then VLCDOUT must be left open-circuit and VLCDSENSE must be connected to VLCDIN • VDD2 and VDD3 should be applied according to the specified voltage range PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 15 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver • If the PCF8811 is in Power-save mode, the external LCD supply voltage can be switched off 7.1.7 T1 to T5: test pads T1, T2 and T5 must be connected to VSS. T3 and T4 must be left open-circuit. These test pads are not accessible to the user. 7.1.8 MF2 to MF0 Manufacturer device ID pads. (Manufacturer ID 100 = NXP Semiconductors). 7.1.9 DS0 Device recognition pad; see Table 15. 7.1.10 VOS4 to VOS0 These 5 input pads enable the calibration of the offset of the programmed VLCD; see Equation 4 and Equation 5 in Section 12.10. VOS4 to VOS0 must be connected to VDD1 or VSS1. 7.1.11 EXT: extended command set Input to select the basic command set or the extended command set. Must be connected on the module to have only one command set enabled; see Table 6. Table 6. Pad EXT Command set selection Level LOW (VSS1) HIGH (VDD1) Description basic command set extended command set Remark: NXP Semiconductors recommends that the extended command set is used. 7.1.12 PS0, PS1 and PS2 Parallel/serial/I2C-bus interface selection; see Table 7. Table 7. PS[2:0] 000 001 010 011 100 or 110 101 or 111 Interface selection Interface 3-line SPI 4-line SPI no operation 6800 parallel interface high speed I2C-bus interface 3-line serial interface 7.1.13 D/C Input to select either data or command input. Not used in the 3-line serial interface, 3-line SPI and I2C-bus interface and must be connected to VDD1 or VSS1. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 16 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 7.1.14 R/W/WR Input to select read or write mode when the 6800 parallel interface is selected. Not used in the serial and I2C-bus mode and must be connected to VDD1 or VSS1. 7.1.15 E/RD E is the clock enable input for the 6800 parallel bus. Not used in the serial or I2C-bus interface and must be connected to VDD1 or VSS1. 7.1.16 SCLH/SCE Input to select the chip and so allowing data or commands to be clocked in or input for serial clock when the I2C-bus interface is selected. 7.1.17 SDAH I2C-bus serial data input. When not used, it must be connected to VDD1 and VSS1. 7.1.18 SDAHOUT SDAHOUT is the serial data acknowledge output for the I2C-bus interface. • By connecting SDAHOUT to SDAH externally, the SDAH line becomes fully I2C-bus compatible • The acknowledge output is separated from the serial data line due to the following reasons: – In COG applications where the track resistance from the SDAHOUT pad to the system SDAH line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance – It is possible that during the acknowledge cycle the PCF8811 will not be able to create a valid LOW level – By splitting the SDAH input from the SDAHOUT output the device could be used in a mode that ignores the acknowledge bit – In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid LOW level • When not used it must be connected to VDD1 or VSS1. 7.1.19 DB7 to DB0 These input/output lines are used by several interfaces as described below. When not used in the serial interface or the I2C-bus interface they must be connected to VDD1 or VSS1. 7.1.19.1 DB7 to DB0 (parallel interface) 8-bit bidirectional bus. DB7 is the MSB. 7.1.19.2 DB7, DB6 and DB5 (serial interface) • DB7 is used for serial input data (SDATA) when the serial interface is selected • DB6 (SCLK) is used for the serial input clock when the serial interface is selected • DB5 is used as the serial output of the serial interface (SDO) PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 17 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 7.1.19.3 DB3 and DB2 (I2C-bus interface) DB3 and DB2 are respectively the SA1 and SA0 inputs when the I2C-bus interface is selected and can be used so that up to four PCF8811s can be distinguished on one I2C-bus interface. 7.1.20 OSC: oscillator • When the on-chip oscillator is used this input must be connected to VDD1 • If an external clock signal is used, it is connected to this input • If the oscillator and an external clock are both inhibited by connecting the OSC pad to VSS1, the display is not clocked and may be left in a Direct Current (DC) state. To avoid a DC on display, the chip should always be put into Power-down mode before stopping the clock 7.1.21 RES: reset This signal will reset the device and must be applied to properly initialize the chip. The signal is active LOW. 7.2 Block diagram functions See Figure 1 for the block diagram layout. 7.2.1 Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required, and the OSC input must be connected to VDD1. An external clock signal, if used, is connected to this input. 7.2.2 Address counter The address counter assigns addresses to the display data RAM for writing. The X address X[6:0] and the Y address Y[3:0] are set separately. 7.2.3 Display data RAM The PCF8811 contains an 80 × 128 bit static RAM which stores the display data. • The RAM is divided into 10 banks of 128 bytes (10 × 8 × 128 bit) • The icon row (when enabled) is always row 79 and located in bank 9 • During RAM access, data is transferred to the RAM via the parallel interface, serial interface or I2C-bus interface • There is a direct correspondence between the X address and the column output number 7.2.4 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 18 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 7.2.5 Display address counter The display is generated by reading out the RAM content for 2, 4 or 8 rows simultaneously, depending on the current selected display size. This content is processed with the corresponding set of 2, 4 or 8 orthogonal functions and so generates the signals for switching the pixels in the display on or off according to the RAM content. The value p defines the number of rows which are simultaneously selected. It is possible to set the p value for the display sizes 64 and 80 manually to p = 4; see Table 10. The display status (all dots on/off and normal/inverse video) is set by the bits DON, DAL and E in the command display control; see Table 11. 7.2.6 LCD row and column drivers The PCF8811 contains 80 row and 128 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. 8. Addressing Data is written in bytes to the RAM matrix of the PCF8811 as shown in Figure 5. The display RAM has a matrix of 80 × 128 bits. The columns are addressed by the address pointer. The address ranges are: X = 0 to 127 (111 1111), Y = 0 to 9 (1001). The Y address represents the bank number. The effective X and Y addresses are programmed in such an order to use the PCF8811 with different display sizes, without additional loading of the microprocessor. Addresses outside these ranges are not allowed. The icon row when enabled is always row 79 and therefore located in bank 9. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 19 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver DPRAM bank 0 top of LCD R0 bank 1 R8 bank 2 R16 LCD bank 3 R24 bank 9 R72 R79 mgw734 Fig 5. DDRAM to display mapping 8.1 Display data RAM structure The mode for storing data into the data RAM depends on the selected command set. 8.1.1 Basic command set After a write operation the column address counter (X address) auto-increments by one, and wraps to zero after the last column is written. The number of columns (X address) after which the wrap around must occur can be programmed. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 20 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver The Y address counter does not auto-increment in the basic command set. The counter stops when a complete bank has been written to. In this case the Y address counter must be set; for Y address, see Table 10. To write the next bank, see Figure 6. When only a part of the RAM is used, both X (Xmax) and Y (Ymax) addresses can be set. The data order in the basic command set is as defined in Figure 6. LSB 0 MSB LSB Y max MSB 0 X address Y address X max mgw735 Fig 6. Sequence of writing data bytes into the RAM (basic command set) 8.1.2 Extended command set 8.1.2.1 Horizontal/vertical addressing Two different address modes are possible with the extended command set: horizontal address mode and vertical address mode. In the horizontal address mode (V = 0) the X address increments after each byte. After the last X address, X wraps around to 0 and Y increments to address the next row; see Figure 7. The number of columns (last X address) after which the wrap around must occur can be programmed. In Figure 7 it can be seen that the X address is programmed as 127, and the Y address is programmed as 9. With Xmax and Ymax the X and Y addresses can be programmed while the whole RAM is not being used. In the vertical addressing mode (V = 1) the Y address increments after each byte. After the last Y address (Y = 9), Y wraps around to 0 and X increments to address the next column; see Figure 8. The last Y address, after which Y wraps to 0, can be programmed. In Figure 8 it can be seen that the X address is programmed as 127, and the Y address is programmed as 9. With Xmax and Ymax the X and Y addresses can be programmed while the whole RAM is not being used. After the very last address, the address pointers wrap around to address X = 0 and Y = 0 in both horizontal and vertical addressing modes. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 21 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 0 128 256 384 512 640 768 896 1 129 257 385 513 641 769 897 2 130 258 386 514 642 770 898 0 Y address 1024 1025 1026 1152 1153 1154 0 X address 1279 127 9 mgw736 Fig 7. Sequence of writing data bytes into the RAM with horizontal addressing; V = 0 (extended command set) 0 1 2 3 4 5 6 7 8 9 0 10 11 0 Y address 1279 X address 127 9 mgw737 Fig 8. Sequence of writing data bytes into the RAM with vertical addressing; V = 1 (extended command set) 8.1.2.2 Data order The data order bit (DOR) defines the bit order (LSB or MSB on top) for writing into the RAM; see Figure 9 and Figure 10. This feature is only available in the extended command set. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 22 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver LSB MSB LSB mgw738 MSB Fig 9. RAM byte organization, if DOR = 0 (extended command set) MSB LSB MSB mgw739 LSB Fig 10. RAM byte organization, if DOR = 1 (extended command set) 8.1.2.3 Features available in both command sets Mirror X (MX): The MX bit allows horizontal mirroring: when MX = 1, the X address space is mirrored; the address X = 0 is then located at the right side (Xmax) of the display; see Figure 11. When MX = 0, the mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display; see Figure 12. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 23 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 0 Y max X max X address Y address 0 mgw740 Fig 11. RAM format addressing; MX = 1 (both command sets) 0 Y max 0 X address Y address X max mgw741 Fig 12. RAM format addressing; MX = 0 (both command sets) Mirror Y (MY): The MY bit allows vertical mirroring: when MY = 1, the Y address space is mirrored; the address Y = 0 is then located at the bottom of the display; see Figure 13. When MY = 0, the mirroring is disabled and the address Y = 0 is located at top of the display; see Figure 14. The icon row, when enabled, is always located in bank 9 and row 79. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 24 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Y max 0 0 X address Y address X max mgw742 Fig 13. RAM format addressing; MY = 1 (both command sets) 0 Y max 0 X address Y address X max mgw743 Fig 14. RAM format addressing; MY = 0 (both command sets) 9. Parallel interface The parallel interface, which can be selected, is the 6800 series 8-bit bidirectional interface for communication between the microcontroller and the LCD driver chip. The selection of this interface is achieved with pads PS[2:0]; see Section 7.1.12. 9.1 6800 series parallel interface The interface functions of the 6800 series parallel interface are given in Table 8. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 25 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 6800 series parallel interface functions R/W/WR 0 1 0 1 Operation command data write read status register display data write none Table 8. D/C 0 0 1 1 The parallel interface timing diagram for the 6800 series is given in Section 16.1, Figure 39 and Figure 40. The timing diagrams differ because in Figure 39 the clock is connected to the enable (E) input. In Figure 40 the clock is connected to the chip enable input (SCE) and the enable input (E) is tied HIGH. 10. Serial interfacing (SPI and serial interface) Communication with the microcontroller can also occur via a clock-synchronized Serial Peripheral Interface (SPI). It is possible to select between either a 3-line (SPI or serial interface) or a 4-line serial peripheral interface. Selection is achieved via PS[2:0]; see Section 7.1.12). 10.1 Serial peripheral interface lines The serial peripheral interface is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver chip. The 3 lines are: • SCE (chip enable) • SCLK (serial clock) • SDATA (serial data) For the 4-line serial peripheral interface a separate D/C line is added. The PCF8811 is connected to the serial data I/O (SDA) of the microcontroller by connecting the two pads SDATA (data input) and SDO (data output) together. 10.1.1 Write mode The display data/command indication may be controlled either via software or the D/C select pad. When the D/C pad is used, display data is transmitted when D/C is HIGH, and command data is transmitted when D/C is LOW; see Figure 15 and Figure 16. When pad D/C is not used, the display data length instruction is used to indicate that a specific number of display data bytes (1 to 255) are to be transmitted; see Figure 17. The next byte after the display data string is handled as an instruction command. When the 3-line SPI interface is used, the display data/command is controlled by software. If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. The next byte received will be handled as an instruction command; see Figure 18. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 26 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver SCE D/C SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 mgw744 Fig 15. Serial bus protocol: transmission of one byte SCE D/C SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 mgw745 Fig 16. Serial bus protocol: transmission of several bytes SCE SCLK last DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 data instruction SDATA DB7 DB6 DB5 DB4 DB2 DB1 DB0 data data display length instruction and length data (two bytes) display data string mgw746 Fig 17. Transmission of several bytes SCE SCLK SDATA data data data data data data display data string DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 mgw747 instruction Fig 18. Transmission interrupted by SCE PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 27 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 10.1.2 Read mode (only extended command set) The read mode of the interface means that the microcontroller reads data from the PCF8811. To do so, the microcontroller first has to send a command (the read status command) and then the PCF8811 will respond by transmitting data on the SDO line. After that, SCE is required to go HIGH; see Figure 19. The PCF8811 samples the SDATA data on rising SCLK edges, but shifts SDO data on falling SCLK edges. So, the microcontroller is supposed to read SDO data on rising SCLK edges. After the read status command has been sent, the SDATA line must be set to 3-state not later then the falling SCLK edge of the last bit; see Figure 19. Serial interface timing diagrams are shown in Section 16.2. SCE RES SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO instruction DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 read out data mgw748 Fig 19. Read mode SPI 3-line and 4-line 10.2 Serial interface (3-line) The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The 3 lines are: • SCE (chip enable) • SCLK (serial clock) • SDATA (serial data) The PCF8811 is connected to the SDA of the microcontroller by two lines: SDATA (data input) and SDO (data output) which are connected together. 10.2.1 Write mode The write mode of the interface means that the microcontroller writes commands and data to the PCF8811. Each data packet contains a control bit (D/C) and a transmission byte. If D/C is LOW, the following byte is interpreted as a command byte. The instruction set is shown in Table 10. If D/C is HIGH, the following byte is stored in the display data RAM. After every data byte the address counter is incremented automatically. Figure 20 shows the general format of the write mode and the definition of the transmission byte. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 28 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Any instruction can be sent in any order to the PCF8811; the MSB is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission. Figure 21, Figure 22 and Figure 23 show the protocol of the write mode: • when SCE is HIGH, SCLK clocks are ignored; during the HIGH time of SCE the serial interface is initialized • SCLK must be LOW on the falling SCE edge; see Figure 41 • SDATA is sampled on the rising edge of SCLK • D/C indicates, whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is sampled on the first rising SCLK edge • If SCE stays LOW after the last bit of a data/command byte, the serial interface receives the D/C bit of the next byte on the next rising edge of SCLK; see Figure 22 • A reset pulse RES interrupts the transmission. The data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a data/command byte; see Figure 23. Transmission Byte (TB) (command byte or data byte) D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB D/C TB D/C TB D/C TB mgu278 Fig 20. Serial data stream; write mode SCE SCLK SDATA D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 001aai348 Fig 21. Write mode: a control bit followed by a transmission byte PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 29 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver SCE SCLK SDATA D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C 001aai349 Fig 22. Write mode: transmission of several bytes SCE RES SCLK SDATA D/C DB7 DB6 DB5 DB4 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 001aai350 Fig 23. Write mode: interrupted by reset (RES) 10.2.2 Read mode (only extended command set) The read mode of the interface means that the microcontroller reads data from the PCF8811. To do so, the microcontroller first has to send a command (the read status command) and then the following byte is transmitted in the opposite direction using SDO; see Figure 24. After that, SCE is required to go HIGH before a new command is sent. The PCF8811 samples the SDATA data on the rising SCLK edges, but shifts SDO data on the falling SCLK edges. Thus the microcontroller is supposed to read SDO data on rising SCLK edges. After the read status command has been sent, the SDATA line must be set to 3-state not later then the falling SCLK edge of the last bit; see Figure 24. The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge; see Figure 44. The last rising SCLK edge sets SDO to 3-state after the delay time t4. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 30 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver SCE SCLK SDATA D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C SDO DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 001aai351 Fig 24. Read mode serial interface 3-line 11. I2C-bus interface 11.1 Characteristics of the I2C-bus (Hs-mode) The I2C-bus Hs-mode is for bidirectional, two-line communication between different ICs or modules with speeds of up to 3.4 MHz. The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate. Because of this the buffers on the SCLH and SDAH have open-drain outputs. This is the same for I2C-bus master devices which have an open-drain SDAH output and a combination of an open-drain, pull-down and current source pull-up circuits on the SCLH output. Only the current source of one master is enabled at any one time, and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.1.1 System configuration The system configuration is shown in Figure 25. Definitions of the I2C-bus terminology: • transmitter: the device which sends the data to the bus • receiver: the device which receives the data from the bus • master: the device which initiates a transfer, generates clock signals and terminates a transfer • slave: the device addressed by a master • multi-master: more than one master can attempt to control the bus at the same time without corrupting the message • arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted • synchronization: procedure to synchronize the clock signals of two or more devices PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 31 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER mga807 Fig 25. System configuration 11.1.2 Bit transfer One data bit is transferred during each clock pulse; see Figure 26. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. SDA SCL data line stable; data valid change of data allowed mbc621 Fig 26. Bit transfer 11.1.3 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 27. SDA SDA SCL S START condition P STOP condition SCL mbc622 Fig 27. Definition of START and STOP conditions 11.1.4 Acknowledge Each byte of eight bits is followed by an acknowledge bit; see Figure 28. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 32 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement mbc602 1 2 8 9 Fig 28. Acknowledge on the I2C-bus 11.2 I2C-bus Hs-mode protocol The PCF8811 is a slave receiver/transmitter. If data is to be read from the device, the SDAH pad must be connected, otherwise the SDAH pad is unused. Hs-mode can only commence after the following conditions: • START condition (S) • 8-bit master code (0000 1xxx) • Not-acknowledge bit (A) The master code has two functions: it allows arbitration and synchronization between competing masters at F/S-mode speeds, resulting in one winner. The master code also indicates the beginning of an Hs-mode transfer. These conditions are shown in Figure 29 and Figure 30. F/S-mode Hs-mode (current-source for SCLH enabled) F/S-mode S MASTER CODE A Sr SLAVE ADD. R/W A DATA (n bytes + ack.) A/A P Hs-mode continues Sr SLAVE ADD. msc616 Fig 29. Data transfer format in Hs-mode PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 33 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver S SDAH 8-bit master code 0000 1xxx A t1 tH SCLH 1 2 to 5 6 7 8 9 F/S-mode Sr 7-bit SLA R/W A n + (8-bit data + A/A) Sr P SDAH SCLH 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9 If P then F/S-mode If Sr (dotted lines) then Hs-mode Hs-mode tH = Master current source pull-up tFS msc618 = Resistor pull-up Fig 30. Data transfer timing format in F/S-mode and Hs-mode As no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge (A). After this A bit, and the SCLH line pulled up to a HIGH level, the active master switches to Hs-mode and enables at tH the current-source pull-up circuit for the SCLH signal; see Figure 30. The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address (SLA) with a R/W bit, and receives an acknowledge bit (A) from the selected slave. After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its current source pull-up circuit. The active master re-enables its current source again when all devices have been released and the SCLH signal reaches a HIGH level. The rising of the SCLH signal is done by a pull-up resistor and therefore is slower, the last part of the SCLH rise time is speeded up because the current source is enabled. Data transfer only switches back to F/S-mode after a STOP condition (P). A write sequence after the Hs-mode is selected is shown in Figure 31. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, the remainder will ignore the I2C-bus transfer. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 34 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver acknowledge from PCF8811 SS Sr 0 1 1 1 1 A A 0 A 1 D/C 10 slave address acknowledge from PCF8811 acknowledge from PCF8811 acknowledge from PCF8811 acknowledge from PCF8811 control byte A data byte A 0 D/C control byte A data byte n ≥ 0 bytes MSB . . . . . . . . . . . LSB AP R/W Co 2n ≥ 0 bytes Co 1 byte mgw749 Fig 31. Master transmits in Hs-mode to slave receiver; write mode After the acknowledgement cycle of a write (W), one or more command words will follow which define the status of the addressed slaves. A command word consists of a control byte, which defines continuation bit Co and D/C, plus a data byte; see Figure 31 and Table 9. The last control byte is initiated by bit Co (a cleared MSB). The control and data bytes are also acknowledged by all addressed slaves on the bus. Table 9. Bit Co 0 Co and D/C definitions Action last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RESTART condition another control byte will follow the data byte unless a STOP or RESTART condition is received data byte will be decoded and used to set-up the device data byte will return the status byte data byte will be stored in the display RAM RAM read back is not supported N/A Logic state R/W 1 D/C 0 1 N/A 0 1 0 1 A read sequence is shown in Figure 32 and again this sequence follows after the Hs-mode is selected. The PCF8811 will immediately start to output the requested data until a not-acknowledge is transmitted by the master. Before the read access, the user has to set the D/C bit to the appropriate value by a preceding write access. The write access must be terminated by a RESTART condition so that the Hs-mode is not disabled. acknowledge from PCF8811 SS Sr 0 1 1 1 1 A A 1 A 10 slave address R/W not-acknowledge from master status information AP STOP condition mgw750 Fig 32. Master receives from slave transmitter (status register is read); read mode After the last control byte, depending on the D/C bit setting, either a series of display data bytes or command data bytes may follow. If the D/C bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 35 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver The data pointer is automatically updated and the data is directed to the intended PCF8811 device. If the D/C bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8811. At the end of the transmission the I2C-bus master issues a STOP condition (P) and switches back to the F/S-mode, however, to reduce the overhead of the master code, it is possible that a master can link a number of Hs-mode transfers, separated by repeated START conditions (Sr). 11.3 Command decoder The command decoder identifies command words that are received on the I2C-bus: • pairs of bytes: information in second byte, first byte determines whether information is display or instruction data • Stream of information bytes after Co = 0: display or instruction data depending on last D/C The most significant bit of a control byte is the continuation bit Co. If this bit is at logic 1, it indicates that only one data byte, either command or RAM data, will follow. If this bit is at logic 0, it indicates that a series of data bytes, either command or RAM data, may follow. The DB6 bit of a control byte is the RAM data/command bit D/C. When this bit is at logic 1, it indicates that a RAM data byte will be transferred next. If the bit is at logic 0, it indicates that a command byte will be transferred next. 12. Instructions The PCF8811 interfaces via an 8-bit parallel interface, two different 3-line serial interfaces, a 4-wire serial interface or an I2C-bus interface. Processing of the instructions does not require the display clock. Data accesses to the PCF8811 can be broken down into two areas: those that define the operating mode of the device, and those that fill the display RAM. In the case of the parallel and 4-wire SPI interfaces, the distinction is the D/C pad. When the D/C pad is at logic 0, the chip will respond to instructions as defined in Table 10. When the D/C bit is at logic 1, the chip will send data to the RAM. When the 3-wire SPI, the 3-wire serial interface or the I2C-bus interface is used, the distinction between instructions which define the operating mode of the device and those that fill the display RAM, is made respectively by the display data length instruction (3-line SPI) or by the D/C bit in the data stream (3-line serial interface and I2C-bus interface). There are 4 types of instructions. Those which: 1. Define the PCF8811 functions, such as display configuration etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are used most frequently. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 36 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver A basic and an extended instruction set is available. If the EXT pad is set LOW the basic command set is used. If the EXT pad is set HIGH the extended command set is used. Both command sets are detailed in Table 10. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 37 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 04 — 27 June 2008 38 of 81 PCF8811_4 © NXP B.V. 2008. All rights reserved. NXP Semiconductors Table 10. Instruction set[1] Pad EXT[2] D/C 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 R/W/WR 0 0 0 0 0 0 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X 1 1 1 1 Command byte DB7[3] 0 1 1 D7 1 D7 BUSY 1 1 1 1 1 1 1 1 1 1 1 0 0 0 X 0 X 0 X 0 X 0 X DB6 1 1 1 D6 1 D6 DON 1 0 0 0 0 1 1 0 1 1 0 0 0 0 X 0 1 L6 1 C6 1 P6 DB5 0 1 1 D5 1 D5 RES 0 1 1 1 1 0 1 1 1 1 1 0 0 0 X 0 0 L5 0 C5 0 P5 DB4 0 0 0 D4 0 D4 MF2 1 0 0 0 0 0 0 0 0 0 1 1 0 1 X 1 0 L4 0 C4 0 P4 DB3 1 0 0 D3 1 D3 MF1 1 1 0 0 0 MY 1 0 1 1 Y3 0 X3 1 1 0 L3 0 C3 1 P3 DB2 1 1 0 D2 0 D2 MF0 0 1 1 1 0 X 1 0 0 1 Y2 X6 X2 0 0 0 L2 1 C2 0 P2 DB1 X 0 1 D1 0 D1 DS1 1 1 1 0 0 X 1 1 1 0 Y1 X5 X1 0 0 X L1 X C1 X P1 DB0 X 0 0 D0 0 D0 DS0 X E DAL MX X IC V BRS Y0 X4 X0 1 0 X L0 X C0 X P0 set partial display 1:16 to 1:80 set start row; 0 ≤ C ≤ 79[6] set Ymax; 0 ≤ Y ≤ 9 set Xmax; 0 ≤ X ≤ 127 set initial display line; 0 ≤ L ≤ 79[5] read status byte read status byte normal or reverse mode all pixels on or off mirror X mirror Y icon enable or disable[4] vertical or horizontal addressing[4] bottom row swap[4] set Y address; 0 ≤ Y ≤ 9 set X address; 0 ≤ X ≤ 127 soft reset write data to display RAM only used in 3-line SPI no operation Description Instruction NOP Reset Write data Display data length Status read Display control DON display on or off DOR data order[4] Address commands X X X X 80 x 128 pixels matrix LCD driver Ymax3 Ymax2 Ymax1 Ymax0 Ymax6 Ymax5 Ymax4 Ymax3 Ymax2 Ymax1 Ymax0 Set initial display line Set initial row Set partial display X X X X X X PCF8811 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 10. Instruction set[1] …continued Pad EXT[2] VOP setting 0 0 0 1 1 Power control HVgen stages FR TC[9] Bias system Manual p value (p = 4) Power-save on Power-save off Internal oscillator Internal oscillator Enter CALMM mode Reserved Reserved Test [1] [2] [3] [4] © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 39 of 81 PCF8811_4 NXP Semiconductors Instruction Command byte D/C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W/WR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB7[3] 1 X 0 1 VPR7 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 DB6 0 X 0 0 VPR6 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 DB5 0 VPR5 1 0 VPR5 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 DB4 0 VPR4 0 0 VPR4 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 DB3 0 VPR3 0 0 VPR3 1 0 0 1 1 0 1 1 0 1 0 0 1 X X DB2 0 VPR2 0 VPR2 PC1 1 S2 1 TC2 BS2 0 0 0 0 1 0 X X X DB1 0 VPR1 0 VPR1 PC0 S1 S1 FR1 TC1 BS1 1 0 0 1 1 1 X X X DB0 1 VPR0 1 VPR0 1 S0 S0 FR0 TC0 BS0 MP 1 1 OS EC 0 0 X X Description set VOP[7][8] VOFF2 VOFF1 VOFF0 offset for VOP[7][8] set VOP[4] switch HVgen on/off set multiplication factor set multiplication factor[4] set frame rate frequency[4] set temperature coefficient[4] set bias system[10] set manual p value[4][11] Power-save mode exit Power-save mode switch internal oscillator on/off enable or disable the internal or external oscillator[4] enter CALMM mode reserved reserved X 0 1 1 1 0 1 X X X 1 X X X X 80 x 128 pixels matrix LCD driver do not use; reserved for testing X = value without meaning. NXP Semiconductors recommends that the extended command set be used. D7 = MSB. Commands only available with the extended command set, EXT = 1. If EXT = 0 these commands have no effect. When the icon mode is enabled the set initial display line 0 ≤ L ≤ 78. When the icon mode is enabled the set initial row line 0 ≤ C ≤ 78. Commands only used for the basic command set EXT = 0. If EXT = 1 these commands have no effect. It must be checked, when setting VOP in the basic command set that it is followed by another command. The programming of VOP in the basic command set must be done in the following order: a) VPR[5:0] PCF8811 [5] [6] [7] [8] NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver b) VOFF[2:0] c) must be followed by another command. [9] One fixed TC is set automatically if the basic command set is used. [10] Bias system settings which can be received when the chip is used as a replacement for the Alt-Pleshko driving method (NOP). [11] Only for multiplex rates 1:64 and 1:80. The number of simultaneous rows can be set manually to p = 4; see Table 18. 12.1 Instruction set commands 12.1.1 Common instructions of the basic and extended command set Table 11. Bit DON E DAL MX MY OC OS X[6:0] Y[3:0] Common commands Logic 0 display off normal display normal display no X mirroring no Y mirroring stop frame frequency calibration internal oscillator off Logic 1 display on inverse video mode all pixels on X mirroring Y mirroring start frame frequency calibration start internal oscillator Reset state 0 0 0 0 0 0 0 000 0000 0000 111 1111 1001 000 0000 set X address (column) for writing in the RAM set Y address (bank) for writing in the RAM Xmax[6:0] set wrap around X address (column) Ymax[3:0] set wrap around Y address (bank) L[6:0] sets line address of the display; this command cannot access the icon driver row, row 80, if the icon row is enabled sets the initial row 0 of the display; this command cannot access the icon driver row, row 80, if the icon row is enabled partial display mode 1:16 to 1:80 switch HV multiplier on/off charge pump multiplication factor [1] C[6:0] 000 0000 P[6:0] PC[1:0] S[1:0] [1] 101 0000 (1:80)/100 0000 (1:64) 00 00 Partial displays can be selected in steps of 8, when the icon mode is not selected. When the icon mode is selected, partial displays can be selected in steps of 16. For example, without icons the available partial display sizes are 8, 16, 24, 32, 40, 48, 56, 64 or 72 lines. With icons there are 16, 32, 48 or 64 lines possible. Table 12. PC[1:0] 00 x1 1x Power control register Description HVgen off HVgen on HVgen on PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 40 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Power-save mode (PSM), OS, DON, DAL and E combinations[1] OS 0 1 1 1 1 1 X DON X X 0 1 1 1 X DAL X 0 1 0 0 1 X E X X X 0 1 X X Description oscillator off; HVgen disabled oscillator on; HVgen disabled display off; pads Rn/Cn at VSS; oscillator off; HVgen disabled[2] normal display mode inverse display mode all pixels on[3] Power-save mode: display off; pads Rn/Cn at VSS; oscillator off; HVgen disabled Table 13. PSM 0 0 0 0 0 0 1 [1] [2] [3] X = value without meaning. Bit DON can only be addressed after bit DAL is activated. Bit DAL has priority over bit E. Table 14. Bit BUSY DON RES MF[2:0] DS0 Table 15. DS0 0 1 [1] Read status byte Description if BUSY = 0 the chip is able to accept new commands same bit as in Table 13 if RES = 1 a reset is in progress device manufacturer ID device recognition; see Table 15 Device recognition[1] Description 64 row driver 80 row driver This is the only default setting after reset; another setting can be selected with the ‘set partial display mode’ command. Table 16. S[1:0] 00 01 10 11 Multiplication settings Description 4 × voltage multiplier 5 × voltage multiplier 6 × voltage multiplier 7 × voltage multiplier 12.1.2 Specific commands of the basic command set Table 17. Bit VPR[5:0] VOFF[2:0] Specific basic commands Description programming value of VLCD offset for the programming value of VLCD Reset state 00 0000 000 PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 41 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 12.1.3 Specific commands of the extended command set Table 18. Bit VPR[7:6] + VPR[5:0] FR[1:0] TC[2:0] S[2:0] V DOR IC BRS MP[1] Specific extended commands Logic 0 frame rate frequency temperature coefficient charge pump multiplication factor horizontal addressing LSB at top no icon row (multiplex rate 1:16 to 1:80) bottom rows are not mirrored multiplex rate driven p value (automatic) use internal oscillator vertical addressing MSB at top Logic 1 Reset state 000 0000 11 010 100 0 0 programming value of VLCD icon row (multiplex rate 0 1:16 to 1:80) bottom rows are mirrored 0 p = 4 selected for 0 multiplex rate 1:64 and 1:80 use external oscillator 0 EC [1] NXP Semiconductors recommends to use the p = 4 setting. Table 19. FR[1:0] 00 01 10 11 Table 20. TC[2:0] 000 001 010 011 100 101 110 111 [1] Frame rate frequency Frame rate frequency 30 Hz 40 Hz 50 Hz 60 Hz Temperature coefficient[1] Temperature coefficient 0 1 2 3 4 5 6 7 For further information about temperature coefficient, see Table 30. Table 21. S[2:0] 000 001 010 PCF8811_4 Multiplication settings Description 2 × voltage multiplier 3 × voltage multiplier 4 × voltage multiplier © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 42 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Multiplication settings …continued Description 5 × voltage multiplier 4 × voltage multiplier 5 × voltage multiplier 6 × voltage multiplier 7 × voltage multiplier Table 21. S[2:0] 011 100 101 110 111 12.2 Initialization Reset is accomplished by applying an external reset pulse (active LOW) at pad RES. When reset occurs within the specified time, all internal registers are reset, however the RAM is still undefined. The state after reset is described in Section 12.3. Pad RES must be ≤ 0.3 VDD1 when VDD1 reaches VDD(min) (or higher) within a maximum time tVHRL after VDD1 goes HIGH; see Figure 47. A reset can also be achieved by sending a reset command. This command can be used during normal operation but not to initialize the chip after power-on. 12.3 Reset function 12.3.1 Basic command set After reset the LCD driver has the following state: • • • • • • • • • • • • • • • Display setting E = 0 and DAL = 0 Address commands X[6:0] = 0 and Y[3:0] = 0 VLCD is equal to 0, the HV multiplier is switched off (PC[1:0] = 00) No offset of the programming range (VOFF[2:0] = 0) HV multiplier programming (VPR[5:0] = 0) 4 × voltage multiplier (S[1:0] = 00) After power-on, RAM data is undefined, the reset signal does not change the content of the RAM All LCD outputs at VSS (display off) Initial display line set to line 0 (L[6:0] = 0) Initial row set to row 0 (C[6:0] = 0) Full display selected (P[6:0] = multiplex rate 1:80 or 1:64) Display is not mirrored (MX = 0; MY = 0) Internal oscillator is off Power-save mode is on No frame calibration is running 12.3.2 Extended command set After reset the LCD driver has the following state: • Display settings E = 0 and DAL = 0 PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 43 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver • • • • • • • • • • • • • • • • • • • • Icons disabled (IC = 0) Address counter X[6:0] = 0 and Y[3:0] = 0 Temperature control mode TC2 (TC[2:0] = 010) VLCD is equal to 0 V; the HV multiplier is switched off (PC[1:0] = 0) HV multiplier programming (VPR[7:0] = 0) 4 × voltage multiplier (S[2:0] = 100) Frame-rate frequency (FR[1:0] = 11) After power-on, RAM data is undefined, the reset signal does not change the content of the RAM All LCD outputs at VSS (display off) Full display selected (P[6:0] = multiplex rate 1:80 or 1:64) Initial display line set to line 0 (L[6:0] = 0) Initial row set to row 0 (C[6:0] = 0) Display is not mirrored (MX = 0; MY = 0) Internal oscillator is off Power-save mode is on Horizontal addressing enabled (V = 0) No data order swap (DOR = 0) No bottom row swap (BRS = 0) Internal oscillator enabled (EC = 0) No frame calibration running (OC = 0) 12.4 Power-save mode In the Power-save mode the LCD driver has the following state: • • • • • All LCD outputs at VSS (display off) Bias generator and VLCD generator switched off; external VLCD can be disconnected Oscillator off (external clock possible) RAM contents not cleared; RAM data can be written VLCD discharged to VSS in Power-down mode There are two ways to put the chip into Power-save mode: • The display must be off (DON = 0) and all the pixels on (DAL = 1) • The Power-save mode command is activated 12.5 Display control The bits DON, E and DAL select the display mode; see Table 13. 12.5.1 Bit MX When MX = 0 the display RAM is written from left to right (X = 0 is on the left side and X = Xmax is on the right side of the display). PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 44 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver When MX = 1 the display RAM is written from right to left (X = 0 is on the right side and X = Xmax is on the left side of the display). The MX bit has an impact on the way the RAM is written to. So if a horizontal mirroring of the display is desired, the RAM must first be rewritten, after changing the MX bit. 12.5.2 Bit MY When MY = 1, the display is mirrored vertically. A change to this bit has an immediate effect on the display. 12.6 Set Y address of RAM Y[3:0] defines the Y address of the display RAM. Table 22. Y3 0 0 0 0 0 0 0 0 1 1 RAM X/Y address range Y2 0 0 0 0 1 1 1 1 0 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1 Content bank 0 (display RAM) bank 1 (display RAM) bank 2 (display RAM) bank 3 (display RAM) bank 4 (display RAM) bank 5 (display RAM) bank 6 (display RAM) bank 7 (display RAM) bank 8 (display RAM) bank 9 (display RAM) Allowed X range 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 When the icon row (row 79) is enabled it will always be in bank 9 independent of the multiplex rate which is programmed. 12.7 Set X address of RAM The X address points to the columns. The range of X is 0 to 127 (7Fh). 12.8 Set display start line L[6:0] (see Table 11) is used to select the display line address of the display RAM to be displayed on the initial row, row 0. The selection of L[6:0] is limited to steps of 8. When the icon row is selected, the selection of L[6:0] is limited to steps of 16. When a partial mode is selected, the selection of L[6:0] is also limited in steps. In addition, the selection of L[6:0] = 72 is not allowed when the icon row is enabled or disabled. The initial row can, in turn, be set by C[6:0]; see Table 11. Row 0 cannot be set to icon row 79 when enabled. An example of the mapping from the RAM content to the display is shown in Figure 33. The content of the RAM is not modified. This feature allows, for instance, screen scrolling without rewriting the RAM. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 45 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 04 — 27 June 2008 © NXP B.V. 2008. All rights reserved. PCF8811_4 NXP Semiconductors set initial display line and start row when MY = 0 X address RAM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 Row 10 Row 11 Row 12 Row 13 Row 14 Row 15 Row 16 Row 17 Row 18 Row 19 Row 20 Row 21 Row 22 Row 23 Row 24 Row 25 Row 26 Row 27 Row 28 Row 29 Row 30 Row 31 Display 0 L=8 1 C = 16 2 3 8 9 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Row 64 Row 65 Row 66 Row 67 Row 68 Row 69 Row 70 Row 71 Row 72 Row 73 Row 74 Row 75 Row 76 Row 77 Row 78 Row 79 mgw751 80 x 128 pixels matrix LCD driver PCF8811 46 of 81 Fig 33. Programming the L[6:0] address and C[6:0] address when MY = 0 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 12.9 Bias levels The bias levels for a MRA (Multiple Row Addressing) driving method with p = 8 are given in Figure 34 when Gmax and F have the same value. The value p defines the number of rows which are simultaneously selected. VLCD V3_H V2_H V1_H VC V1_L V2_L V3_L VSS mgw752 Gmax = F = VLCD 0.75Gmax 0.50Gmax 0.25Gmax VC −0.25Gmax −0.50Gmax −0.75Gmax −Gmax = F = VSS Fig 34. Bias levels for an MRA system with p = 8 and Gmax = F The row voltage F depends on the multiplex rate selected (number of rows N), the threshold voltage of the liquid (VTH), the number of simultaneously selected rows (p) and the multiplexibility (m): 1 N m± m–N F = ------ × V TH × ---- × ---------------------------------2 m–1 p (1) The column voltages are situated around the common level VC. The column voltage levels are equidistant from each other. In Table 23 the column voltage levels are given as a function of F. Table 23. Symbol F = Gmax VLCD V3_H V2_H V1_H VC V1_L V2_L F Bias levels for MRA driving method Bias voltages DC shifted bias voltages VLCD V LCD  (p – 2) -------------- ×  1 + ----------------------------------  2 m – m – N F ( p – 2 ) × ---------------------------------m– m–N F ( p – 4 ) × ---------------------------------m– m–N F ( p – 6 ) × ---------------------------------m– m–N 0 V LCD  (p – 4) -------------- ×  1 + ----------------------------------  2 m – m – N V LCD  (p – 6) -------------- ×  1 + ----------------------------------  2 m – m – N 1⁄ V 2 LCD F – ( p – 6 ) × ---------------------------------m– m–N F – ( p – 4 ) × ---------------------------------m– m–N V LCD  (p – 6) -------------- ×  1 – ----------------------------------  2 m – m – N V LCD  (p – 4) -------------- ×  1 – ----------------------------------  2 m – m – N PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 47 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Bias levels for MRA driving method …continued Bias voltages Table 23. Symbol V3_L VSS F – ( p – 2 ) × ---------------------------------m– m–N −F DC shifted bias voltages V LCD  (p – 2) -------------- ×  1 – ----------------------------------  2 m – m – N VSS The row voltages (F) are not necessarily larger then the column voltages. This depends on the number of rows which are selected, the multiplexibility and the value of p. However, the PCF8811 is designed in such a way that the maximum column voltages are always equal to the row voltages. In Table 24 the VLCD and the different bias levels are given for the PCF8811. The VLCD voltage is defined as: V LCD = 2F Where F is defined in Equation 1. (2) The bias system settings for different display modes are given in Table 24. All bias levels can be calculated by using the third column of Table 23 and the variables given in Table 24. Programming of the bias levels is not necessary in the PCF8811. The selection of the appropriate bias level voltages for each display mode is done automatically. Only the appropriate VLCD voltage must be programmed according to Equation 1 and Equation 2 for the display modes listed in Table 24. Table 24. Relationship between multiplex rates and bias setting variables without icon row Variable N 1:16 1:24 1:32 1:40 1:48 1:56 1:64 1:72 1:80 16 24 32 40 48 56 64 72 80 m 25 49 81 49 64 81 64 81 81 p 2 2 2 4 4 4 8 8 8 Multiplex rate The variables for calculating VLCD, when the icon row is enabled, are given in Table 25. The icon row can only be addressed in the extended command set. The PCF8811 allows the value of p for certain multiplex rates to be chosen manually. This is only possible for the multiplex rates 1:64 and 1:80. If other multiplex rates are chosen the PCF8811 determines the optimum value of p. By setting the value of p manually a compromise can be made between contrast and power consumption with certain liquids for the high multiplex rates 1:64 and 1:80. However, care must be taken that the liquid which is chosen ensures that the row voltages (F) and the maximum column voltages are equal. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 48 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Relationship between multiplex rates and bias setting variables with the icon row (only extended command set) Variable N m 49 49 81 81 81 p 2 4 8 8 8 24 40 56 80 80 Table 25. Multiplex rate 1:16 1:32 1:48 1:64 1:80 12.10 Set VOP value For multiplex rate 1:80 the optimum operation voltage of a liquid can be calculated with the variables given in Table 25, Equation 1 and Equation 2. 2 80 81 – 81 – 80 V LCD = ------ × V TH × ----- × --------------------------------------- = 4.472 × V TH 2 8 81 – 1 Where VTH is the threshold voltage of the liquid crystal material used. (3) The programming method for the VOP value is implemented differently in the basic command set from that in the extended command set. In the basic command set two commands are sent to the PCF8811: namely VPR[5:0] and VOFF[2:0]. In the extended command set only one command VPR[7:0] is sent to the PCF8811. The programming of VOP in the basic command set can be used when the PCF8811 is used as a replacement for an IAPT (Improved Alt-Pleshko Technique) LCD driver. The ROM look-up table Table 28 shows the possible values for VOFF[2:0], VPR[5:0], VOP[7:0] and VLCD. EXT = 1 EXT = 0 VPR[7:0] MMVOPCAL[4:0] VPR[5:0] VOFF[2:0] EXT 1 VLCD 0 LOOK-UP TABLE rom_add[8:0] ROM VOP[7:0] mgw753 VOS[4:0] b a 76543210210 Fig 35. Setting of VOP in the basic and extended command set 12.10.1 Basic command set The VLCD at T = TCUT in the basic command set is determined by the conversion in the ROM look-up table with the programmed values of VPR[5:0] and VOFF[2:0]. It can, additionally, be adjusted with the VLCD offset pads VOS[4:0] to obtain the optimum optical performance. Example: To get the value of 6 V for VLCD the following values have to be taken; see Table 26. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 49 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Example values of VPR, VOP and VOFF for VLCD = 6 V Value in Table 28 15 100 010 Binary value 0 1111 110 0100 010 Table 26. Register VPR[5:0] VOP[7:0] VOFF[2:0] Instead of using the VLCD offset pads (VOS[4:0]) the VLCD can be adjusted with the module maker calibration setting MMVOPCAL[4:0]; see Section 18. V LCD ( T Where: = T CUT ) = a + ( V OS [4:0] + V OP [7:0] ) × b (4) • • • • • TCUT is a reference temperature; see Section 12.11 a is a fixed constant value; see Table 27 b is a fixed constant value; see Table 27 VOP[7:0] is the result of the conversion table VOS[4:0]/MMVOPCAL[4:0] is the value of the offset VLCD pads or the value stored in the OTP cells Parameters of VLCD for the basic and extended command set Value 40 0.03 3 Unit °C V V Table 27. Symbol TCUT b a PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 50 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 04 — 27 June 2008 © NXP B.V. 2008. All rights reserved. PCF8811_4 NXP Semiconductors Table 28. VOFF[000] ROM look-up table with values of VOFF, VPR, VOP and VLCD VOFF[001] VOFF[010] VOFF[011] VOFF[100] VOFF[101] VPR VOP VLCD [5:0] [7:0] (V) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 185 187 189 191 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 221 223 225 227 229 231 233 235 237 239 8.55 8.61 8.67 8.73 8.76 8.82 8.88 8.94 9 9.06 9.12 9.18 9.24 9.3 9.36 9.42 9.48 9.54 9.6 9.63 9.69 9.75 9.81 9.87 9.93 9.99 VOFF[110] VPR VOP VLCD [5:0] [7:0] (V) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 219 221 223 226 228 230 232 234 236 239 241 243 245 247 249 252 254 256 256 256 256 256 256 256 256 256 256 256 256 9.57 9.63 9.69 9.78 9.84 9.9 9.96 VOFF[111] VPR VOP VLCD [5:0] [7:0] (V) 0 1 2 3 4 5 6 253 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 10.59 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 13 14 15 15 16 17 18 19 19 20 21 22 22 23 24 25 25 26 27 28 29 29 30 31 32 32 33 34 35 3.39 3.42 3.45 3.45 3.48 3.51 3.54 3.57 3.57 3.6 3.63 3.66 3.66 3.69 3.72 3.75 3.75 3.78 3.81 3.84 3.87 3.87 3.9 3.93 3.96 3.96 3.99 4.02 4.05 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 66 68 69 70 71 72 73 74 75 76 4.44 4.47 4.5 4.53 4.56 4.59 4.62 4.65 4.68 4.71 4.74 4.77 4.8 4.83 4.86 4.89 4.92 4.95 4.98 4.98 5.04 5.07 5.1 5.13 5.16 5.19 5.22 5.25 5.28 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 82 83 84 86 87 88 89 90 92 93 94 95 97 98 99 100 102 103 104 105 106 108 109 110 111 113 114 115 116 5.46 5.49 5.52 5.58 5.61 5.64 5.67 5.7 5.76 5.79 5.82 5.85 5.91 5.94 5.97 6 6.06 6.09 6.12 6.15 6.18 6.24 6.27 6.3 6.33 6.39 6.42 6.45 6.48 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 116 118 119 121 122 123 125 126 128 129 131 132 134 135 137 138 140 141 143 144 145 147 148 150 151 153 154 156 157 6.48 6.54 6.57 6.63 6.66 6.69 6.75 6.78 6.84 6.87 6.93 6.96 7.02 7.05 7.11 7.14 7.2 7.23 7.29 7.32 7.35 7.41 7.44 7.5 7.53 7.59 7.62 7.68 7.71 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 150 152 154 156 157 159 161 162 164 166 167 169 171 173 174 176 178 179 181 183 184 186 188 190 191 193 195 196 198 7.5 7.56 7.62 7.68 7.71 7.77 7.83 7.86 7.92 7.98 8.01 8.07 8.13 8.19 8.22 8.28 8.34 8.37 8.43 8.49 8.52 8.58 8.64 8.7 8.73 8.79 8.85 8.88 8.94 10.02 7 10.08 8 10.17 9 10.23 10 10.29 11 10.35 12 10.41 13 10.47 14 10.56 15 10.62 16 10.68 17 10.68 18 10.68 19 10.68 20 10.68 21 10.68 22 10.68 23 10.68 24 10.68 25 10.68 26 10.68 27 10.68 28 80 x 128 pixels matrix LCD driver 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 PCF8811 10.05 26 10.11 27 10.17 28 51 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 28. VOFF[000] ROM look-up table with values of VOFF, VPR, VOP and VLCD …continued VOFF[001] VOFF[010] VOFF[011] VOFF[100] VOFF[101] VPR VOP VLCD [5:0] [7:0] (V) 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 241 243 245 247 249 250 252 254 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 VOFF[110] VPR VOP VLCD [5:0] [7:0] (V) 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 VOFF[111] VPR VOP VLCD [5:0] [7:0] (V) 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 Product data sheet Rev. 04 — 27 June 2008 © NXP B.V. 2008. All rights reserved. PCF8811_4 NXP Semiconductors VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 35 36 37 38 39 39 40 41 42 42 43 44 45 45 46 47 48 48 49 50 51 52 52 53 54 55 55 56 57 4.05 4.08 4.11 4.14 4.17 4.17 4.2 4.23 4.26 4.26 4.29 4.32 4.35 4.35 4.38 4.41 4.44 4.44 4.47 4.5 4.53 4.56 4.56 4.59 4.62 4.65 4.65 4.68 4.71 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 5.31 5.34 5.37 5.4 5.43 5.46 5.49 5.52 5.55 5.58 5.61 5.64 5.67 5.7 5.73 5.76 5.79 5.82 5.85 5.88 5.91 5.94 5.97 6 6.03 6.06 6.09 6.12 6.15 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 118 119 120 121 123 124 125 126 127 129 130 131 132 134 135 136 137 139 140 141 142 143 145 146 147 148 150 151 152 6.54 6.57 6.66 6.63 6.69 6.72 6.75 6.78 6.81 6.87 6.9 6.93 6.96 7.02 7.05 7.08 7.11 7.17 7.2 7.23 7.26 7.29 7.35 7.38 7.41 7.44 7.5 7.53 7.56 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 159 160 162 163 165 166 167 169 170 172 173 175 176 178 179 181 182 184 185 187 188 189 191 192 194 195 197 198 200 7.77 7.8 7.86 7.89 7.95 7.98 8.01 8.07 8.1 8.16 8.19 8.25 8.28 8.34 8.37 8.43 8.46 8.52 8.55 8.61 8.64 8.67 8.73 8.76 8.82 8.85 8.91 8.94 9 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 200 201 203 205 207 208 210 212 213 215 217 218 220 222 224 225 227 229 230 232 234 235 237 239 241 242 244 246 247 9 9.03 9.09 9.15 9.21 9.24 9.3 9.36 9.39 9.45 9.51 9.54 9.6 9.66 9.72 9.75 9.81 9.87 9.9 9.96 10.23 29 10.29 30 10.35 31 10.41 32 10.47 33 10.5 34 10.56 35 10.62 36 10.68 37 10.68 38 10.68 39 10.68 40 10.68 41 10.68 42 10.68 43 10.68 44 10.68 45 10.68 46 10.68 47 10.68 48 10.68 49 10.68 50 10.68 51 10.68 52 10.68 53 10.68 54 10.68 55 10.68 56 10.68 57 10.68 29 10.68 30 10.68 31 10.68 32 10.68 33 10.68 34 10.68 35 10.68 36 10.68 37 10.68 38 10.68 39 10.68 40 10.68 41 10.68 42 10.68 43 10.68 44 10.68 45 10.68 46 10.68 47 10.68 48 10.68 49 10.68 50 10.68 51 10.68 52 10.68 53 10.68 54 10.68 55 10.68 56 10.68 57 80 x 128 pixels matrix LCD driver 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.02 49 10.05 50 10.11 51 10.17 52 10.23 53 10.26 54 10.32 55 10.38 56 10.41 57 PCF8811 52 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 28. VOFF[000] ROM look-up table with values of VOFF, VPR, VOP and VLCD …continued VOFF[001] VOFF[010] VOFF[011] VOFF[100] VOFF[101] VPR VOP VLCD [5:0] [7:0] (V) 256 256 256 256 256 256 VOFF[110] VPR VOP VLCD [5:0] [7:0] (V) 256 256 256 256 256 256 VOFF[111] VPR VOP VLCD [5:0] [7:0] (V) 256 256 256 256 256 256 10.68 10.68 10.68 10.68 10.68 10.68 Product data sheet Rev. 04 — 27 June 2008 53 of 81 PCF8811_4 © NXP B.V. 2008. All rights reserved. NXP Semiconductors VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD VPR VOP VLCD [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) [5:0] [7:0] (V) 58 59 60 61 62 63 58 58 59 60 61 62 4.74 4.74 4.77 4.8 4.83 4.86 58 59 60 61 62 63 105 107 108 109 110 111 6.15 6.21 6.24 6.27 6.3 6.33 58 59 60 61 62 63 153 155 156 157 158 160 7.59 7.65 7.68 7.71 7.74 7.8 58 59 60 61 62 63 201 203 204 206 207 209 9.03 9.09 9.12 9.18 9.21 9.27 58 59 60 61 62 63 249 251 252 254 256 256 10.47 58 10.53 59 10.56 60 10.62 61 10.68 62 10.68 63 10.68 58 10.68 59 10.68 60 10.68 61 10.68 62 10.68 63 10.68 58 10.68 59 10.68 60 10.68 61 10.68 62 10.68 63 80 x 128 pixels matrix LCD driver PCF8811 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 12.10.2 Extended command set The VLCD at T = TCUT is calculated using Equation 5. In the extended command set VPR[7:0] is the same value as VOP[7:0]. It can additionally be adjusted with the VLCD offset pads VOS[4:0] to obtain the optimum optical performance. Instead of using the VLCD offset pads (VOS[4:0]) the VLCD can be adjusted with the module maker calibration setting MMVOPCAL[4:0]; see Section 18. V LCD ( T Where: = T CUT ) = a + ( V OS [4:0] + V OP [7:0] ) × b (5) • • • • • TCUT is a reference temperature; see Section 12.11 a is a fixed constant value; see Table 27 b is a fixed constant value; see Table 27 VPR[7:0] is the programmed VOP value VOS[4:0]/MMVOPCAL[4:0] is the value of the offset VLCD pads or the value stored in the OTP cells As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9 V) the user has to ensure while setting the VPR register and selecting the Temperature Compensation (TC), that under all conditions and including all tolerances the VLCD remains below 9.0 V. This is valid for the two different command sets. mgt847 V LCD b a 00 01 02 03 04 05 06 ... ... FD FE FF V OP VOP[7:0] programming, (00h to FFh). Fig 36. VLCD programming of the PCF8811 12.11 Temperature control Due to the temperature dependency of the liquid crystals’ viscosity, the LCD controlling voltage VLCD might have to be increased at lower temperatures to maintain optimum contrast. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 54 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver You can calculate the VLCD at a specific temperature for both command sets. VLCD (at T = TCUT) is given by Equation 4 or Equation 5 depending on the command set which is used. V LCD ( T ) = V LCD ( T = T CUT ) × [ 1 + ( T – T CUT ) × TC ] (6) In the extended command set and basic command set 8 different temperature coefficients are available; see Figure 37. VLCD TCUT T mgw754 Fig 37. Temperature coefficients The typical values of the different temperature coefficients are given in Section 15. The coefficients are proportional to the programmed VLCD. The basic and extended command set differ in the way that the temperature coefficients can be accessed. In the basic command set only one temperature coefficient is available. However, the possibility exists to program the default temperature coefficient by means of OTP programming; see Section 18. In the extended command set the different temperature coefficients are selected by the interface with three bits TC[2:0]. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 55 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 13. Internal circuitry VDD1 VDD2 VDD3 VSS1 VSS1 VSS2 VSS1 VSS2 VLCDIN, VLCDSENSE VLCDOUT VSS1 VSS1 VSS1 VOTPPROG VLCDIN VDD1 DB[7:0], SCLK, SDATA, SDO, SA1, SA0, R/W/WR VSS1 LCD outputs VSS1 VSS1 VDD1 OSC, RES, D/C, PS[2:0], T1, T2, T5, E/RD VSS1 I2C-bus pins VDD1 VDD1 T3, T4, VSS1(1), VDD(2) VSS1 VSS1 001aai352 For test purposes only: (1) The maximum forward current is 5 mA (2) The maximum reverse voltage is 5 V Fig 38. Device protection diagrams 14. Limiting values Table 29. Limiting values[1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD1 VDD2 VDD3 Parameter supply voltage 1 supply voltage 2 supply voltage 3 Conditions general for internal voltage generator for internal voltage generator [2] Min −0.5 −0.5 −0.5 Max +6.5 +4.5 +4.5 Unit V V V [2] PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 56 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 29. Limiting values[1] …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VLCD Vi VOTPPROG II IO ISS Ptot P/out Tstg [1] [2] Parameter LCD supply voltage input voltage voltage applied to pad VOTPPROG input current output current ground supply current total power dissipation power dissipation per output storage temperature Conditions Min −0.5 −0.5 −0.5 Max +10 +6.5 +12 +10 +10 +50 300 30 +150 Unit V V V mA mA mA mW mW °C DC level DC level −10 −10 −50 −65 Parameters are valid over the whole operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. For the internal voltage multiplier. 15. Static characteristics Table 30. Static characteristics VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = 3 V to 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter VDD1 supply voltage 1 Conditions general basic command set; when using ROM look-up table; see Section 12.10 VDD2 VDD3 VLCDIN supply voltage 2 supply voltage 3 LCD supply voltage for internal voltage multiplier for internal voltage multiplier LCD voltage externally supplied (voltage multiplier disabled) LCD voltage internally generated (voltage multiplier enabled) without calibration with calibration general for internal voltage multiplier for internal voltage multiplier VDD1 + VDD2 + VDD3 [2] [3][4] [4][5] [1] Min 1.7 2 Typ - Max 3.3 3.3 Unit V V 1.8 1.8 3 - - 3.3 3.3 9 9 V V V V VLCDOUT voltage multiplier output voltage VLCD(tol) IDD1 IDD2 IDD3 IDD(tot) Vi VIL PCF8811_4 tolerance of generated VLCD supply current 1 supply current 2 supply current 3 total supply current input voltage LOW-level input voltage −300 −70 0.5 15 0 130 0 130 145 VSS − 0.5 VSS 1.5 25 0.5 150 0.5 150 175 +300 +70 5 50 1 200 1 200 250 mV mV µA µA µA µA µA µA µA [3][4] [4][5] [3][4] [4][5] [4][5] Logic inputs; MF[2:0], VOS[4:0], DS0, EXT, PS[2:0], RES and OSC VDD1 + 0.5 V 0.2VDD1 V © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 57 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 30. Static characteristics …continued VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = 3 V to 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter VIH IL Rcol Rrow Vbias(col) HIGH-level input voltage leakage current VI = VDD or VSS Conditions Min 0.8VDD1 −1 −100 −100 [6] Typ 0 0 0 −0.16 × 10−3 −0.33 × 10−3 −0.50 × 10−3 −0.66 × 10−3 Max VDD1 +1 5 5 +100 +100 - Unit V µA kΩ kΩ mV mV 1⁄°C 1⁄°C 1⁄°C 1⁄°C 1⁄°C 1⁄°C 1⁄°C 1⁄°C Column and row outputs column output resistance C0 to C127; VLCD = 5 V row output resistance bias tolerance voltage R0 to R79; VLCD = 5 V C0 to C127 R0 to R80 Vbias(row) bias tolerance voltage LCD supply voltage multiplier TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 LCD voltage temperature coefficient 0 LCD voltage temperature coefficient 1 LCD voltage temperature coefficient 2 LCD voltage temperature coefficient 3 LCD voltage temperature coefficient 4 LCD voltage temperature coefficient 5 LCD voltage temperature coefficient 6 LCD voltage temperature coefficient 7 input voltage LOW-level input voltage HIGH-level input voltage input voltage LOW-level input voltage HIGH-level input voltage −0.833 × 10−3 −1.25 × 10−3 −1.66 × 10−3 - - Parallel interface; VDD1 = 1.8 V to 3.3 V Vi VIL VIH Vi VIL VIH I2C-bus Vi IOL(SDA) VIL VIH VOL VOH [1] −0.5 VSS 0.8VDD1 −0.5 VSS 0.8VDD1 −0.5 VSS 0.7VDD1 VSS 0.8VDD1 - VDD1 + 0.5 V 0.2VDD1 VDD1 V V Serial interface; VDD1 = 1.7 V to 3.3 V VDD1 + 0.5 V 0.2VDD1 VDD1 +3.3 3 2 0.3VDD1 VDD1 0.2VDD1 VDD1 V V V mA mA V V V V interface; VDD1 = 1.8 V to 3.3 V input voltage LOW-level output current VOL = 0.4 V; VDD1 > 2 V on pin SDAH VOL = 0.2 VDD1; VDD1 < 2 V LOW-level input voltage HIGH-level input voltage LOW-level output voltage IOL = 0.5 mA HIGH-level output voltage IOH = −0.5 mA Output levels for all interfaces The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. © NXP B.V. 2008. All rights reserved. PCF8811_4 Product data sheet Rev. 04 — 27 June 2008 58 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver [2] [3] [4] [5] [6] Valid for values of temperature, VPR and TC used at calibration. During power-down all static currents are switched off. Conditions are: VDD1 = 1.8 V, VDD2 = 2.7 V, VLCD = 8.05 V, voltage multiplier 4 × VDD2, inputs at VDD1 or VSS, interface inactive, internal VLCD generation, VLCD output is loaded by 10 µA and Tamb = 25 °C. Normal mode. TC7 can only be used when VDD2 = VDD3 = 2.4 V or higher. 16. Dynamic characteristics Table 31. Dynamic characteristics[1] VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol fext fframe tVHRL tRW [1] [2] Parameter external frequency frame frequency VDD to RES LOW RES LOW pulse width Conditions external clock Tamb = 25 °C; VDD1 = 2.4 V see Figure 47 see Figure 47 [2] Min 54 43 0 500 Typ 200 60 58 - Max 66 73 1 - Unit kHz Hz Hz µs ns All specified timings are based on 20 % and 80 % of VDD. RES can be LOW before VDD goes HIGH. 16.1 Parallel interface timing characteristics Table 32. Parallel interface (6800 series) timing characteristics VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified; see Figure 39 and Figure 40. Symbol tSU;DC tHD;DC Tcyc(DS) tDS(L) tDS(H) tSU;RW tHD;RW tSU;CE tHD;CE tSU;DAT tHD;DAT tDAT;ACC tDAT;OH Parameter data/command set-up time data/command hold time data strobe cycle time data strobe LOW time data strobe HIGH time read/write set-up time read/write hold time chip enable set-up time chip enable hold time data set-up time data hold time data output access time data output disable time Min 40 20 1000 320 300 280 20 280 0 20 40 Max 280 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 59 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver R/W/WR tSU;CE tSU;RW tHD;CE tHD;RW D/C tSU;DC tHD;DC SCE Tcyc(DS) tDS(H) tDS(L) E tSU;DAT tHD;DAT D0 to D7 (Write) tDAT;ACC D0 to D7 (Read) mgw755 tDAT;OH Fig 39. Parallel interface timing; 6800 series (read mode) PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 60 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver D/C, R/W/WR tSU;RW tHD;RW D/C tSU;DC tHD;DC E Tcyc(DS) tDS(L) tDS(H) SCE tSU;DAT tHD;DAT D0 to D7 (Write) tDAT;ACC D0 to D7 (Read) 001aai347 tDAT;OH Fig 40. Parallel interface timing; 6800 series (write mode) 16.2 Serial interface timing characteristics Table 33. Serial interface timing characteristics[1] VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified; see Figure 41, Figure 42, Figure 43 and Figure 44. Symbol fSCLK Tcyc tPWH1 tPWL1 tS2 tH2 tPWH2 tH5 tS3 tH3 tS1 tH1 t1 t2 PCF8811_4 Parameter clock frequency clock cycle SCLK SCLK pulse width HIGH SCLK pulse width LOW SCE set-up time SCE hold time SCE minimum HIGH time SCE start hold time data/command set-up time data/command hold time SDATA set-up time SDATA hold time SDO access time SDO disable time [3] [2] Min 9.00 111 45 45 50 45 50 50 50 50 50 50 - Max 50 50 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 61 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 33. Serial interface timing characteristics[1] …continued VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified; see Figure 41, Figure 42, Figure 43 and Figure 44. Symbol t3 t4 Cb Rb [1] [2] [3] [4] [5] Parameter SCE hold time SDO disable time capacitive load for SDO series resistance for SDO [4] [5] [5] Min 50 25 - Max 100 30 500 Unit ns ns pF Ω All specified timings are based on 20 % and 80 % of VDD. tH5 is the time from the previous SCLK rising edge (irrespective of the state of SCE) to the falling edge of SCE. SDO disable time for SPI 3-line or 4-line. SDO disable time for 3-line serial interface. Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance + printed-circuit board. tS2 tH2 tPWH2 SCE (tH5) Tcyc tPWL1 SCLK tPWH1 tS2 tH5 tS1 tH1 SDATA mgw757 Fig 41. 3-line serial interface timing PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 62 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver tS2 tH2 tPWH2 SCE tS3 tH3 (tH5) tH5 D/C Tcyc tPWL1 SCLK tPWH1 tS2 tS1 tH1 SDATA mgw758 Fig 42. 4-line serial interface timing SCE t3 SCLK tH1 tS1 SDATA t1 SDO t2 001aai353 Fig 43. Serial interface timing; SPI 3-line or 4-line (read mode) PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 63 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver SCE t3 SCLK tH1 tS1 SDATA t1 SDO t4 001aai354 Fig 44. Serial interface timing; 3-line serial interface (read mode) 16.3 I2C-bus interface timing characteristics Table 34. I2C-bus characteristics; F/S-mode VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified[1]; see Figure 45. Symbol fSCL tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STO tSP tBUF VnL VnH Parameter SCL clock frequency set-up time for a repeated START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line set-up time for STOP condition pulse width of spikes that must be suppressed by the input filter bus free time between a STOP and START condition noise margin at the LOW level noise margin at the HIGH level for each connected device (including hysteresis) for each connected device (including hysteresis) Conditions Min 0 600 600 1300 600 100 0 Typ Max 400 900 300 300 400 50 Unit kHz ns ns ns ns ns ns ns ns pF ns ns ns V V 20 + 0.1Cb 20 + 0.1Cb 600 1300 0.1VDD1 0.2VDD1 - [1] All specified timings are based on 20 % and 80 % of VDD. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 64 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver Table 35. I2C-bus characteristics; Hs-mode VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified[1]; see Figure 46. Symbol fSCLH tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT trCL trCL1 Parameter SCLH clock frequency set-up time for a repeated START condition hold time (repeated) START condition LOW period of the SCLH clock HIGH period of the SCLH clock data set-up time data hold time rise time of SCLH signal rise time of SCLH signal after a repeated START condition and after an acknowledge bit fall time of SCLH signal rise time of SDAH signal fall time of SDAH signal set-up time for STOP condition pulse width of spikes that must be suppressed by the input filter capacitive load for each bus line SDAH and SCLH Conditions Cb = 100 pF (max) Min 0 160 160 160 60 10 20[3] 10 10 Max 3.4 70 40 80 Cb = 400 pF[2] Min 0 160 160 320 120 10 20[3] 20 20 Max 1.7 150 80 160 MHz ns ns ns ns ns ns ns ns Unit tfCL trDA tfDA tSU;STO tSP 10 10 10 160 0 40 80 80 5 20 20 20 160 0 80 160 160 5 ns ns ns ns ns Cb SDAH and SCLH lines SDAH + SDA line and SCLH + SCL line [2] 0 0 0.1VDD1 0.2VDD2 100 400 - 0.1VDD1 0.2VDD2 400 400 - pF pF V V VnL VnH noise margin at the LOW level for each connected device (including hysteresis) noise margin at the HIGH level for each connected device (including hysteresis) [1] [2] [3] All specified timings are based on 20 % and 80 % of VDD. For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 65 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver SDA tf tf tLOW tr tSU;DAT tHD;STA tSP tr tBUF SCL tHD;STA S tSU;STA Sr tSU;STO tHD;DAT tHIGH P S 001aai355 S = start Sr = start repeated P = stop Fig 45. I2C-bus timing diagram (F/S-mode) Sr tfDA trDA Sr P SDAH tHD;DAT tSU;STA tHD;STA tSU;DAT tSU;STO SCLH tfCL trCL1 (1) trCL tHIGH tLOW tLOW tHIGH trCL1 (1) mgk871 = MCS current source pull-up = Rp resistor pull-up (1) Rising edge of the first SCLH clock pulse after an acknowledge bit. Fig 46. I2C-bus timing diagram (Hs-mode) PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 66 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver VDD tRW RES tRW VDD tVHRL tRW tRW RES mgw761 Fig 47. Reset timing 17. Application information Semiconductors are light sensitive. Exposure to light sources can cause the IC to malfunction. In this application you must protect the IC from light. The protection has to be done on all sides of the IC, i.e. front, rear and all edges. The pinning of the PCF8811 has an optimum design for single plane wiring e.g. for chip-on-glass display modules. Display size: 80 × 128 pixels. For further application information refer to NXP Semiconductors Application Note AN10170 Design guidelines for COG modules with Philips monochrome LCD drivers. DISPLAY 80 × 128 pixels PCF8811 VDD3 VDD2 VDD1 VSS1 VSS2 CVDD CVLCD I/O VDD VSS VLCDSENSE VLCDOUT VLCDIN mgw762 Fig 48. Application diagram: internal charge pump and a single supply PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 67 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver DISPLAY 80 × 128 pixels PCF8811 VDD3 VDD2 VDD1 VSS1 VSS2 CVDD1 CVDD2 VDD1 I/O VDD2 CVLCD VLCDSENSE VLCDOUT VLCDIN VSS mgw763 Fig 49. Application diagram: internal charge pump and two separate supplies (VDD1 and VDD2) DISPLAY 80 × 128 pixels PCF8811 VDD3 VDD2 VDD1 VSS1 VSS2 CVDD I/O VDD VSS VLCDSENSE VLCDOUT VLCDIN VLCDIN mgw764 Fig 50. Application diagram: external high voltage The required minimum value for the external capacitors in an application with the PCF8811 are: CVLCD = 1.0 µF to 4.7 µF depending on the application. CVDD, CVDD1, CVDD2 = 1.0 µF. For these capacitors, higher values can be used. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 68 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 18. Support information 18.1 Module maker programming One Time Programmable (OTP) technology is implemented on the PCF8811. It enables the module maker to program some extended features of the PCF8811 after it has been assembled on an LCD module. Programming is made under the control of the interfaces and the use of one special pad. This pad must be made available on the module glass but need not be accessed by the set maker. The PCF8811 features 3 parameters programmable by the module maker: • VLCD calibration • Temperature coefficient selection • Seal bit 18.1.1 VLCD calibration The first feature included is the ability to adjust the VLCD voltage with a 5-bit code (MMVOPCAL). This code is implemented in two’s complement notation giving rise to a positive or negative offset to the VPR register. This is in the same manner as the on-glass calibration pads VOS. In theory, both may be used together but it is recommended that the VOS pads are tied to VSS when OTP calibration is being used. This sets them to a default offset of zero. If both are used then the addition of the two 5-bit numbers must not exceed a 5-bit result, otherwise the resultant value is undefined. The final adder in the circuit has underflow and overflow protection. In the event of an overflow, the output will be clamped to 255; during an underflow the output will be clamped to 0. The final control to the high voltage multiplier, VOP, is the sum of all the calibration registers and pads. The VLCD Equation 4 or Equation 5 given in Section 12.10.1 or Section 12.10.2 must be extended to include the OTP calibration, as follows: V LCD ( T = T CUT ) = a + ( V OS [4:0] + MMVOPCAL[4:0] + V OP [7:0] ) × b (7) The possible values for MMVOPCAL[4:0] and VOS[4:0] values are given in Table 36. Table 36. Binary 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 PCF8811_4 VOS/MMVOPCAL values in two’s complement notation Decimal 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 Binary 1 1111 1 1110 1 1101 1 1100 1 1011 1 1010 1 1001 1 1000 1 0111 1 0110 Decimal −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 69 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver VOS/MMVOPCAL values in two’s complement notation …continued Decimal +10 +11 +12 +13 +14 +15 Binary 1 0101 1 0100 1 0011 1 0010 1 0001 1 0000 Decimal −11 −12 −13 −14 −15 −16 Table 36. Binary 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 OTP VLCD calibration: 5-bit offset MMVOPCAL[4:0] laser trim pins: 5-bit offset VOS[4:0] range −16 to +15 range −16 to +15 + + VOP[7:0] range: 0 to +255 to high voltage generator range 0 to +255 usable range +32 to +255 VPR register: 8-bit value VPR[7:0] mgu287 Fig 51. VLCD calibration 18.1.2 Temperature coefficient selection The second feature is an OTP factory default setting for the temperature coefficient selection (MMTC) in the basic command set. This 3-bit value will be loaded from OTP after leaving the Power-save mode or by the Refresh command. The idea of this feature is to provide, in the basic command set, the complete set of temperature coefficients without an additional command. In the extended command set the temperature coefficient can be programmed as given in Table 20 and Table 30. 18.1.3 Seal bit The module maker programming is performed in a special mode: the calibration mode (CALMM). This mode is entered via a special interface command, CALMM. To prevent unwanted programming, a seal bit has been implemented which prevents the device from entering the calibration mode. This seal bit, once programmed, cannot be reversed so further changes in programmed values are not possible. Applying the programming voltages when not in CALMM mode has no effect on the programmed values. Table 37. Seal bit 0 1 Seal bit definition Action possible to enter calibration mode calibration mode disabled PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 70 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 18.1.4 OTP architecture The OTP circuitry in the PCF8811 contains 9 bits of data: 5 for VLCD calibration (MMVOPCAL), 3 for the temperature coefficient default setting in the basic command set MMTC and 1 seal bit. The circuitry for 1-bit is called an OTP slice. Each OTP slice consists of 2 main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are only accessible through their shift register cells: on the one hand both reading from and writing to the OTP cells is performed with the shift register cells, on the other hand only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Figure 52. This OTP architecture allows the following operations: Reading data from the OTP cells — The content of the non-volatile OTP cells is transferred to the shift register where upon it may affect the PCF8811 operation. Writing data to the OTP cells — All 9 data bits are shifted into the shift register via the interface. The content of the shift register is then transferred to the OTP cells. There are some limitations related to storing data in these cells; see Section 18.1.7. Checking calibration without writing to the OTP cells — Shifting data into the shift register allows the effects on the VLCD voltage to be observed. The reading of data from the OTP cells is initiated by either: • Exit from Power-save mode • The ‘Refresh’ command (power control) Remark: Note that in both cases the reading operation needs up to 5 ms to complete. The shifting of data into the shift register is performed in the special mode CALMM. In the PCF8811 the CALMM mode is entered by the CALMM command. Once in the CALMM mode the data is shifted into the shift register via the interface at the rate of 1-bit per command. After transmitting the last (9th) bit and exiting the CALMM mode, the serial interface will return to the normal mode and all other commands can be sent. Care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the CALMM mode, otherwise the bits will be in the wrong positions. In the shift register the value of the seal bit is, like the others, always zero at reset. To ensure that the security feature (seal bit) works correctly, the CALMM command is disabled until a refresh has been performed. Once the refresh is completed, the seal bit value in the shift register will be valid and permission to enter the CALMM mode can thus be determined. The 9 bits are shifted into the shift register in a predefined order: first 5 bits of MMVOPCAL[4:0], 3 bits for MMTC[2:0] and lastly the seal bit. The MSB is always first, thus the first bit shifted is MMVOPCAL[4] and the two last bits are MMTC[0] and the seal bit. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 71 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver DATA TO THE CIRCUIT FOR CONFIGURATION AND CALIBRATION OTP slice SHIFT REGISTER FLIP-FLOP SHIFT REGISTER DATA INPUT SHIFT REGISTER read data from the OTP cell write data to the OTP cell OTP CELLS mgu289 OTP CELL Fig 52. Basic OTP architecture 18.1.5 Interface commands These instructions are in addition to those indicated in Table 10. Table 38. Additional interface commands Pad EXT CALMM Power control (‘refresh’) X[1] X[1] D/C 0 0 R/W/WR 0 0 Command byte DB7 1 0 DB6 0 0 DB5 0 1 DB4 0 0 DB3 0 1 DB2 0 PC1 DB1 1 PC0 DB0 0 1 enter CALMM mode switch HVgen on/off to force a refresh of the shift register Description Instruction [1] X = value without meaning. 18.1.5.1 CALMM This instruction puts the device in calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode all commands are interpreted as shift register data. The mode can only be exited by sending data with DB7 set to logic 0. Reset will also clear this mode. Each shift register data byte is preceded by D/C = 0 and has only 2 significant bits, thus the remaining 6 bits are ignored. DB7 is the continuation bit (DB7 = 1 remain in CALMM mode, DB7 = 0 exit CALMM mode). DB0 is the data bit and its value is shifted into the OTP shift register (on the falling edge of SCLK). 18.1.5.2 Refresh The action of the ‘Refresh’ instruction is to force the OTP shift register to re-load from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all other instructions may be sent. In the PCF8811 the ‘Refresh’ instruction is associated with the ‘Power control’ instruction so that the shift register is automatically refreshed every time the high voltage multiplier is enabled or disabled. Note that if this instruction is sent while in Power-save mode, the PC[1:0] bits are updated but the refreshing is ignored. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 72 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 18.1.6 Example sequence for filling the shift register An example of the sequence of commands and data is shown in Table 39. In this example the shift register is filled with the following data: MMVOPCAL = −4 (1 1100b), MMTC = 2 (010b) and the seal bit is logic 0. It is assumed that the PCF8811 has just been reset. After transmitting the last bit the PCF8811 can either exit or remain in the CALMM mode; see Table 39, Step 1. It should be noted that while in CALMM mode the interface does not recognize commands in the normal sense. After this sequence has been applied it is possible to observe the impact of the data shifted in. The described sequence is, however, not useful for OTP programming because the number of bits with the value logic 1 is greater than that allowed for programming; see Section 18.1.7. The shift register after this action is shown in Figure 53. Table 39. Step Pad EXT 1 2 3 4 5 6 7 8 9 10 11 12 13 [1] [2] Sequence for filling the shift register; example 1[1] Command byte D/C R/W/WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 X X X X X X X X X 1 1 0 X X X X X X X X X 1 0 0 X X X X X X X X X 1 0 0 X X X X X X X X X 1 0 0 X X X X X X X X X 1 0 1 X X X X X X X X X 1 1 0 1 1 1 0 0 0 1 0 0 0 exit power-down wait 5 ms for refresh to take effect enter CALMM mode shift in data; MMVOPCAL[4] is first bit [2] MMVOPCAL[3] MMVOPCAL[2] MMVOPCAL[1] MMVOPCAL[0] MMTC[2] MMTC[1] MMTC[0] seal bit; exit CALMM mode seal bit; remain in CALMM mode Action X X X X X X X X X X X X An alternative ending could be to stay in CALMM mode X = value without meaning. The data for the bits is not in the correct shift register position until all bits have been sent. OTP SHIFT REGISTER shifting direction SEAL BIT = 0 LSB MMTC[2:0] MSB LSB 0 1 0 0 MMVOPCAL[4:0] 0 1 1 MSB 1 mgw765 Fig 53. Shift register contents after example sequence; see Table 39 18.1.7 Programming flow Programming is achieved whilst in CALMM mode and with the application of the programming voltages. As mentioned previously, the data for programming the OTP cell is contained in the corresponding shift register cell. The shift register cell must be loaded PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 73 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver with a logic 1 in order to program the corresponding OTP cell. If the shift register cell contains a logic 0, then no action will take place when the programming voltages are applied. Once programmed, an OTP cell cannot be de-programmed. An already programmed cell, i.e. an OTP cell containing a logic 1, must not be re-programmed. During programming, a substantial current flows in the VLCDIN pad. For this reason it is recommended to program only one OTP cell at a time. This is achieved by filling all but one shift register cells with logic 0. It should be noted that the programming specification refers to the voltages at the chip pads, contact resistance must therefore be considered by the user. An example sequence of commands and data for OTP programming is given in Table 40. It is assumed that the PCF8811 has just been reset. The order for programming cells is not significant. However, NXP Semiconductors recommends that the seal bit is programmed last. Once this bit has been programmed and the CALMM mode is exited, it is not possible to re-enter the CALMM mode. Table 40. Step Pad 1 2 3 4 5 6 7 9 10 11 12 13 14 15 X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sequence for filling the shift register; example 2[1] Command byte 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 X X X X X X X X X 0 0 0 X X X X X X X X X 0 1 0 X X X X X X X X X 0 0 0 X X X X X X X X X 0 0 1 X X X X X X X X X 1 1 0 1 1 1 0 0 0 1 0 0 Action exit power-save wait 5 ms for refresh to take effect re-enter power-down (DON = 0) enter CALMM mode shift in data; MMVOPCAL[4] is first bit MMVOPCAL[3] MMVOPCAL[2] MMVOPCAL[1] MMVOPCAL[0] MMTC[2] MMTC[1] MMTC[0] seal bit apply programming voltage at pads VOTPPROG and VLCDIN; see Section 18.1.8 apply external reset EXT D/C R/W/WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Repeat steps 5 to 14 for each bit which must be programmed to 1; exit CALMM mode 16 [1] - - - - - - - - - - - X = value without meaning. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 74 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 18.1.8 Programming specification Table 41. Programming specification See Figure 54. Symbol VOTPPROG VLCDIN ILCDIN IVOTPPROG Tamb(PROG) tSU;SCLK tHD;SCLK Parameter voltage applied to pad VOTPPROG relative to VSS1 voltage applied to pad VLCDIN relative to VSS1 current drawn by VLCDIN during programming current drawn by VOTPPROG during programming ambient temperature during programming set-up time of internal data after last clock hold time of internal data before next clock Conditions programming active programming inactive programming active programming inactive when programming a single bit to logic 1 [1] [1] [1][2] [1][2] Min 11 VSS − 0.2 9 0 1 1 1 1 100 Typ 11.5 0 9.5 850 100 25 120 Max 12 10 4.5 1000 200 40 10 10 200 Unit V V V mA mA °C µs µs µs ms ms VSS + 0.2 V VDD2 − 0.2 VDD2 tSU;VOTPPROG set-up time of VOTPPROG prior to programming tHD;VOTPPROG hold time of VOTPPROG after programming tPW pulse width of programming voltage [1] [2] The voltage drop across the ITO track and zebra connector must be taken into account to guarantee a sufficiently high voltage at the chip pads. The Power-down mode (DON = 0 and DAL = 1) and CALMM mode must be active while the VLCDIN pad is being driven. tSU;SCLK tHD;SCLK SCLK VVOTPPROG VLCDIN tSU;VOTPROG tPW tHD;VOTPPROG mgw766 Fig 54. Programming waveforms 19. Package outline Not applicable. PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 75 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 20. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5. 21. Packing information Table 42. Tray dimensions See Figure 55. Symbol A B C D E F x y Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction Value 13.77 mm 4.45 mm 12.55 mm 2.41 mm 50.8 mm 50.8 mm 3 10 x A C y D B F E mgs488 Fig 55. Tray details PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 76 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver PCF8811 mgw771 Fig 56. Tray alignment The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram (Figure 2) for the orientation and position of the type name on the die surface. 22. Abbreviations Table 43. Acronym CDM CMOS COG DDRAM ESD HBM HV IC ITO LCD LSB MM MRA MSB MPU OTP RAM SPI TC TCP Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Chip-On-Glass Double Data Random Access Memory ElectroStatic Discharge Human Body Model High Voltage Integrated Circuit Indium Tin Oxide Liquid Crystal Display Least Significant Bit Machine Model Multiple Row Addressing Most Significant Bit MicroProcessing Unit One Time Programmable Read Access Memory Serial Peripheral Interface Temperature Coefficient Tape Carrier Packages PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 77 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 23. Revision history Table 44. Revision history Release date 20080627 Data sheet status Product data sheet Change notice Supersedes PCF8811_3 Document ID PCF8811_4 Modifications: • • • • • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Amendments to the text Added ROM look-up Table 28 Changed values in Table 30 and Table 31 Changed Figure 2, Figure 4, Figure 48, Figure 49, and Figure 50 Moved Figure 2 to Section 6 “Pinning information” Moved Table 3 and Table 4 to Section 6 “Pinning information” Added Fab 1 and Fab 2 details and adjusted die dimensions in Table 3 Product specification Product specification Product specification PCF8811_2 PCF8811_1 - PCF8811_3 (9397 750 13144) PCF8811_2 (9397 750 10285) PCF8811_1 (9397 750 09148) 20040517 20021204 20020814 PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 78 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 24. Legal information 24.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 24.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 24.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 24.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 25. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 79 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 26. Contents General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . 15 Pad functions . . . . . . . . . . . . . . . . . . . . . . . . . 15 R0 to R79: row driver outputs . . . . . . . . . . . . . 15 C0 to C127: column driver signals . . . . . . . . . 15 VSS1 and VSS2: negative power supply rails . . 15 VDD1 to VDD3: positive power supply rails . . . . 15 VOTPPROG: OTP power supply. . . . . . . . . . . . . 15 VLCDOUT, VLCDIN, and VLCDSENSE: LCD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1.7 T1 to T5: test pads . . . . . . . . . . . . . . . . . . . . . 16 7.1.8 MF2 to MF0 . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1.9 DS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1.10 VOS4 to VOS0 . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1.11 EXT: extended command set . . . . . . . . . . . . . 16 7.1.12 PS0, PS1 and PS2 . . . . . . . . . . . . . . . . . . . . . 16 7.1.13 D/C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1.14 R/W/WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.15 E/RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.16 SCLH/SCE . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.17 SDAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.18 SDAHOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.19 DB7 to DB0. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.19.1 DB7 to DB0 (parallel interface) . . . . . . . . . . . . 17 7.1.19.2 DB7, DB6 and DB5 (serial interface) . . . . . . . 17 7.1.19.3 DB3 and DB2 (I2C-bus interface) . . . . . . . . . . 18 7.1.20 OSC: oscillator . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1.21 RES: reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 Block diagram functions . . . . . . . . . . . . . . . . . 18 7.2.1 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2.2 Address counter . . . . . . . . . . . . . . . . . . . . . . . 18 7.2.3 Display data RAM . . . . . . . . . . . . . . . . . . . . . . 18 7.2.4 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 18 7.2.5 Display address counter . . . . . . . . . . . . . . . . . 19 7.2.6 LCD row and column drivers . . . . . . . . . . . . . 19 8 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1 Display data RAM structure . . . . . . . . . . . . . . 20 8.1.1 Basic command set . . . . . . . . . . . . . . . . . . . . 20 8.1.2 Extended command set . . . . . . . . . . . . . . . . . 21 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 8.1.2.1 8.1.2.2 8.1.2.3 9 9.1 10 10.1 10.1.1 10.1.2 10.2 10.2.1 10.2.2 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.3 12 12.1 12.1.1 12.1.2 12.1.3 12.2 12.3 12.3.1 12.3.2 12.4 12.5 12.5.1 12.5.2 12.6 12.7 12.8 12.9 12.10 12.10.1 12.10.2 12.11 13 14 15 Horizontal/vertical addressing . . . . . . . . . . . . Data order . . . . . . . . . . . . . . . . . . . . . . . . . . . Features available in both command sets . . . Parallel interface . . . . . . . . . . . . . . . . . . . . . . . 6800 series parallel interface . . . . . . . . . . . . . Serial interfacing (SPI and serial interface) . Serial peripheral interface lines . . . . . . . . . . . Write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . Read mode (only extended command set) . . Serial interface (3-line) . . . . . . . . . . . . . . . . . . Write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . Read mode (only extended command set) . . I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . Characteristics of the I2C-bus (Hs-mode) . . . System configuration . . . . . . . . . . . . . . . . . . . Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . Start and stop conditions . . . . . . . . . . . . . . . . Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus Hs-mode protocol . . . . . . . . . . . . . . . Command decoder. . . . . . . . . . . . . . . . . . . . . Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction set commands . . . . . . . . . . . . . . . Common instructions of the basic and extended command set . . . . . . . . . . . . . . . . . Specific commands of the basic command set Specific commands of the extended command set . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . Reset function . . . . . . . . . . . . . . . . . . . . . . . . Basic command set . . . . . . . . . . . . . . . . . . . . Extended command set . . . . . . . . . . . . . . . . . Power-save mode. . . . . . . . . . . . . . . . . . . . . . Display control . . . . . . . . . . . . . . . . . . . . . . . . Bit MX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit MY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Y address of RAM . . . . . . . . . . . . . . . . . . Set X address of RAM . . . . . . . . . . . . . . . . . . Set display start line . . . . . . . . . . . . . . . . . . . . Bias levels . . . . . . . . . . . . . . . . . . . . . . . . . . . Set VOP value . . . . . . . . . . . . . . . . . . . . . . . . . Basic command set . . . . . . . . . . . . . . . . . . . . Extended command set . . . . . . . . . . . . . . . . . Temperature control . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . 21 22 23 25 25 26 26 26 28 28 28 30 31 31 31 32 32 32 33 36 36 40 40 41 42 43 43 43 43 44 44 44 45 45 45 45 47 49 49 54 54 56 56 57 continued >> PCF8811_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 27 June 2008 80 of 81 NXP Semiconductors PCF8811 80 x 128 pixels matrix LCD driver 59 59 61 64 67 69 69 69 70 70 71 72 72 72 73 73 75 75 76 76 77 78 79 79 79 79 79 79 80 16 Dynamic characteristics . . . . . . . . . . . . . . . . . 16.1 Parallel interface timing characteristics. . . . . . 16.2 Serial interface timing characteristics . . . . . . . 16.3 I2C-bus interface timing characteristics . . . . . 17 Application information. . . . . . . . . . . . . . . . . . 18 Support information . . . . . . . . . . . . . . . . . . . . 18.1 Module maker programming . . . . . . . . . . . . . . 18.1.1 VLCD calibration. . . . . . . . . . . . . . . . . . . . . . . . 18.1.2 Temperature coefficient selection . . . . . . . . . . 18.1.3 Seal bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.4 OTP architecture. . . . . . . . . . . . . . . . . . . . . . . 18.1.5 Interface commands . . . . . . . . . . . . . . . . . . . . 18.1.5.1 CALMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.5.2 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.6 Example sequence for filling the shift register 18.1.7 Programming flow . . . . . . . . . . . . . . . . . . . . . . 18.1.8 Programming specification . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Handling information. . . . . . . . . . . . . . . . . . . . 21 Packing information. . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 26 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 June 2008 Document identifier: PCF8811_4