PMGD8000LN,115

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PMGD8000LN Dual µTrenchMOS™ logic level FET Rev. 01 — 27 February 2003 MBD128 Product data 1. Description Dual N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. Product availability: PMGD8000LN in SOT363 (SC-88). 2. Features ■ ■ ■ ■ TrenchMOS™ technology Very fast switching Logic level compatible Subminiature surface mount package. 3. Applications ■ Battery management ■ High-speed switch ■ Low power DC-to-DC converter. 4. Pinning information Table 1: Pinning - SOT363 (SC-88), simplified outline and symbol Pin Description 1 source (s1) 2 gate (g1) 3 drain (d2) 4 source (s2) 5 gate (g2) 6 drain (d1) Simplified outline 6 5 4 1 2 3 Symbol d1 s1 Top view MSA370 SOT363 (SC-88) d2 g1 s2 g2 MSD901 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj 150 °C - 30 V ID drain current (DC) Tamb = 25 °C; VGS = 4 V - 125 mA Ptot total power dissipation Tamb = 25 °C - 0.2 W Tj junction temperature - 150 °C RDSon drain-source on-state resistance VGS = 4 V; ID = 10 mA 1.8 8 Ω VGS = 2.5 V; ID = 1 mA 2.9 13 Ω Conditions Min Max Unit 25 °C ≤ Tj 150 °C - 30 V - ±15 V Tamb = 25 °C; VGS = 4 V; Figure 2 and 3 - 125 mA Tamb = 70 °C; VGS = 4 V; Figure 2 - 100 mA 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS drain-source voltage (DC) VGS gate-source voltage (DC) ID drain current (DC) IDM peak drain current Tamb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 250 mA Ptot total power dissipation Tamb = 25 °C; Figure 1 - 0.2 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C - 125 mA Source-drain diode IS source (diode forward) current (DC) Tamb = 25 °C © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 2 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 03aa11 120 03aa19 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 200 Tamb (°C) 0 P tot P der = ---------------------- × 100% P ° 50 100 150 200 Tamb (°C) ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of ambient temperature. Fig 2. Normalized continuous drain current as a function of ambient temperature. 03ah13 1 ID (A) Limit RDSon = VDS / ID tp = 10 µ s 1 ms 10-1 10 ms DC 100 ms 10-2 10-3 1 10 VDS (V) 102 Tamb = 25 °C; IDM is single pulse; VGS = 4 V. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 3 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 7. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter thermal resistance from junction to ambient Rth(j-a) Conditions Min Typ Max Unit minimum footprint; mounted on a PCB; vertical in still air - - 625 K/W 7.1 Transient thermal impedance 03ah12 103 Zth(j-a) (K/W) δ = 0.5 0.2 102 0.1 0.05 0.02 single pulse 10 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Tamb = 25 °C Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 4 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ID = 10 µA; VGS = 0 V 30 - - V 0.8 - 1.5 V Tj = 25 °C - 0.01 1.0 µA Tj = 55 °C - - 10 µA - 10 100 nA Tj = 25 °C - 1.8 8 Ω Tj = 150 °C - 2.9 12.8 Ω Tj = 25 °C - 2.9 13 Ω Tj = 150 °C - 4.6 21 Ω Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) gate-source threshold voltage ID = 100 µA; VDS = VGS; Figure 9 IDSS drain-source leakage current VDS = 30 V; VGS = 0 V IGSS gate-source leakage current VGS = ±10 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 4 V; ID = 10 mA; Figure 7 and 8 VGS = 2.5 V; ID = 1 mA; Figure 7 and 8 Dynamic characteristics Qg(tot) total gate charge - 350 - pC Qgs gate-source charge VDD = 10 V; VGS = 4.5 V; ID = 0.1 A; Figure 13 - 60 - pC Qgd gate-drain (Miller) charge - 120 - pC Ciss input capacitance - 18.5 - pF VGS = 0 V; VDS = 5 V; f = 1 MHz; Figure 11 Coss output capacitance - 12.5 - pF Crss reverse transfer capacitance - 9 - pF td(on) turn-on delay time - 10 - ns tr rise time - 7 - ns td(off) turn-off delay time - 15 - ns tf fall time - 7 - ns - 0.77 1.35 V VDD = 3 V; RL = 100 Ω; VGS = 4.5 V; RG = 6 Ω Source-drain diode VSD source-drain (diode forward) voltage IS = 0.1 A; VGS = 0 V; Figure 12 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 5 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 03ah14 0.25 ID (A) 5 V 4 V 3.5 V 3V 0.2 03ah16 0.5 VDS > ID x RDSon ID (A) 0.4 25 °C 0.15 0.3 Tj = 150 °C VGS = 2.5 V 0.1 0.2 0.05 0.1 0 0 0 0.2 0.4 VDS (V) 0.6 Tj = 25 °C 0 2 3 VGS (V) 4 Tj = 25 °C and 150 °C; VDS > ID × RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03ah15 4 Tj = 25 °C RDSon (Ω) 1 VGS = 2.5 V 03af18 2 a 3 1.5 3V 3.5 V 4V 5V 2 1 1 0.5 0 0 0 0.05 0.1 0.15 0.2 ID (A) 0.25 Tj = 25 °C -60 0 60 120 Tj (°C) 180 R DSon a = --------------------------R ° DSon ( 25 C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 6 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 03ah20 2 VGS(th) (V) ID (A) max 1.5 03ah77 10-3 10-4 typ min typ max 1 min 10-5 0.5 10-6 0 -60 0 60 120 Tj (°C) 180 0 ID = 100 µA; VDS = VGS 0.5 1 1.5 VGS (V) 2 Tj = 25 °C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03ah18 102 C (pF) Ciss 10 Coss Crss 1 10-1 1 10 2 VDS (V) 10 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 7 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 03ah17 0.25 IS (A) 0.2 03ah19 5 VGS (V) 4 VGS = 0 V ID = 100 mA VDD = 10 V Tj = 25 °C 0.15 3 0.1 2 150 °C 0.05 Tj = 25 °C 0 1 0 0 0.2 0.4 0.6 0.8 1 VSD (V) Tj = 25 °C and 150 °C; VGS = 0 V 0 200 300 QG (pC) 400 ID = 100 mA; VDD = 10 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data 100 Rev. 01 — 27 February 2003 8 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 9. Package outline Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC EIAJ SC-88 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Fig 14. SOT363 (SC-88). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 9 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 10. Revision history Table 6: Revision history Rev Date 01 20030227 CPCN Description - Product data (9397 750 10939) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Product data Rev. 01 — 27 February 2003 10 of 12 PMGD8000LN Philips Semiconductors Dual µTrenchMOS™ logic level FET 11. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 12. Definitions 13. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 14. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10939 Rev. 01 — 27 February 2003 11 of 12 Philips Semiconductors PMGD8000LN Dual µTrenchMOS™ logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 27 February 2003 Document order number: 9397 750 10939