S9S12VR64AF0CLC

MC9S12VR-Family Reference Manual S12 Microcontrollers MC9S12VRRMV3 Rev. 3.11 October 10, 2013 freescale.com To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the device overview section. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual. Revision History Date Revision Level 14-August-2013 Rev 3.9 • Updated Equation for Jitter J(N) Appendix E 16-August-2013 Rev 3.10 • Changed HBM Test Condition Number of Pulse per Pin from 3 to 1 Table A-3 Rev 3.11 • • • • • • • • • • • 10-October-2013 Description Added Num 4 VSENSE input voltage to Table A-2 Added REXT_HVI to HVI input voltage Table A-2 Moved Num 2 & 3 voltage differences from Table C-1 to Table A-5 Removed Num 1 & 4 from Table C-1 VRH/VRL connected to VDDA/VSSA Added TJ to Table B-1 Num 12 Removed Table C-4 3.3V conversion performence Added HSDRV Static and Dynamic Characteristics for 5V operation Updated S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) Updated LIN Physical Layer (S12LINPHYV2) Updated 64 KByte Flash Module (S12FTMRG64K512V1) Updated Device Overview MC9S12VR-Family Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 2 Chapter 1 Device Overview MC9S12VR-Family . . . . . . . . . . . . . . . . . . . . 21 Chapter 2 Port Integration Module (S12VRPIMV2) . . . . . . . . . . . . . . . . . . 51 Chapter 3 S12G Memory Map Controller (S12GMMCV1) . . . . . . . . . . . . 103 Chapter 4 S12 Clock, Reset and Power Unit (S12CPMU_UHV) . . . . . . . 115 Chapter 5 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . 173 Chapter 6 S12S Debug Module (S12DBGV2). . . . . . . . . . . . . . . . . . . . . . 197 Chapter 7 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . . 241 Chapter 8 Analog-to-Digital Converter (ADC12B6CV2) . . . . . . . . . . . . . 249 Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) . . . . . . . . . . . . . . 273 Chapter 10 Serial Communication Interface (S12SCIV6) . . . . . . . . . . . . . 303 Chapter 11 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . 343 Chapter 12 Timer Module (TIM16B4CV3) . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Chapter 13 High-Side Drivers - HSDRV (S12HSDRVV2). . . . . . . . . . . . . . 387 Chapter 14 Low-Side Drivers - LSDRV (S12LSDRV1). . . . . . . . . . . . . . . . 397 Chapter 15 LIN Physical Layer (S12LINPHYV2) . . . . . . . . . . . . . . . . . . . . 409 Chapter 16 Supply Voltage Sensor - (BATSV2). . . . . . . . . . . . . . . . . . . . . 431 Chapter 17 64 KByte Flash Module (S12FTMRG64K512V1). . . . . . . . . . . 443 Appendix A MCU Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 495 Appendix B VREG Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 509 Appendix C ATD Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 511 Appendix D HSDRV Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . 517 Appendix E PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 519 Appendix F IRC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Appendix G LINPHY Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 525 Appendix H LSDRV Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 529 Appendix I BATS Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 531 Appendix J PIM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 535 Appendix K SPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 537 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 3 Appendix L XOSCLCP Electrical Specifications . . . . . . . . . . . . . . . . . . . . 543 Appendix M FTMRG Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 545 Appendix N Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Appendix O Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Appendix P Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . 557 MC9S12VR Family Reference Manual, Rev. 3.11 4 Freescale Semiconductor Chapter 1 Device Overview MC9S12VR-Family 1.1 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.2.1 MC9S12VR-Family Member Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.1 HCS12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.4 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.5 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.6 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.7 Clock and Power Management Unit (CPMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.8 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.9 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.10 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.11 LIN physical layer transceiver (LINPHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.13 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.14 Analog-to-Digital Converter Module (ATD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.15 Supply Voltage Sense (BATS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.16 On-Chip Voltage Regulator system (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.17 Low-side drivers (LSDRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.18 High-side drivers (HSDRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.19 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.20 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.1 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.8 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.8.1 Pinout 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.8.2 Pinout 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.9.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.9.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 5 1.12 1.13 1.14 1.15 1.16 1.17 API external clock output (API_EXTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash IFR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ADC External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ADC Special Conversion Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ADC Result Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 2 Port Integration Module (S12VRPIMV2) 2.1 2.2 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.3.3 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.4 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.5 Port E, BKGD pin Pull Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.6 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.7 PIM Miscellaneous Register (PIMMISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.8 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.9 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.10 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.11 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.12 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.13 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.14 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.15 Module Routing Register 0 (MODRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.16 Module Routing Register 1 (MODRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.17 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.18 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.19 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.20 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.21 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.3.22 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.3.23 Module Routing Register 2 (MODRR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.3.24 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.25 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.3.26 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.3.27 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.28 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.3.29 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.30 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.31 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MC9S12VR Family Reference Manual, Rev. 3.11 6 Freescale Semiconductor 2.4 2.5 2.3.32 Port L Input Register (PTIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.33 Port L Digital Input Enable Register (DIENL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.34 Port L Analog Access Register (PTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.3.35 Port L Input Divider Ratio Selection Register (PIRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.36 Port L Polarity Select Register (PPSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.37 Port L Interrupt Enable Register (PIEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.38 Port L Interrupt Flag Register (PIFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.39 Port AD Data Register (PT1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.3.40 Port AD Input Register (PTI1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.3.41 Port AD Data Direction Register (DDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.3.42 Port AD Pull Enable Register (PER1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.3.43 Port AD Polarity Select Register (PPS1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.3.44 Port AD Interrupt Enable Register (PIE1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.3.45 Port AD Interrupt Flag Register (PIF1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.5.2 ADC External Triggers ETRIG1-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.5.3 Over-Current Protection on EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.5.4 Open Input Detection on HVI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Chapter 3 S12G Memory Map Controller (S12GMMCV1) 3.1 3.2 3.3 3.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.4.3 Unimplemented and Reserved Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.4.4 Prioritization of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 7 Chapter 4 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.1.3 S12CPMU_UHV Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.2.3 VSUP — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.2.4 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.2.5 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.2.6 VSS— Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.2.7 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.2.8 VDD— Internal Regulator Output Supply (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . 124 4.2.9 VDDF— Internal Regulator Output Supply (NVM Logic) . . . . . . . . . . . . . . . . . . . . . . 124 4.2.10 TEMPSENSE — Internal Temperature Sensor Output Voltage . . . . . . . . . . . . . . . . . . 124 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.4.3 Stop Mode using PLLCLK as source of the Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . 162 4.4.4 Full Stop Mode using Oscillator Clock as source of the Bus Clock . . . . . . . . . . . . . . . 163 4.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 4.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.7.1 General Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Chapter 5 Background Debug Module (S12SBDMV1) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 MC9S12VR Family Reference Manual, Rev. 3.11 8 Freescale Semiconductor 5.2 5.3 5.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 5.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Chapter 6 S12S Debug Module (S12DBGV2) 6.1 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 6.4.1 S12DBGV2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 6.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 6.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 6.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 9 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Chapter 7 Interrupt Module (S12SINTV1) 7.1 7.2 7.3 7.4 7.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 7.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 7.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 7.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 7.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 7.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Chapter 8 Analog-to-Digital Converter (ADC12B6CV2) 8.1 8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 8.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 8.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 MC9S12VR Family Reference Manual, Rev. 3.11 10 Freescale Semiconductor Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2) 9.1 9.2 9.3 9.4 9.5 9.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 9.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 9.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Chapter 10 Serial Communication Interface (S12SCIV6) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 10.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 10.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 10.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 10.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 10.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 10.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 10.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 10.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 10.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 10.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 10.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 10.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 10.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 10.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 10.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 10.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 11 10.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Chapter 11 Serial Peripheral Interface (S12SPIV5) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 11.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 11.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 11.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 11.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 11.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 11.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 11.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 11.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 11.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 11.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 11.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Chapter 12 Timer Module (TIM16B4CV3) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.2.1 IOC3 - IOC0 — Input Capture and Output Compare Channel 3-0 . . . . . . . . . . . . . . . . 371 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 12.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 12.6.1 Channel [3:0] Interrupt (C[3:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 MC9S12VR Family Reference Manual, Rev. 3.11 12 Freescale Semiconductor 12.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Chapter 13 High-Side Drivers - HSDRV (S12HSDRVV2) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 13.2.1 HS0, HS1— High Side Driver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 13.2.2 VSUPHS — High Side Driver Power Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 13.3.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 13.3.3 Port HS Data Register (HSDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 13.3.4 HSDRV Configuration Register (HSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 13.3.5 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 13.3.6 HSDRV Interrupt Enable Register (HSIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 13.3.7 HSDRV Interrupt Flag Register (HSIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 13.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 13.4.2 Over-Current Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 13.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Chapter 14 Low-Side Drivers - LSDRV (S12LSDRV1) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 14.2.1 LS0, LS1— Low Side Driver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 14.2.2 LSGND — Low Side Driver Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 14.3.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 14.3.3 Port LS Data Register (LSDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 14.3.4 LSDRV Configuration Register (LSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 14.3.5 LSDRV Status Register (LSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 14.3.6 LSDRV Interrupt Enable Register (LSIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 14.3.7 LSDRV Interrupt Flag Register (LSIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 14.4.2 Open-Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 13 14.4.3 Over-Current Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 14.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Chapter 15 LIN Physical Layer (S12LINPHYV2) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.2.1 LIN — LIN Bus Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.2.2 LGND — LIN Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.2.3 VLINSUP — Positive Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.2.4 LPTxD — LIN Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.2.5 LPRxD — LIN Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.4.2 Slew Rate and LIN Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.4.3 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 15.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 15.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 15.5.1 Module Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 15.5.2 Interrupt handling in Interrupt Service Routine (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Chapter 16 Supply Voltage Sensor - (BATSV2) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 16.2.1 VSENSE — Supply (Battery) Voltage Sense Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 16.2.2 VSUP — Voltage Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 16.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 16.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 16.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 MC9S12VR Family Reference Manual, Rev. 3.11 14 Freescale Semiconductor Chapter 17 64 KByte Flash Module (S12FTMRG64K512V1) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 17.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 17.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 476 17.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 17.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 17.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 17.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 493 17.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 493 17.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Appendix A MCU Electrical Specifications A.1 General A.1.1 A.1.2 A.1.3 A.1.4 A.1.5 A.1.6 A.1.7 A.1.8 A.1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 15 Appendix B VREG Electrical Specifications Appendix C ATD Electrical Specifications C.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 C.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 C.2.1 Port AD Output Drivers Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 C.2.2 Source Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 C.2.3 Source Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 C.2.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 C.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 C.3.1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 C.3.2 ATD Analog Input Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 Appendix D HSDRV Electrical Specifications D.1 Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 D.2 Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 D.3 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 Appendix E PLL Electrical Specifications E.1 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 E.1.1 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Appendix F IRC Electrical Specifications Appendix G LINPHY Electrical Specifications G.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 G.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 G.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Appendix H LSDRV Electrical Specifications H.1 Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 H.2 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Appendix I BATS Electrical Specifications I.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 MC9S12VR Family Reference Manual, Rev. 3.11 16 Freescale Semiconductor I.2 I.3 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Appendix J PIM Electrical Specifications J.1 J.2 High-Voltage Inputs (HVI) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Pin Interrupt Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 Appendix K SPI Electrical Specifications K.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 K.1.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 K.1.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 Appendix L XOSCLCP Electrical Specifications Appendix M FTMRG Electrical Specifications M.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 M.1.1 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 M.1.2 NVM Factory Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Appendix N Package Information Appendix O Ordering Information Appendix P Detailed Register Address Map P.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 17 MC9S12VR Family Reference Manual, Rev. 3.11 18 Freescale Semiconductor Chapter 1 Device Overview MC9S12VR-Family Revision History Version Number Revision Date Rev 3.0 13-October-2012 Rev 3.1 3-July-2013 Rev 3.2 4-August-2013 Rev 3.3 23-September-2013 1.1 Description of Changes • Maskset and Part ID changed • Added Section 1.14 Flash IFR Mapping • Updated Section 1.17 ADC Result Reference • Section 1.3 & 1.4.4 4-20 MHz XOSCLCP • Section 1.7.2.16 Added VLINSUP description • Section 1.4.5 Removed temperature range from feature list, this is specified in Appendix F • Section 1.8.1 Added API_EXTCLK to pinout pin PS2 • Corrected Table 1-10 High Temperature Interrupt cannot wake up MCU from STOP • Corrected Table 1-10 Local enable and wake up for SCI0 and SCI1 Introduction The MC9S12VR-Family is an optimized automotive 16-bit microcontroller product line focused on low-cost, high-performance, and low pin-count. This family integrates an S12 microcontroller with a LIN Physical interface, a 5V regulator system to supply the microcontroller, and analog blocks to control other elements of the system which operate at vehicle battery level (e.g. relay drivers, high-side driver outputs, wake up inputs). The MC9S12VR-Family is targeted at generic automotive applications requiring single node LIN communications. Typical examples of these applications include window lift modules, seat modules and sun-roof modules to name a few. The MC9S12VR-Family uses many of the same features found on the MC9S12G family, including error correction code (ECC) on flash memory, EEPROM for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12VR-Family delivers an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings. The MC9S12VR-Family delivers all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS family, the MC9S12VR-Family will run 16-bit wide accesses without wait states for all peripherals and memories. Misaligned single cycle 16 bit RAM access is not supported. The MC9S12VR-Family will be available in 32-pin and 48-pin LQFP. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. The MC9S12VR-Family is a general-purpose family of devices created with relay based motor control in mind and is suitable for a range of applications, including: MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 19 Device Overview MC9S12VR-Family • • • • • 1.2 Window lift modules Door modules Seat controllers Smart actuators Sun roof modules Features This section describes the key features of the MC9S12VR-Family. 1.2.1 MC9S12VR-Family Member Comparison Table 1-1 provides a summary of different members of the MC9S12VR-Family and their features. This information is intended to provide an understanding of the range of functionality offered by this microcontroller family. Table 1-1. MC9S12VR - Family Feature MC9S12VR48 CPU MC9S12VR64 HCS12 Flash memory (ECC) 48 Kbytes 64 Kbytes EEPROM (ECC) 512 Bytes RAM 2 Kbytes LIN physical layer 1 SPI 1 SCI Up to 2 Timer 4ch x 16-bit PWM 8ch x 8-bit or 4ch x 16-bit ADC 6 ch x 10-bit available on external pins and four internal channels. see Table 1-13. Frequency modulated PLL Yes Internal 1 MHz RC oscillator Yes Autonomous window watchdog 1 Low-side drivers (protected for inductive loads) 2 High-side drivers High voltage Inputs General purpose I/Os (5V) Direct battery sense pin Up to 2 4 Up to 28 Yes MC9S12VR Family Reference Manual, Rev. 3.11 20 Freescale Semiconductor Device Overview MC9S12VR-Family Feature Supply voltage sense Chip temperature sensor Supply voltage EVDD output current 1.3 MC9S12VR48 MC9S12VR64 Yes 1 general sensor VSUP = 6V – 18 V (normal operation) up to 40V (protected operation) 20mA @ 5V Maximum execution speed 25 MHz Package 32 LQFP 48 LQFP Chip-Level Features On-chip modules available within the family include the following features: • HCS12 CPU core • 64 or 48 Kbyte on-chip flash with ECC • 512 byte EEPROM with ECC • 2 Kbyte on-chip SRAM • Phase locked loop (IPLL) frequency multiplier with internal filter • 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range • 4-20 MHz amplitude controlled pierce oscillator • Internal COP (watchdog) module (with separate clock source) • Timer module (TIM) supporting input/output channels that provide a range of 16-bit input capture, output compare and counter (up to 4 channels) • Pulse width modulation (PWM) module (up to 8 x 8-bit channels) • 10-bit resolution successive approximation analog-to-digital converter (ADC) with up to 6 channels available on external pins • One serial peripheral interface (SPI) module • One serial communication interface (SCI) module supporting LIN communications (with RX connected to a timer channel for internal oscillator calibration purposes, if desired) • Up to one additional SCI (not connected to LIN physical layer) • One on-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard & SAE J2602-2 LIN standard • On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages • Autonomous periodic interrupt (API) (combination with cyclic, watchdog) • Two protected low-side outputs to drive inductive loads • Up to two protected high-side outputs • 4 high-voltage inputs with wake-up capability and readable internally on ADC • Up to two 10mA high-current outputs MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 21 Device Overview MC9S12VR-Family • • • 1.4 20mA high-current output for use as Hall sensor supply Battery voltage sense with low battery warning, internally reverse battery protected Chip temperature sensor Module Features The following sections provide more details of the modules implemented on the MC9S12VR-Family. 1.4.1 HCS12 16-Bit Central Processor Unit (CPU) The HCS12 CPU is a high-speed, 16-bit processing unit that has a programming model identical to that of the industry standard M68HC11 central processor unit (CPU). • Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution • Supports instructions with odd byte counts, including many single-byte instructions. This allows much more efficient use of ROM space. • Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode — Accumulator offsets using A, B, or D accumulators — Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8) 1.4.2 On-Chip Flash with ECC On-chip flash memory on the MC9S12VR features the following: • 64 or 48 Kbyte of program flash memory — Automated program and erase algorithm — Protection scheme to prevent accidental program or erase • 512 Byte EEPROM — 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 4 bytes — Automated program and erase algorithm — User margin level setting for reads 1.4.3 • On-Chip SRAM 2 Kbytes of general-purpose RAM MC9S12VR Family Reference Manual, Rev. 3.11 22 Freescale Semiconductor Device Overview MC9S12VR-Family 1.4.4 • 1.4.5 • 1.4.6 • 1.4.7 • • • 1.4.8 • • • • Main External Oscillator (XOSCLCP) Loop control Pierce oscillator using 4 MHz to 20 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals — Oscillator pins shared with GPIO functionality Internal RC Oscillator (IRC) Factory trimmed internal reference clock — 1 MHz internal RC oscillator with ±1.3% accuracy over rated temperature range Internal Phase-Locked Loop (IPLL) Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – Internal 1 MHz RC oscillator (IRC) Clock and Power Management Unit (CPMU) Real time interrupt (RTI) Clock monitor (CM) System reset generation System Integrity Support Power-on reset (POR) Illegal address detection with reset Low-voltage detection with interrupt or reset Computer operating properly (COP) watchdog with option to run on internal RC oscillator — Configurable as window COP for enhanced failure detection — Can be initialized out of reset using option bits located in flash memory MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 23 Device Overview MC9S12VR-Family • Clock monitor supervising the correct function of the oscillator 1.4.9 • • Timer (TIM) Up to 4 x 16-bit channels for input capture or output compare 16-bit free-running counter with 8-bit precision prescaler 1.4.10 • Up to eight 8-bit channels or reconfigurable four 16-bit channel PWM resolution — Programmable period and duty cycle per channel — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies 1.4.11 • • • • • • • • • • LIN physical layer transceiver (LINPHY) Compliant with LIN Physical Layer 2.2 specification. Compliant with the SAE J2602-2 LIN standard. Standby mode with glitch-filtered wake-up. Slew rate selection optimized for the baud rates: 10.4kBit/s, 20kBit/s and Fast Mode (up to 250kBit/s). Switchable 34kΩ/330kΩ pull-ups (in shutdown mode, 330kΩ only) Current limitation for LIN Bus pin falling edge. Over-current protection. LIN TxD-dominant timeout feature monitoring the LPTxD signal. Automatic transmitter shutdown in case of an over-current or TxD-dominant timeout. Fulfills the OEM “Hardware Requirements for LIN (CAN and FlexRay) Interfaces in Automotive Applications” v1.3. 1.4.12 • • • • • • Pulse Width Modulation Module (PWM) Serial Peripheral Interface Module (SPI) Configurable 8- or 16-bit data size Full-duplex or single-wire bidirectional Double-buffered transmit and receive Master or slave MSB-first or LSB-first shifting Serial clock phase and polarity options MC9S12VR Family Reference Manual, Rev. 3.11 24 Freescale Semiconductor Device Overview MC9S12VR-Family 1.4.13 • • • • • • • • • Serial Communication Interface Module (SCI) Full-duplex or single-wire operation Standard mark/space non-return-to-zero (NRZ) format Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths 16-bit baud rate selection Programmable character length Programmable polarity for transmitter and receiver Active edge receive wake-up Break detect and transmit collision detect supporting LIN Internal connection to one SCI routable to external pins 1.4.14 Analog-to-Digital Converter Module (ATD) • Up to 6-channel, 10-bit analog-to-digital converter — 8-/10-bit resolution — 3 us, 10-bit single conversion time — Left or right justified result data — Internal oscillator for conversion in stop modes — Continuous conversion mode — Multiple channel scans • Pins can also be used as digital I/O • Up to 6 pins can be used as keyboard wake-up interrupt (KWI) • Internal voltages monitored with the ATD module — VSUP, VSENSE, chip temperature sensor, high voltage inputs,VRH, VRL, VDDF 1.4.15 • • VSENSE & VSUP pin low or a high voltage interrupt VSENSE & VSUP pin can be routed via an internal divider to the internal ADC 1.4.16 • • Supply Voltage Sense (BATS) On-Chip Voltage Regulator system (VREG) Voltage regulator — Linear voltage regulator directly supplied by VSUP (protected VBAT) — Low-voltage detect with low-voltage interrupt on VSUP — Capable of supplying both the MCU internally and providing additional external current (approximately 20mA) to supply other components within the electronic control unit. — Over-temperature protection and interrupt Internal Voltage regulator — Linear voltage regulator with bandgap reference MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 25 Device Overview MC9S12VR-Family — Low-voltage detect with low-voltage interrupt on VDDA — Power-on reset (POR) circuit — Low-voltage reset (LVR) 1.4.17 • • • • • • 2x low-side drivers targeted for up to approximately 150mA current capability. Internal timer or PWM channels can be routed to control the low-side drivers Open-load detection Over-current protection with shutdown and interrupt Active clamp (for driving relays) Recirculation detection 1.4.18 • • • • • • Background Debug (BDM) Background debug module (BDM) with single-wire interface — Non-intrusive memory access commands — Supports in-circuit programming of on-chip nonvolatile memory 1.4.20 • • High-side drivers (HSDRV) 2 High-side drivers targeted for up to approximately 50mA current capability Internal timer or PWM channels can be routed to control the high-side drivers Over-current protection with shutdown and interrupt 1.4.19 • Low-side drivers (LSDRV) Debugger (DBG) Trace buffer with depth of 64 entries Three comparators (A, B and C) — Access address comparisons with optional data comparisons — Program counter comparisons — Exact address or address range comparisons Two types of comparator matches — Tagged This matches just before a specific instruction begins execution — Force This is valid on the first instruction boundary after a match occurs Four trace modes Four stage state sequencer MC9S12VR Family Reference Manual, Rev. 3.11 26 Freescale Semiconductor Device Overview MC9S12VR-Family 1.5 Block Diagram Figure 1-1. MC9S12VR Block Diagram VSUP VSS Voltage Regulator Input: 6V – 18V AN[5:0] IOC0 IOC1 IOC2 IOC3 TIM 16-bit 4 channel Timer CPU12-V1 PWM PE0 PE1 PTE BKGD RESET TEST Single-wire Background Debug Module EXTAL Low Power Pierce XTAL Oscillator Debug Module 3 comparators 64 Byte Trace Buffer Clock Monitor COP Watchdog Real Time Interrupt Auton. Periodic Int. PLL with Frequency Modulation option Internal RC Oscillator Reset Generation and Test Entry Interrupt Module PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 8-bit 8 channel Pulse Width Modulator PWM[7:6] see Pinout SCI1 Asynchronous Serial IF SCI0 Asynchronous Serial IF SPI0 RXD TXD RXD TXD MISO MOSI SCK SS PTL Synchronous Serial IF PL0 PL1 PL2 PL3 LIN LIN 5V IO Supply Output VDDX1/VSSX1 VDDX2/VSSX2 HSDRV 0 & 1 High Side Driver LSDRV 0 & 1 LGND LINPHY LGND LIN Physical Low Side Driver BATS Battery Sensor HS0 HS1 VSUPHS LS0 LS1 LSGND VSENSE PTAD 10-bit 6 channel Analog-Digital Converter PAD[5:0] PTT 512 bytes EEPROM with ECC VDDA VSSA PT0 PT1 PT2 PT3 PTP 2K bytes RAM ADC PP0 PP1 PP2 / EVDD PP3 PP4 PP5 PS0 PS1 PTS 48K & 64K bytes Flash with ECC PS2 PS3 PS4 PS5 HS0 HS1 VSUPHS LS0 LS1 LSGND VSENSE Block Diagram shows the maximum configuration! Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 27 Device Overview MC9S12VR-Family 1.6 Family Memory Map Table 1-2 shows the MC9S12VR-Family register memory map. Table 1-2. Device Register Memory Map Address Module Size (Bytes) 0x0000–0x0009 PIM (port integration module) 10 0x000A–0x000B MMC (memory map control) 2 0x000C–0x000D PIM (port integration module) 2 0x000E–0x000F Reserved 2 0x0010–0x0017 MMC (memory map control) 8 0x0018–0x0019 Reserved 2 0x001A–0x001B Device ID register 2 0x001C–0x001F PIM (port integration module) 4 0x0020–0x002F DBG (debug module) 16 0x0030–0x0033 Reserved 4 0x0034–0x003F CPMU (clock and power management) 12 0x0040–0x006F TIM (timer module TSCR1; - Correct typo: ECTxxx->TIMxxx - Correct reference: Figure 1-25 -> Figure 12-22 - Add description, “a counter overflow when TTOV[7] is set”, to be the condition of channel 7 override event. - Phrase the description of OC7M to make it more explicit -single source generate different channel guide 12.1 Introduction The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. This timer could contain up to 4 input capture/output compare channels . The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 12.1.1 Features The TIM16B4CV3 includes these distinctive features: • Up to 4 channels available. (refer to device specification for exact number) • All channels have same input capture/output compare functionality. • Clock prescaling. • 16-bit counter. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 367 Timer Module (TIM16B4CV3) 12.1.2 Modes of Operation Stop: Timer is off because clocks are stopped. Freeze: Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. 12.1.3 Block Diagrams Bus clock Timer overflow interrupt Prescaler 16-bit Counter Timer channel 0 interrupt Timer channel 1 interrupt Timer channel 2 interrupt Channel 0 Input capture Output compare Channel 1 Input capture Output compare Channel 2 Input capture Output compare Registers Channel 3 Input capture Output compare IOC0 IOC1 IOC2 IOC3 Timer channel 3 interrupt Figure 12-1. TIM16B4CV3 Block Diagram MC9S12VR Family Reference Manual, Rev. 3.11 368 Freescale Semiconductor Timer Module (TIM16B4CV3) 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 12-2. Interrupt Flag Setting 12.2 External Signal Description The TIM16B4CV3 module has a selected number of external pins. Refer to device specification for exact number. 12.2.1 IOC3 - IOC0 — Input Capture and Output Compare Channel 3-0 Those pins serve as input capture or output compare for TIM16B4CV3 channel . NOTE For the description of interrupts see Section 12.6, “Interrupts”. 12.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 12.3.1 Module Memory Map The memory map for the TIM16B4CV3 module is given below in Figure 12-3. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B4CV3 module and the address offset for each register. 12.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 369 Timer Module (TIM16B4CV3) Only bits related to implemented channels are valid. Register Name 0x0000 TIOS 0x0001 CFORC 0x0004 TCNTH 0x0005 TCNTL 0x0006 TSCR1 0x0007 TTOV 0x0008 TCTL1 0x0009 TCTL2 0x000A TCTL3 0x000B TCTL4 0x000C TIE 0x000D TSCR2 0x000E TFLG1 0x000F TFLG2 0x0010–0x001F TCxH–TCxL1 0x0024–0x002B Reserved 0x002C OCPD 0x002D Reserved 0x002E PTPSR 0x002F Reserved Bit 7 6 5 4 R RESERVE RESERVE RESERVE RESERVE D D D D W R 0 0 0 0 W RESERVE RESERVE RESERVE RESERVE D D D D R TCNT15 TCNT14 TCNT13 TCNT12 W R TCNT7 TCNT6 TCNT5 TCNT4 W R TEN TSWAI TSFRZ TFFCA W R RESERVE RESERVE RESERVE RESERVE D D D D W R W R W R W R W R W R W R W R W R W 2 1 Bit 0 IOS3 IOS2 IOS1 IOS0 0 0 0 0 FOC3 FOC2 FOC1 FOC0 TCNT11 TCNT10 TCNT9 TCNT8 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 TOV2 TOV1 TOV0 PRNT TOV3 RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE D D D D D D D D OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE D D D D D D D D EDG3B EDG3A EDG2B EDG2A RESERVE RESERVE RESERVE RESERVE D D D D TOI 0 0 0 RESERVE RESERVE RESERVE RESERVE D D D D TOF Bit 15 PTPS7 EDG1B EDG1A EDG0B EDG0A C3I C2I C1I C0I RESERVE D PR2 PR1 PR0 C3F C2F C1F C0F 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 OCPD3 OCPD2 OCPD1 OCPD0 PTPS3 PTPS2 PTPS1 PTPS0 R Bit 7 Bit 6 Bit 5 Bit 4 W R W R RESERVE RESERVE RESERVE RESERVE D D D D W R R W R W 3 PTPS6 PTPS5 PTPS4 Figure 12-3. TIM16B4CV3 Register Summary MC9S12VR Family Reference Manual, Rev. 3.11 370 Freescale Semiconductor Timer Module (TIM16B4CV3) 1 The register is available only if corresponding channel exists. 12.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 7 6 5 4 3 2 1 0 IOS3 IOS2 IOS1 IOS0 0 0 0 0 R RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 Figure 12-4. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime Write: Anytime Table 12-2. TIOS Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field 3:0 IOS[3:0] 12.3.2.2 Description Input Capture or Output Compare Channel Configuration 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare. Timer Compare Force Register (CFORC) Module Base + 0x0001 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 FOC3 FOC2 FOC1 FOC0 0 0 0 0 W RESERVED RESERVED RESERVED RESERVED Reset 0 0 0 0 Figure 12-5. Timer Compare Force Register (CFORC) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 12-3. CFORC Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 FOC[3:0] Note: Force Output Compare Action for Channel 3:0 — A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won’t get set. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 371 Timer Module (TIM16B4CV3) 12.3.2.3 Timer Count Register (TCNT) Module Base + 0x0004 15 14 13 12 11 10 9 9 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0 0 0 0 0 0 0 0 R W Reset Figure 12-6. Timer Count Register High (TCNTH) Module Base + 0x0005 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 R W Reset Figure 12-7. Timer Count Register Low (TCNTL) The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes . The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. 12.3.2.4 Timer System Control Register 1 (TSCR1) Module Base + 0x0006 7 6 5 4 3 TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 0 0 R 2 1 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-8. Timer System Control Register 1 (TSCR1) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 3.11 372 Freescale Semiconductor Timer Module (TIM16B4CV3) Table 12-4. TSCR1 Field Descriptions Field Description 7 TEN Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is generated by the timer prescaler. 6 TSWAI Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. 5 TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. 3 PRNT Precision Timer 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits. This bit is writable only once out of reset. 12.3.2.5 Timer Toggle On Overflow Register 1 (TTOV) Module Base + 0x0007 7 6 5 4 3 2 1 0 TOV3 TOV2 TOV1 TOV0 0 0 0 0 R RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 Figure 12-9. Timer Toggle On Overflow Register 1 (TTOV) Read: Anytime Write: Anytime MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 373 Timer Module (TIM16B4CV3) Table 12-5. TTOV Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 TOV[3:0] Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. 12.3.2.6 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 7 6 5 4 3 2 1 0 R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 0 0 0 0 Figure 12-10. Timer Control Register 1 (TCTL1) Module Base + 0x0009 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 R W Reset Figure 12-11. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 12-6. TCTL1/TCTL2 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero Field Description 3:0 OMx Output Mode — These four pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared. 3:0 OLx Output Level — These fourpairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared. MC9S12VR Family Reference Manual, Rev. 3.11 374 Freescale Semiconductor Timer Module (TIM16B4CV3) Table 12-7. Compare Result Output Action 12.3.2.7 OMx OLx Action 0 0 No output compare action on the timer output signal 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4) Module Base + 0x000A 7 6 5 4 3 2 1 0 R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 0 0 0 0 Figure 12-12. Timer Control Register 3 (TCTL3) Module Base + 0x000B 7 6 5 4 3 2 1 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 R W Reset Figure 12-13. Timer Control Register 4 (TCTL4) Read: Anytime Write: Anytime. Table 12-8. TCTL3/TCTL4 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field 3:0 EDGnB EDGnA Description Input Capture Edge Control — These four pairs of control bits configure the input capture edge detector circuits. Table 12-9. Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 375 Timer Module (TIM16B4CV3) Table 12-9. Edge Detector Circuit Configuration 12.3.2.8 EDGnB EDGnA Configuration 1 1 Capture on any edge (rising or falling) Timer Interrupt Enable Register (TIE) Module Base + 0x000C 7 6 5 4 3 2 1 0 C3I C2I C1I C0I 0 0 0 0 R RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 Figure 12-14. Timer Interrupt Enable Register (TIE) Read: Anytime Write: Anytime. Table 12-10. TIE Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero Field Description 3:0 C3I:C0I Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. 12.3.2.9 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R 6 5 4 0 0 0 TOI 3 2 1 0 RESERVED PR2 PR1 PR0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 12-15. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. MC9S12VR Family Reference Manual, Rev. 3.11 376 Freescale Semiconductor Timer Module (TIM16B4CV3) Table 12-11. TSCR2 Field Descriptions Field 7 TOI 2:0 PR[2:0] Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set. Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 12-12. Table 12-12. Timer Clock Selection PR2 PR1 PR0 Timer Clock 0 0 0 Bus Clock / 1 0 0 1 Bus Clock / 2 0 1 0 Bus Clock / 4 0 1 1 Bus Clock / 8 1 0 0 Bus Clock / 16 1 0 1 Bus Clock / 32 1 1 0 Bus Clock / 64 1 1 1 Bus Clock / 128 NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 12.3.2.10 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E 7 6 5 4 3 2 1 0 C3F C2F C1F C0F 0 0 0 0 R RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 Figure 12-16. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 377 Timer Module (TIM16B4CV3) Table 12-13. TRLG1 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field 3:0 C[3:0]F Description Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one. Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared. 12.3.2.11 Main Timer Interrupt Flag 2 (TFLG2) Module Base + 0x000F 7 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOF W Reset 0 Unimplemented or Reserved Figure 12-17. Main Timer Interrupt Flag 2 (TFLG2) TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one while TEN bit of TSCR1 . Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. Table 12-14. TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one . MC9S12VR Family Reference Manual, Rev. 3.11 378 Freescale Semiconductor Timer Module (TIM16B4CV3) 12.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0– 3(TCxH and TCxL) 0x0018=RESERVD 0x001A=RESERVD 0x001C=RESERVD 0x001E=RESERVD Module Base + 0x0010 = TC0H 0x0012 = TC1H 0x0014=TC2H 0x0016=TC3H 15 14 13 12 11 10 9 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 12-18. Timer Input Capture/Output Compare Register x High (TCxH) 0x0019 =RESERVD 0x001B=RESERVD 0x001D=RESERVD 0x001F=RESERVD Module Base + 0x0011 = TC0L 0x0013 = TC1L 0x0015 =TC2L 0x0017=TC3L 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 12-19. Timer Input Capture/Output Compare Register x Low (TCxL) 1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read: Anytime Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 379 Timer Module (TIM16B4CV3) 12.3.2.13 Output Compare Pin Disconnect Register(OCPD) Module Base + 0x002C 7 6 5 4 3 2 1 0 OCPD3 OCPD2 OCPD1 OCPD0 0 0 0 0 R RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 Figure 12-20. Output Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 12-15. OCPD Field Description Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 OCPD[3:0] Output Compare Pin Disconnect Bits 0 Enables the timer channel port. Output Compare action will occur on the channel pin. These bits do not affect the input capture . 1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output compare flag still become set. 12.3.2.14 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E 7 6 5 4 3 2 1 0 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0 0 0 0 0 0 0 0 R W Reset Figure 12-21. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12VR Family Reference Manual, Rev. 3.11 380 Freescale Semiconductor Timer Module (TIM16B4CV3) ... Table 12-16. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 12-17 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit: PRNT = 1 : Prescaler = PTPS[7:0] + 1 Table 12-17. Precision Timer Prescaler Selection Examples when PRNT = 1 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 1 1 4 - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 1 0 0 1 1 20 0 0 0 1 0 1 0 0 21 0 0 0 1 0 1 0 1 22 - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 0 253 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 12.4 Functional Description This section provides a complete functional description of the timer TIM16B4CV3 block. Please refer to the detailed timer block diagram in Figure 12-22 as necessary. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 381 Timer Module (TIM16B4CV3) PRE-PRESCALER PRNT tim source Clock PTPSR[7:0] PR[2:1:0] 1 MUX 0 PRESCALER CxI TCNT(hi):TCNT(lo) CxF 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 0 16-BIT COMPARATOR OM:OL0 TC0 EDG0A C0F C0F EDGE DETECT EDG0B CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0COMPARE TOV0 IOC0 PIN IOC0 CHANNEL 1 16-BIT COMPARATOR EDG1A C1F C1F OM:OL1 TC1 EDGE DETECT EDG1B CH. 1 CAPTURE IOC1 PIN LOGIC CH. 1 COMPARE TOV1 IOC1 PIN IOC1 CHANNEL2 CHANNELn-1 16-BIT COMPARATOR Cn-1F Cn-1F TCn-1 EDG(n-1)A EDG(n-1)B EDGE DETECT CH.n-1 CAPTURE IOCn-1 PIN LOGIC CH. n-1COMPAREIOCn-1 PIN OM:OLn-1 TOVn-1 IOCn-1 n is channels number. Figure 12-22. Detailed Timer Block Diagram 12.4.1 Prescaler The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. MC9S12VR Family Reference Manual, Rev. 3.11 382 Freescale Semiconductor Timer Module (TIM16B4CV3) By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by using PTPSR[7:0] bits of PTPSR register generating divide by 1, 2, 3, 4,....20, 21, 22, 23,......255, or 256. 12.4.2 Input Capture Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx. The minimum pulse width for the input capture input is greater than two Bus clocks. An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF). 12.4.3 Output Compare Setting the I/O select bit, IOSx, configures channel x when available as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF). The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx results in no output compare action on the output compare channel pin. Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel flag. Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. 12.4.3.1 OC Channel Initialization The internal register whose output drives OCx can be programmed before the timer drives OCx. The desired state can be programmed to this internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 383 Timer Module (TIM16B4CV3) Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero. 12.5 Resets The reset state of each individual bit is listed within Section 12.3, “Memory Map and Register Definition” which details the registers and their bit fields 12.6 Interrupts This section describes interrupts originated by the TIM16B4CV3 block. Table 12-18 lists the interrupts generated by the TIM16B4CV3 to communicate with the MCU. Table 12-18. TIM16B4CV3 Interrupts Interrupt Offset Vector Priority Source Description C[3:0]F — — — Timer Channel 3–0 Active high timer channel interrupts 3–0 TOF — — — Timer Overflow Timer Overflow interrupt The TIM16B4CV3 could use up to 5 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. 12.6.1 Channel [3:0] Interrupt (C[3:0]F) This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt. The TIM block only generates the interrupt and does not service it. Only bits related to implemented channels are valid. 12.6.2 Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12VR Family Reference Manual, Rev. 3.11 384 Freescale Semiconductor Chapter 13 High-Side Drivers - HSDRV (S12HSDRVV2) Table 13-1. Revision History Table Rev. No. Date (Item No.) (Submitted By) Sections Affected Substantial Change(s) V1.00 10 December 2010 All - Initial V2.00 07 Sep 2012 All - Added description and register bits for over-current masking feature All - Removed open-load detection feature V2.02 13.1 05 August 2013 Introduction The HSDRV module provides two high-side drivers typically used to drive LED or resistive loads 13.1.1 Features The HSDRV module includes two independent high-side drivers with common high voltage supply. Each driver has the following features: • Selectable gate control of high-side switches: HSDR[1:0] register bits or PWM or timer channels. • Over-current shutdown for the drivers, while they are enabled, comprising: – Interrupt flag generation – Driver shutdown – Optional masking window 13.1.2 Modes of Operation The HSDRV module behaves as follows in the system power modes: 1. MCU run mode The activation of the HSE0 or HSE1 bits enable the related high-side driver. The driver is controlled by the selected source. 2. MCU stop mode MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 385 High-Side Drivers - HSDRV (S12HSDRVV2) During stop mode operation the high-side drivers are shut down, i.e. the high-side drivers are disabled and their drivers are turned off. The bits in the data register which control the drivers (HSDRx) are cleared automatically. After returning from stop mode the drivers are re-enabled and the state of the HSE bits are automatically set. If the data register bits (HSDRx) were chosen as source in PIM module, then the respective high-side driver stays turned off until the software sets the associated bit in the data register (HSDRx). When the timer or PWM were chosen as source, the respective high-side driver is controlled by the timer or PWM without further handling. When it is required that the driver stays turned off after the stop mode for this case (PWM or timer), the software must take the appropriate action to turn off the driver before entering stop mode. 13.1.3 Block Diagram Figure 13-1 shows a block diagram of the HSDRV module. The module consists of a control and an output stage. Internal functions can be routed to control the high-side drivers. See PIM chapter for routing options. Figure 13-1. HSDRV Block Diagram HS0 HS0 control HS0 Over Current VSUPHS HS1 Over Current HS1 control HS1 MC9S12VR Family Reference Manual, Rev. 3.11 386 Freescale Semiconductor High-Side Drivers - HSDRV (S12HSDRVV2) 13.2 External Signal Description Table 13-2 shows the external pins associated with the HSDRV module. Table 13-2. HSDRV Signal Properties Name Function HS0 High-side driver output 0 disabled (off) HS1 High-side driver output 1 disabled (off) High Voltage Power Supply for both high side drivers disabled (off) VSUPHS 13.2.1 Reset State HS0, HS1— High Side Driver Pins Outputs of the two high-side drivers are intended to drive LEDs or resistive loads. 13.2.2 VSUPHS — High Side Driver Power Pin Power supply for both high-side drivers. This pin must be connected to the main power supply with the appropriate reverse battery protection network. 13.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the HSDRV module. 13.3.1 Module Memory Map A summary of registers associated with the HSDRV module is shown in Table 13-3. Detailed descriptions of the registers and bits are given in the following sections. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Table 13-3. Register Summary Address Offset Register Name Bit 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0x0000 HSDR R W 0 0 0x0001 HSCR R W 0 0 0x0002 Reserved R W 0 0 HSOCME1 HSOCME0 0 0 1 Bit 0 HSDR1 HSDR0 HSE1 HSE0 0 0 MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 387 High-Side Drivers - HSDRV (S12HSDRVV2) Table 13-3. Register Summary Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0003 Reserved R Reserved W 0x0004 Reserved R W 0 0 0 0 0 0 0 0 0x0005 Reserved R W 0 0 0 0 0 0 0 0 0 0 HSOCIF1 HSOCIF0 0x0006 HSIE R HSOCIE W 0 0 0 0 0 0x0007 HSIF R W 0 0 0 0 0 0 MC9S12VR Family Reference Manual, Rev. 3.11 388 Freescale Semiconductor High-Side Drivers - HSDRV (S12HSDRVV2) 13.3.2 Register Definition 13.3.3 Port HS Data Register (HSDR) Access: User read/write1 Module Base + 0x0000 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 HSDR1 HSDR0 W Altern. Read Function — — — — — — OC2 OC2 — — — — — — PWM2 PWM2 Reset 0 0 0 0 0 0 0 0 = Unimplemented Figure 13-2. Port HS Data Register (HSDR) 1 Read: Anytime The data source (HSDRx or alternate function) depends on the HSE control bit settings. Write: Anytime 2 See PIM chapter for detailed routing description. Table 13-4. PTHS Register Field Descriptions Field 1-0 HSDRx Description Port HS Data Bits—Data registers or routed timer outputs or routed PWM outputs These register bits can be used to control the high-side drivers if selected as control source. See PIM section for routing details. If the associated HSEx bit is set to 0, a read returns the value of the Port HS Data Register (HSDRx). If the associated HSEx bit is set to 1, a read returns the value of the selected control source for the driver. When entering in STOP mode the Port HS Data Register (HSDRx) is cleared. 0 High-side driver is turned off 1 High-side driver is turned on NOTE After enabling the high-side driver with the HSEx bit in HSCR register, the user must wait a minimum settling time tHS_settling before turning on the high-side driver. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 389 High-Side Drivers - HSDRV (S12HSDRVV2) 13.3.4 HSDRV Configuration Register (HSCR) Access: User read/write1 Module Base + 0x0001 R 7 6 0 0 5 4 HSOCME1 HSOCME0 0 0 3 2 0 0 1 0 HSE1 HSE0 0 0 W Reset 0 0 0 0 = Unimplemented Figure 13-3. HSDRV Configuration Register (HSCR) 1 Read: Anytime Write: Anytime, except HSOCME (see description) Table 13-5. HSCR Register Field Descriptions Field Description 5-4 HSDRV Over-Current Mask Enable HSOCME These bits enable the masking of the over-current shutdown for tHSOCM on the related high-side driver, after x switching the driver on. These bits are only writable when the related high-side driver is disabled (HSEx=0) 0 over-current masking window is disabled 1 over-current masking window is enabled 1-0 HSEx HSDRV Enable These bits control the bias of the related high-side driver circuit. 0 High-side driver is disabled 1 High-side driver is enabled NOTE After enabling the high-side driver (write 1 to HSEx) a settling time tHS_settling is required before the high-side driver is allowed to be turned on (e.g. by writing HSDRx bits). MC9S12VR Family Reference Manual, Rev. 3.11 390 Freescale Semiconductor High-Side Drivers - HSDRV (S12HSDRVV2) 13.3.5 Reserved Register Access: User read/write1 Module Base + 0x0003 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x R W Reset = Unimplemented Figure 13-4. Reserved Register 1 Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. Table 13-6. Reserved Register Field Descriptions Field Description 7-0 These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 391 High-Side Drivers - HSDRV (S12HSDRVV2) 13.3.6 HSDRV Interrupt Enable Register (HSIE) Access: User read/write1 Module Base + 0x0006 7 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSOCIE W Reset 0 = Unimplemented Figure 13-5. HSDRV Interrupt Enable Register (HSIE) 1 Read: Anytime Write: Anytime Table 13-7. HSIE Register Field Descriptions Field 7 HSOCIE Description HSDRV Over-Current Interrupt Enable 0 Interrupt request is disabled 1Interrupt is requested whenever a HSOCIFx flag is set MC9S12VR Family Reference Manual, Rev. 3.11 392 Freescale Semiconductor High-Side Drivers - HSDRV (S12HSDRVV2) 13.3.7 HSDRV Interrupt Flag Register (HSIF) Access: User read/write1 Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 HSOCIF1 HSOCIF0 0 0 W Reset 0 0 0 0 0 0 = Unimplemented Figure 13-6. HSDRV Interrupt Flag Register (HSIF) 1 Read: Anytime Write: Write 1 to clear, writing 0 has no effect Table 13-8. HSIF Register Field Descriptions Field 1-0 HSOCIFx Description HSDRV Over-Current Interrupt Flag These flags are set to 1 when an over-current event occurs on the related high-side driver (| IHS | > | IOCTHSX |). While set the related high-side driver is turned off. Once these flags are cleared, the related driver is controlled again by the source selected in PIM module. 0 No over-current event occurred since last clearing of flag 1 An over-current event occurred since last clearing of flag MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 393 High-Side Drivers - HSDRV (S12HSDRVV2) 13.4 Functional Description 13.4.1 General The HSDRV module provides two high-side drivers able to drive LED or resistive loads. The driver can be controlled directly through register bits or alternatively by dedicated timer or PWM channels. See PIM chapter for routing details. 13.4.2 Over-Current Shutdown Each high-side driver has an over-current shutdown feature with a current threshold of IOCTHSX. If an over-current is detected the related interrupt flag (HSOCIF1 or HSOCIF0) is set in the HSDRV Interrupt Flag Register (HSIF). As long as the over-current interrupt flag remains set, the related high-side driver is turned off to protect the circuit. Clearing the related over-current interrupt flag returns back the control to the selected source in the PIM module. The over-current detection and driver shutdown can be masked for an initial THSOCM after switching the driver on. This can be achieved by writing the related HSOCME register bit in the HSCR register to 1. The HSOCME bits are only writable while the related driver is disabled (HSE=0). 13.4.3 Interrupts This section describes the interrupt generated by HSDRV module. The interrupt is only available in MCU run mode. Entering and exiting MCU stop mode has no effect on the interrupt flags. The HSDRV interrupt vector is named in Table 13-9. Vector addresses and interrupt priorities are defined at MCU level. 13.4.3.1 HSDRV Over Current Interrupt (HSOCI) Table 13-9. HSDRV Interrupt Sources Module Interrupt Source Module Internal Interrupt Source Local Enable HSDRV Interrupt (HSI) HSDRV Over-Current Interrupt (HSOCI) HSOCIE = 1 If an over-current is detected the related interrupt flag HSOCIFx asserts. Depending on the setting of the HSDRV Error Interrupt Enable (HSOCIE) bit an interrupt is requested. MC9S12VR Family Reference Manual, Rev. 3.11 394 Freescale Semiconductor Chapter 14 Low-Side Drivers - LSDRV (S12LSDRV1) Table 14-1. Revision History Table Rev. No. Date (Item No.) (Submitted By) Sections Affected Substantial Change(s) V1.01 22 February 2011 All - Added clarification to open-load mechanism in over-current conditions V1.02 12 April 2011 All - improved clarification to open-load mechanism in over-current conditions - corrected typos V1.03 3 April 2011 V1.04 14.1 Register Descriptions for LSDR and LSCR 29 January 2013 All - added Note on considering settling time tLS_settling to LSDR and LSCR register description - added Note on how to disable the low-side driver to LSDR register description - Cleaning Introduction The LSDRV module provides two low-side drivers typically used to drive inductive loads (relays). 14.1.1 Features The LSDRV module includes two independent low side drivers with common current sink. Each driver has the following features: • Selectable driver control of low-side switches: LSDRx register bits, PWM or timer channels. See PIM chapter for routing options. • Open-load detection while enabled – While driver off: selectable high-load resistance open-load detection • Over-current protection with shutdown and interrupt while enabled • Active clamp to protect the device against over-voltage when the power transistor that is driving an inductive load (relay) is turned off. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 395 Low-Side Drivers - LSDRV (S12LSDRV1) 14.1.2 Modes of Operation The LSDRV module behaves as follows in the system operating modes: 1. MCU run mode The activation of the LSE0 or LSE1 bits enable the related low-side driver. The driver is controlled by the selected source in the Port Integration Module (see PIM chapter). 2. MCU stop mode During stop mode operation the low-side drivers are shut down, i.e. the low-side drivers are disabled and their drivers are turned off. The bits in the data register which control the drivers (LSDRx) are cleared automatically. After returning from stop mode the drivers are re-enabled. If the data register bits (LSDRx) were chosen as source in PIM module, then the respective low-side driver stays turned off until the software sets the associated bit in the data register (LSDRx). When the timer or PWM were chosen as source, the respective low-side driver is controlled by the timer or PWM without further handling. When it is required that the driver stays turned off after the stop mode for this case (PWM or timer), the software must take the appropriate action to turn off the driver before entering stop mode. 14.1.3 Block Diagram Figure 14-1 shows a block diagram of the LSDRV module. The module consists of a control and an output stage. Internal functions can be routed to control the low-side drivers. See PIM chapter for routing options. Figure 14-1. LSDRV Block Diagram LS0 control LS1 control Low Side Driver Control LS0 LSGND LS1 MC9S12VR Family Reference Manual, Rev. 3.11 396 Freescale Semiconductor Low-Side Drivers - LSDRV (S12LSDRV1) 14.2 External Signal Description Table 14-2 shows the external pins associated with the LSDRV module. Table 14-2. LSDRV Signal Properties Name Function LS0 Low-side driver output 0 disabled (off) LS1 Low-side driver output 1 disabled (off) LSGND 14.2.1 Reset State Low-side driver ground pin — LS0, LS1— Low Side Driver Pins Outputs of the two low-side drivers intended to drive inductive loads (relays). 14.2.2 LSGND — Low Side Driver Ground Pin Common current sink for both low-side driver pins. This pin should be connected on-board to the common ground. 14.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the LSDRV module. 14.3.1 Module Memory Map A summary of registers associated with the LSDRV module is shown in Table 14-3. Detailed descriptions of the registers and bits are given in the following sections. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Table 14-3. Register Summary Address Offset Register Name Bit 7 6 5 4 3 2 0 0 LSOLE1 Reserved 0x0000 LSDR R W 0 0 0 0 0x0001 LSCR R W 0 0 0 0 Reserved Reserved Reserved 0x0002 Reserved R Reserved W 1 Bit 0 LSDR1 LSDR0 LSOLE0 LSE1 LSE0 Reserved Reserved Reserved MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 397 Low-Side Drivers - LSDRV (S12LSDRV1) Table 14-3. Register Summary Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0003 Reserved R Reserved W 0x0004 Reserved R W 0 0 0 0 0 0 0 0 0x0005 LSSR R W 0 0 0 0 0 0 LSOL1 LSOL0 0x0006 LSIE R W 0 0 0 0 0 0 0 0x0007 LSIF R W 0 0 0 0 0 LSOCIF1 LSOCIF0 LSOCIE 0 MC9S12VR Family Reference Manual, Rev. 3.11 398 Freescale Semiconductor Low-Side Drivers - LSDRV (S12LSDRV1) 14.3.2 Register Definition 14.3.3 Port LS Data Register (LSDR) Access: User read/write1 Module Base + 0x0000 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 LSDR1 LSDR0 OC2 OC2 PWM2 PWM2 0 0 W Altern. Read Function 0 0 0 0 0 0 Reset 0 0 0 0 0 0 = Unimplemented Figure 14-2. Port LS Data Register (LSDR) 1 Read: Anytime. The data source (LSDRx or alternate function) depends on the LSE control bit settings. Write: Anytime 2 See PIM chapter for detailed routing description. Table 14-4. LSDR Register Field Descriptions Field 1-0 LSDRx Description Port LS Data Bits—Data registers or routed timer outputs or routed PWM outputs These register bits can be used to control the low-side drivers if selected as control source. See PIM section for routing details. If the associated LSEx bit is set to 0, a read returns the value of the Port LS Data Register (LSDRx). If the associated LSEx bit is set to 1, a read returns the value of the selected control source for the driver. When entering in STOP mode the Port LS Data Register (LSDR) is cleared. 0 Low-side driver is turned off 1 Low-side driver is turned on NOTE After enabling the low-side driver with the LSEx bit in LSCR register, the user must wait a minimum settling time tLS_settling before turning on the low-side driver. NOTE The low-side driver should be turned off (e.g. LDSRx=0 or OC=0 or PWM=0) and the load should be de-energized before going into Stop Mode or disabling the low-side driver with the LSEx bits. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 399 Low-Side Drivers - LSDRV (S12LSDRV1) 14.3.4 LSDRV Configuration Register (LSCR) Access: User read/write1 Module Base + 0x0001 R 7 6 5 4 0 0 0 0 3 2 1 0 LSOLE1 LSOLE0 LSE1 LSE0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented Figure 14-3. LSDRV Configuration Register (LSCR) 1 Read: Anytime Write: Anytime Table 14-5. LSCR Register Field Descriptions Field 3-2 LSOLEx Description LSDRV High-Load Resistance Open-Load Detection Enable These bits enable the measurement function to detect an open-load condition on the related low-side driver operating on high-load resistance loads. If the low-side driver is enabled and is not being driven by the selected source, then the high-load resistance detection circuit is activated when this bit is set to ‘1’. 0 high-load resistance open-load detection is disabled 1 high-load resistance open-load detection is enabled 1-0 LSEx LSDRV Enable These bits control the bias of the related low-side driver circuit. 0 Low-side driver is disabled. 1 Low-side driver is enabled. NOTE After enabling the low-side driver (write “1” to LSEx) a settling time tLS_settling is required before the low-side driver is allowed to be turned on (e.g. by writing LSDRx bits). MC9S12VR Family Reference Manual, Rev. 3.11 400 Freescale Semiconductor Low-Side Drivers - LSDRV (S12LSDRV1) 14.3.5 LSDRV Status Register (LSSR) Access: User read1 Module Base + 0x0005 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 LSOL1 LSOL0 0 0 0 0 0 0 0 0 W Reset = Unimplemented Figure 14-4. LSDRV Status Register (LSSR) 1 Read: Anytime Write: No Write Table 14-6. LSSR - Register Field Descriptions Field Description 1-0 LSOLx LSDRV Open-Load Status Bits These bits reflect the open-load condition status on each driver related pin. This open-load monitoring will only be active if the detection function is enabled (bits LSOLEx) and the corresponding low-side driver is enabled and turned off. A delay of tHLROLDT must be granted after enabling the high-load resistance open-load detection function in order to read valid data. 0 Open-load condition ILS < IHLROLDC 1 Open-load condition ILS ≥ IHLROLDC MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 401 Low-Side Drivers - LSDRV (S12LSDRV1) 14.3.6 LSDRV Interrupt Enable Register (LSIE) Access: User read/write1 Module Base + 0x0006 7 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSOCIE W Reset 0 = Unimplemented Figure 14-5. LSDRV Interrupt Enable Register (LSIE) 1 Read: Anytime Write: Anytime Table 14-7. LSIE Register Field Descriptions Field 7 LSOCIE Description LSDRV Error Interrupt Enable 0 Interrupt request is disabled 1 Interrupt will be requested whenever a LSOCIFx flag is set MC9S12VR Family Reference Manual, Rev. 3.11 402 Freescale Semiconductor Low-Side Drivers - LSDRV (S12LSDRV1) 14.3.7 LSDRV Interrupt Flag Register (LSIF) Access: User read/write1 Module Base + 0x0007 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 LSOCIF1 LSOCIF0 0 0 W Reset 0 0 0 0 0 0 = Unimplemented Figure 14-6. LSDRV Interrupt Flag Register (LSIF) 1 Read: Anytime Write: Write 1 to clear, writing 0 has no effect Table 14-8. LSIF Register Field Descriptions Field Description 1-0 LSOCIFx LSDRV Over-Current Interrupt Flag These flags are set to 1 when an over-current event occurs on the related low-side driver (ILS > ILIMLSX). While set the related low-side driver is turned off. Once these flags are cleared, the related driver is again driven by the source selected in PIM module. 0 No over-current event occurred since last clearing of flag 1 An over-current event occurred since last clearing of flag MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 403 Low-Side Drivers - LSDRV (S12LSDRV1) 14.4 14.4.1 Functional Description General The LSDRV module provides two low-side drivers able to drive inductive loads (relays). The driver can be controlled directly through register bits or alternatively by dedicated timer or PWM channels. See PIM section for routing details. Both drivers feature an open-load and over-current detection described in the following sub-sections. In addition to this an active clamp (for driving relays) is protecting each driver stage. The active clamp will turn on a low-side FET if the voltage on a pin exceeds VCLAMP when the driver is turned off. 14.4.2 Open-Load Detection A “High-load resistance Open Load Detection” can be enabled for each driver by setting the corresponding LSOLEx bit (refer to Section 14.3.4, “LSDRV Configuration Register (LSCR)”. This detection will only be executed when the driver is enabled and it is not being driven (LSDRx = 0). That is because the measurement point is between the load and the driver, and the current should not go through the driver. To detect an open-load condition the voltage will be observed at the output from the driver. Then if the driving pin LSx stays at low voltage which is approximately LSGND, there is no load for the corresponding low-side driver. An open-load condition is flagged with bits LSOL0 and LSOL1 in the LSDRV Status Register (LSSR). 14.4.3 Over-Current Detection Each low-side driver has an over-current detection while enabled with a current threshold of ILIMLSX. If over-current is detected the related interrupt flag (LSOCIF1 or LSOCIF0) is set in the LSDRV Interrupt Flag Register (LSIF). As long as the over-current interrupt flag remains set the related low-side driver is turned off to protect the circuit.Clearing the related over-current interrupt flag returns back the control of the driver to the selected source in the PIM module. NOTE The open-load detection is only active if the selected source (e.g. PWM, Timer, LSDRx) for the low-side driver is turned off. 14.4.4 Interrupts This section describes the interrupt generated by LSDRV module. The interrupt is only available in MCU run mode. Entering and exiting MCU stop mode has no effect on the interrupt flags. The LSDRV interrupt vector is named in Table 14-9. Vector addresses and interrupt priorities are defined at MCU level. MC9S12VR Family Reference Manual, Rev. 3.11 404 Freescale Semiconductor Low-Side Drivers - LSDRV (S12LSDRV1) Table 14-9. LSDRV Interrupt Sources Module Interrupt Source Module Internal Interrupt Source Local Enable LSDRV Interrupt (LSI) LSDRV Over-Current Interrupt (LSOCI) LSOCIE=1 14.4.4.1 LSDRV Over Current Interrupt (LSOCI) If a low-side driver over-current event is detected the related interrupt flag LSOCIFx asserts. Depending on the setting of the LSDRV Error Interrupt Enable (LSOCIE) bit an interrupt is requested. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 405 Low-Side Drivers - LSDRV (S12LSDRV1) MC9S12VR Family Reference Manual, Rev. 3.11 406 Freescale Semiconductor Chapter 15 LIN Physical Layer (S12LINPHYV2) Table 15-1. Revision History Table Rev. No. Date (Item No.) (Submitted By) V02.11 V02.12 V02.13 15.1 Sections Affected 19 Sep 2013 All 20 Sep 2013 Standby Mode 8 Oct 2013 All Substantial Change(s) - Removed preliminary note. - Fixed grammar and spelling throughout the document. - Clarified Standby mode behavior. - More grammar, spelling, and formating fixes throughout the document. Introduction The LIN (Local Interconnect Network) bus pin provides a physical layer for single-wire communication in automotive applications. The LIN Physical Layer is designed to meet the LIN Physical Layer 2.2 specification from LIN consortium. 15.1.1 Features The LIN Physical Layer module includes the following distinctive features: • Compliant with LIN Physical Layer 2.2 specification. • Compliant with the SAE J2602-2 LIN standard. • Standby mode with glitch-filtered wake-up. • Slew rate selection optimized for the baud rates: 10.4 kbit/s, 20 kbit/s and Fast Mode (up to 250 kbit/s). • Switchable 34 kΩ/330 kΩ pullup resistors (in shutdown mode, 330 kΩ only) • Current limitation for LIN Bus pin falling edge. • Overcurrent protection. • LIN TxD-dominant timeout feature monitoring the LPTxD signal. • Automatic transmitter shutdown in case of an overcurrent or TxD-dominant timeout. • Fulfills the OEM “Hardware Requirements for LIN (CAN and FlexRay) Interfaces in Automotive Applications” v1.3. The LIN transmitter is a low-side MOSFET with current limitation and overcurrent transmitter shutdown. A selectable internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. To be used as a master node, an external MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 407 LIN Physical Layer (S12LINPHYV2) resistor of 1 kΩ must be placed in parallel between VLINSUP and the LIN Bus pin, with a diode between VLINSUP and the resistor. The fall time from recessive to dominant and the rise time from dominant to recessive is selectable and controlled to guarantee communication quality and reduce EMC emissions. The symmetry between both slopes is guaranteed. 15.1.2 Modes of Operation The LIN Physical Layer can operate in the following four modes: 1. Shutdown Mode The LIN Physical Layer is fully disabled. No wake-up functionality is available. The internal pullup resistor is replaced by a high ohmic one (330 kΩ) to maintain the LIN Bus pin in the recessive state. All registers are accessible. 2. Normal Mode The full functionality is available. Both receiver and transmitter are enabled. 3. Receive Only Mode The transmitter is disabled and the receiver is running in full performance mode. 4. Standby Mode The transmitter of the LIN Physical Layer is disabled. If the wake-up feature is enabled, the internal pullup resistor can be selected (330 kΩ or 34 kΩ). The receiver enters a low power mode and optionally it can pass wake-up events to the Serial Communication Interface (SCI). If the wake-up feature is enabled and if the LIN Bus pin is driven with a dominant level longer than tWUFR followed by a rising edge, the LIN Physical Layer sends a wake-up pulse to the SCI, which requests a wake-up interrupt. (This feature is only available if the LIN Physical Layer is routed to the SCI). 15.1.3 Block Diagram Figure 15-1 shows the block diagram of the LIN Physical Layer. The module consists of a receiver with wake-up control, a transmitter with slope and timeout control, a current sensor with overcurrent protection as well as a registers control block. MC9S12VR Family Reference Manual, Rev. 3.11 408 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) + *,
 
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- , * .* * *   Figure 15-1. LIN Physical Layer Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 409 LIN Physical Layer (S12LINPHYV2) 15.2 External Signal Description This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals. 15.2.1 LIN — LIN Bus Pin This pad is connected to the single-wire LIN data bus. 15.2.2 LGND — LIN Ground Pin This pin is the device LIN ground connection. It is used to sink currents related to the LIN Bus pin. A de-coupling capacitor external to the device (typically 220 pF, X7R ceramic) between LIN and LGND can further improve the quality of this ground and filter noise. 15.2.3 VLINSUP — Positive Power Supply External power supply to the chip. The VLINSUP supply mapping is described in device level documentation. 15.2.4 LPTxD — LIN Transmit Pin This pin can be routed to the SCI, LPDR1 register bit, an external pin, or other options. Please refer to the PIM chapter of the device specification for the available routing options. This input is only used in normal mode; in other modes the value of this pin is ignored. 15.2.5 LPRxD — LIN Receive Pin This pin can be routed to the SCI, an external pin, or other options. Please refer to the PIM chapter of the device specification for the available routing options. In standby mode this output is disabled, and sends only a short pulse in case the wake-up functionality is enabled and a valid wake-up pulse was received in the LIN Bus. MC9S12VR Family Reference Manual, Rev. 3.11 410 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) 15.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the LIN Physical Layer. 15.3.1 Module Memory Map A summary of the registers associated with the LIN Physical Layer module is shown in Table 15-2. Detailed descriptions of the registers and bits are given in the subsections that follow. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0 0 LPE RXONLY LPWUE LPPUE Reserved Reserved LPSLR1 LPSLR0 0x0000 LPDR R W 0 0 0 0 0x0001 LPCR R W 0 0 0 0 Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0002 Reserved R Reserved W 0x0003 LPSLRM R LPDTDIS W 0x0004 Reserved R Reserved W 0x0005 LPSR R W 0x0006 LPIE R W LPDTIE LPOCIE 0x0007 LPIF R W LPDTIF LPOCIF LPDR1 LPDR0 Figure 15-2. Register Summary MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 411 LIN Physical Layer (S12LINPHYV2) 15.3.2 Register Descriptions This section describes all the LIN Physical Layer registers and their individual bits. 15.3.2.1 Port LP Data Register (LPDR) Access: User read/write1 Module Base + Address 0x0000 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 1 LPDR1 1 0 LPDR0 1 = Unimplemented Figure 15-3. Port LP Data Register (LPDR) 1 Read: Anytime Write: Anytime Table 15-2. LPDR Field Description Field Description 1 LPDR1 Port LP Data Bit 1 — The LIN Physical Layer LPTxD input (see Figure 15-1) can be directly controlled by this register bit. The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to the PIM chapter of the device Reference Manual for more info. 0 LPDR0 Port LP Data Bit 0 — Read-only bit. The LIN Physical Layer LPRxD output state can be read at any time. MC9S12VR Family Reference Manual, Rev. 3.11 412 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) 15.3.2.2 LIN Control Register (LPCR) Access: User read/write1 Module Base + Address 0x0001 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 LPE RXONLY LPWUE LPPUE 0 0 0 0 = Unimplemented Figure 15-4. LIN Control Register (LPCR) 1 Read: Anytime Write: Anytime, Table 15-3. LPCR Field Description Field Description 3 LPE LIN Enable Bit — If set, this bit enables the LIN Physical Layer. 0 The LIN Physical Layer is in shutdown mode. None of the LIN Physical Layer functions are available, except that the bus line is held in its recessive state by a high ohmic (330kΩ) resistor. All registers are normally accessible. 1 The LIN Physical Layer is not in shutdown mode. 2 RXONLY Receive Only Mode bit — This bit controls RXONLY mode. 0 The LIN Physical Layer is not in receive only mode. 1 The LIN Physical Layer is in receive only mode. 1 LPWUE LIN Wake-Up Enable — This bit controls the wake-up feature in standby mode. 0 In standby mode the wake-up feature is disabled. 1 In standby mode the wake-up feature is enabled. 0 LPPUE LIN Pullup Resistor Enable — Selects pullup resistor. 0 The pullup resistor is high ohmic (330 kΩ). 1 The 34 kΩ pullup is switched on (except if LPE=0 or when in standby mode with LPWUE=0). MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 413 LIN Physical Layer (S12LINPHYV2) 15.3.2.3 Reserved Register Access: User read/write1 Module Base + Address 0x0002 R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x = Unimplemented Figure 15-5. LIN Test register 1 Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. Table 15-4. Reserved Register Field Description Field 7-0 Reserved 15.3.2.4 Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. LIN Slew Rate Mode Register (LPSLRM) Access: User read/write1 Module Base + Address 0x0003 7 R W Reset LPDTDIS 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 LPSLR1 LPSLR0 0 0 = Unimplemented Figure 15-6. LIN Slew Rate Mode Register (LPSLRM) 1 Read: Anytime Write: Only in shutdown mode (LPE=0) MC9S12VR Family Reference Manual, Rev. 3.11 414 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) Table 15-5. LPSLRM Field Description Field Description 7 LPDTDIS TxD-dominant timeout disable Bit — This bit disables the TxD-dominant timeout feature. Disabling this feature is only recommended for using the LIN Physical Layer for other applications than LIN protocol. It is only writable in shutdown mode (LPE=0). 0 TxD-dominant timeout feature is enabled. 1 TxD-dominant timeout feature is disabled. 1-0 LPSLR[1:0] Slew-Rate Bits — Please see section 15.4.2 for details on how the slew rate control works. These bits are only writable in shutdown mode (LPE=0). 00 Normal Slew Rate (optimized for 20 kbit/s). 01 Slow Slew Rate (optimized for 10.4 kbit/s). 10 Fast Mode Slew Rate (up to 250 kbit/s). This mode is not compliant with the LIN Protocol (LIN electrical characteristics like duty cycles, reference levels, etc. are not fulfilled). It is only meant to be used for fast data transmission. Please refer to section 15.4.2.2 for more details on fast mode.Please note that an external pullup resistor stronger than 1 kΩ might be necessary for the range 100 kbit/s to 250 kbit/s. 11 Reserved . 15.3.2.5 Reserved Register Access: User read/write1 Module Base + Address 0x0004 R W Reset 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x = Unimplemented Figure 15-7. Reserved Register 1 Read: Anytime Write: Only in special mode NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. Table 15-6. Reserved Register Field Description Field 7-0 Reserved Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 415 LIN Physical Layer (S12LINPHYV2) 15.3.2.6 LIN Status Register (LPSR) Access: User read/write1 Module Base + Address 0x0005 R 7 6 5 4 3 2 1 0 LPDT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented Figure 15-8. LIN Status Register (LPSR) 1 Read: Anytime Write: Never, writes to this register have no effect Table 15-7. LPSR Field Description Field Description 7 LPDT LIN Transmitter TxD-dominant timeout Status Bit — This read-only bit signals that the LPTxD pin is still dominant after a TxD-dominant timeout. As long as the LPTxD is dominant after the timeout the LIN transmitter is shut down and the LPTDIF is set again after attempting to clear it. 0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout. 1 LPTxD is still dominant after a TxD-dominant timeout. MC9S12VR Family Reference Manual, Rev. 3.11 416 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) 15.3.2.7 LIN Interrupt Enable Register (LPIE) Access: User read/write1 Module Base + Address 0x0006 7 R W Reset 6 LPDTIE LPOCIE 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 15-9. LIN Interrupt Enable Register (LPIE) 1 Read: Anytime Write: Anytime Table 15-8. LPIE Field Description Field Description 7 LPDTIE LIN transmitter TxD-dominant timeout Interrupt Enable — 0 Interrupt request is disabled. 1 Interrupt is requested if LPDTIF bit is set. 6 LPOCIE LIN transmitter Overcurrent Interrupt Enable — 0 Interrupt request is disabled. 1 Interrupt is requested if LPOCIF bit is set. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 417 LIN Physical Layer (S12LINPHYV2) 15.3.2.8 LIN Interrupt Flags Register (LPIF) Access: User read/write1 Module Base + Address 0x0007 7 R W Reset 6 LPDTIF LPOCIF 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 15-10. LIN Interrupt Flags Register (LPIF) 1 Read: Anytime Write: Writing ‘1’ clears the flags, writing a ‘0’ has no effect Table 15-9. LPIF Field Description Field Description 7 LPDTIF LIN Transmitter TxD-dominant timeout Interrupt Flag — LPDTIF is set to 1 when LPTxD is still dominant (0) after tTDLIM of the falling edge of LPTxD. For protection, the transmitter is disabled. This flag can only be cleared by writing a 1. Writing a 0 has no effect. Please make sure that LPDTIF=1 before trying to clear it. Clearing LPDTIF is not allowed if LPDTIF=0 already. If the LPTxD is still dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see 15.4.4.2 TxD-dominant timeout Interrupt). If interrupt requests are enabled (LPDTIE= 1), LPDTIF causes an interrupt request. 0 No TxD-dominant timeout has occurred. 1 A TxD-dominant timeout has occurred. 6 LPOCIF LIN Transmitter Overcurrent Interrupt Flag — LPOCIF is set to 1 when an overcurrent event happens. For protection, the transmitter is disabled. This flag can only be cleared by writing a 1. Writing a 0 has no effect. Please make sure that LPOCIF=1 before trying to clear it. Clearing LPOCIF is not allowed if LPOCIF=0 already. If the overcurrent is still present or LPTxD is dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see15.4.4.1 Overcurrent Interrupt). If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request. 0 No overcurrent event has occurred. 1 Overcurrent event has occurred. MC9S12VR Family Reference Manual, Rev. 3.11 418 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) 15.4 Functional Description 15.4.1 General The LIN Physical Layer module implements the physical layer of the LIN interface. This physical layer can be driven by the SCI (Serial Communication Interface) module or directly through the LPDR register. 15.4.2 Slew Rate and LIN Mode Selection The slew rate can be selected for Electromagnetic Compatibility (EMC) optimized operation at 10.4 kbit/s and 20 kbit/s as well as at fast baud rate (up to 250 kbit/s) for test and programming. The slew rate can be chosen with the bits LPSLR[1:0] in the LIN Slew Rate Mode Register (LPSLRM). The default slew rate corresponds to 20 kbit/s. The LIN Physical Layer can also be configured to be used for non-LIN applications (for example, to transmit a PWM pulse) by disabling the TxD-dominant timeout (LPDTDIS=1). Changing the slew rate (LPSLRM Register) during transmission is not allowed in order to avoid unwanted effects. To change the register, the LIN Physical Layer must first be disabled (LPE=0). Once it is updated the LIN Physical Layer can be enabled again. NOTE For 20 kbit/s and Fast Mode communication speeds, the corresponding slew rate MUST be set; otherwise, the communication is not guaranteed (violation of the specified LIN duty cycles). For 10.4 kbit/s, the 20 kbit/s slew rate can be set but the EMC performance is worse. The up to 250 kbit/s slew rate must be chosen ONLY for fast mode, not for any of the 10.4 kbit/s or 20 kbit/s LIN compliant communication speeds. 15.4.2.1 10.4 kbit/s and 20 kbit/s When the slew rate is chosen for 10.4 kbit/s or 20 kbit/s communication, a control loop is activated within the module to make the rise and fall times of the LIN bus independent from VLINSUP and the load on the bus. 15.4.2.2 Fast Mode (not LIN compliant) Choosing this slew rate allows baud rates up to 250 kbit/s by having much steeper edges (please refer to electricals). As for the 10.4 kbit/s and 20 kbit/s modes, the slope control loop is also engaged. This mode is used for fast communication only, and the LIN electricals are not supported (for example, the LIN duty cycles). A stronger external pullup resistor might be necessary to sustain communication speeds up to 250 kbit/s. The LIN signal (and therefore the receive LPRxD signal) might not be symmetrical for high baud rates with high loads on the bus. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 419 LIN Physical Layer (S12LINPHYV2) Please note that if the bit time is smaller than the parameter tOCLIM (please refer to electricals), then no overcurrent is reported nor does an overcurrent shutdown occur. However, the current limitation is always engaged in case of a failure. 15.4.3 Modes Figure 15-11 shows the possible mode transitions depending on control bits, stop mode, and error conditions. 15.4.3.1 Shutdown Mode The LIN Physical Layer is fully disabled. No wake-up functionality is available. The internal pullup resistor is high ohmic only (330 kΩ) to maintain the LIN Bus pin in the recessive state. LPTxD is not monitored in this mode for a TxD-dominant timeout. All the registers are accessible. Setting LPE causes the module to leave the shutdown mode and to enter the normal mode or receive only mode (if RXONLY bit is set). Clearing LPE causes the module to leave the normal or receive only modes and go back to shutdown mode. 15.4.3.2 Normal Mode The full functionality is available. Both receiver and transmitter are enabled. The internal pullup resistor can be chosen to be high ohmic (330 kΩ) if LPPUE = 0, or LIN compliant (34 kΩ) if LPPUE = 1. If RXONLY is set, the module leaves normal mode to enter receive only mode. If the MCU enters stop mode, the LIN Physical Layer enters standby mode. 15.4.3.3 Receive Only Mode Entering this mode disables the transmitter and immediately stops any on-going transmission. LPTxD is not monitored in this mode for a TxD-dominant timeout. The receiver is running in full performance mode in all cases. To return to normal mode, the RXONLY bit must be cleared. If the device enters stop mode, the module leaves receive only mode to enter standby mode. 15.4.3.4 Standby Mode with Wake-Up Feature The transmitter of the LIN Physical Layer is disabled and the receiver enters a low power mode. NOTE Before entering standby mode, ensure no transmissions are ongoing. If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the wake-up feature is not needed. MC9S12VR Family Reference Manual, Rev. 3.11 420 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) If LPWUE is set the receiver is able to pass wake-up events to the SCI (Serial Communication Interface). If the LIN Physical Layer receives a dominant level longer than tWUFR followed by a rising edge, it sends a pulse to the SCI which can generate a wake-up interrupt. Once the device exits stop mode, the LIN Physical Layer returns to normal or receive only mode depending on the status of the RXONLY bit. NOTE Since the wake-up interrupt is requested by the SCI, the wake-up feature is not available if the SCI is not used. The internal pullup resistor is selectable only if LPWUE = 1 (wake-up enabled). If LPWUE = 0, the internal pullup resistor is not selectable and remains at 330 kΩ regardless of the state of the LPPUE bit. If LPWUE = 1, selecting the 330 kΩ pullup resistor (LPPUE = 0) reduces the current consumption in standby mode. NOTE When using the LIN wake-up feature in combination with other non-LIN device wake-up features (like a periodic time interrupt), some care must be taken. If the device leaves stop mode while the LIN bus is dominant, the LIN Physical Layer returns to normal or receive only mode and the LIN bus is re-routed to the RXD pin of the SCI and triggers the edge detection interrupt (if the interrupt’s priority of the hardware that awakes the MCU is less than the priority of the SCI interrupt, then the SCI interrupt will execute first). It is up to the software to decide what to do in this case because the LIN Physical Layer can not guarantee it was a valid wake-up pulse. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 421 LIN Physical Layer (S12LINPHYV2)
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 "!%%!  "!  "! #$"! Figure 15-11. LIN Physical Layer Mode Transitions MC9S12VR Family Reference Manual, Rev. 3.11 422 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) 15.4.4 Interrupts The interrupt vector requested by the LIN Physical Layer is listed in Table 15-10. Vector address and interrupt priority is defined at the MCU level. The module internal interrupt sources are combined into a single interrupt request at the device level. Table 15-10. Interrupt Vectors Module Interrupt Source LIN Interrupt (LPI) 15.4.4.1 Module Internal Interrupt Source Local Enable LIN Txd-Dominant Timeout Interrupt (LPDTIF) LPDTIE = 1 LIN Overcurrent Interrupt (LPOCIF) LPOCIE = 1 Overcurrent Interrupt The transmitter is protected against overcurrent. In case of an overcurrent condition occurring within a time frame called tOCLIM starting from LPTxD falling edge, the current through the transmitter is limited (the transmitter is not shut down). The masking of an overcurrent event within the time frame tOCLIM is meant to avoid “false” overcurrent conditions that can happen during the discharging of the LIN bus. If an overcurrent event occurs out of this time frame, the transmitter is disabled and the LPOCIF flag is set. In order to re-enable the transmitter again, the following prerequisites must be met: 1) Overcurrent condition is over 2) LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time. To re-enable the transmitter then, the LPOCIF flag must be cleared (by writing a 1). NOTE Please make sure that LPOCIF=1 before trying to clear it. It is not allowed to try to clear LPOCIF if LPOCIF=0 already. After clearing LPOCIF, if the overcurrent condition is still present or the LPTxD pin is dominant while being in normal mode, the transmitter remains disabled and the LPOCIF flag is set again after a time to indicate that the attempt to re-enable has failed. This time is equal to: • minimum 1 IRC period (1 us) + 2 bus periods • maximum 2 IRC periods (2 us) + 3 bus periods If the bit LPOCIE is set in the LPIE register, an interrupt is requested. Figure 15-12 shows the different scenarios for overcurrent interrupt handling. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 423 LIN Physical Layer (S12LINPHYV2)
 
     

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# "#    !"#   $  % Figure 15-12. Overcurrent interrupt handling 15.4.4.2 TxD-dominant timeout Interrupt To protect the LIN bus from a network lock-up, the LIN Physical Layer implements a TxD-dominant timeout mechanism. When the LPTxD signal has been dominant for more than tDTLIM the transmitter is disabled and the LPDT status flag and the LPDTIF interrupt flag are set. In order to re-enable the transmitter again, the following prerequisites must be met: 1) TxD-dominant condition is over (LPDT=0) 2) LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time To re-enable the transmitter then, the LPDTIF flag must be cleared (by writing a 1). NOTE Please make sure that LPDTIF=1 before trying to clear it. It is not allowed to try to clear LPDTIF if LPDTIF=0 already. MC9S12VR Family Reference Manual, Rev. 3.11 424 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) After clearing LPDTIF, if the TxD-dominant timeout condition is still present or the LPTxD pin is dominant while being in normal mode, the transmitter remains disabled and the LPDTIF flag is set after a time again to indicate that the attempt to re-enable has failed. This time is equal to: • minimum 1 IRC period (1 us) + 2 bus periods • maximum 2 IRC periods (2 us) + 3 bus periods If the bit LPDTIE is set in the LPIE register, an interrupt is requested. Figure 15-13 shows the different scenarios of TxD-dominant timeout interrupt handling.
  

 
     
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           ! "! Figure 15-13. TxD-dominant timeout interrupt handling MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 425 LIN Physical Layer (S12LINPHYV2) 15.5 15.5.1 Application Information Module Initialization The following steps should be used to configure the module before starting the transmission: 1. Set the slew rate in the LPSLRM register to the desired transmission baud rate. 2. When using the LIN Physical Layer for other purposes than LIN transmission, de-activate the dominant timeout feature in the LPSLRM register if needed. 3. In most cases, the internal pullup should be enabled in the LPCR register. 4. Route the desired source in the PIM module to the LIN Physical Layer. 5. Select the transmit mode (Receive only mode or Normal mode) in the LPCR register. 6. If the SCI is selected as source, activate the wake-up feature in the LPCR register if needed for the application (SCI active edge interrupt must also be enabled). 7. Enable the LIN Physical Layer in the LPCR register. 8. Wait for a minimum of a transmit bit. 9. Begin transmission if needed. NOTE It is not allowed to try to clear LPOCIF or LPDTIF if they are already cleared. Before trying to clear an error flag, always make sure that it is already set. 15.5.2 Interrupt handling in Interrupt Service Routine (ISR) Both interrupts (TxD-dominant timeout and overcurrent) represent a failure in transmission. To avoid more disturbances on the transmission line, the transmitter is de-activated in both cases. The interrupt subroutine must take care of clearing the error condition and starting the routine that re-enables the transmission. For that purpose, the following steps are recommended: 1. First, the cause of the interrupt must be cleared: — The overcurrent will be gone after the transmitter has been disabled. — The TxD-dominant timeout condition will be gone once the selected source for LPTxD has turned recessive. 2. Clear the corresponding enable bit (LPDTIE or LPOCIE) to avoid entering the ISR again until the flags are cleared. 3. Notify the application of the error condition (LIN Error handler) and leave the ISR. In the LIN Error handler, the following sequence is recommended: 1. Disable the LIN Physical Layer (LPCR) while re-configuring the transmission. — If the receiver must remain enabled, set the LIN Physical Layer into receive only mode instead. 2. Do all required configurations (SCI, etc.) to re-enable the transmission. 3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter). MC9S12VR Family Reference Manual, Rev. 3.11 426 Freescale Semiconductor LIN Physical Layer (S12LINPHYV2) 4. 5. 6. 7. Clear the error flag. Enable the interrupts again (LPDTIE and LPOCIE). Enable the LIN Physical Layer or leave the receive only mode (LPCR register). Wait for a minimum of a transmit bit before beginning transmission again. If there is a problem re-enabling the transmitter, then the error flag will be set again during step 3 and the ISR will be called again. MC9S12VR Family Reference Manual Rev. 3.11 Freescale Semiconductor 427 LIN Physical Layer (S12LINPHYV2) MC9S12VR Family Reference Manual, Rev. 3.11 428 Freescale Semiconductor Chapter 16 Supply Voltage Sensor - (BATSV2) Table 16-1. Revision History Table Rev. No. (Item No.) Data Sections Affected Substantial Change(s) V01.00 15 Dec 2010 all Initial Version V02.00 16 Mar 2011 16.3.2.1 16.4.2.1 - added BVLS[1] to support four voltage level - moved BVHS to register bit 6 16.1 Introduction The BATS module provides the functionality to measure the voltage of the battery supply pin VSENSE or of the chip supply pin VSUP. 16.1.1 Features Either One of the voltage present on the VSENSE or VSUP pin can be routed via an internal divider to the internal Analog to Digital Converter. Independent of the routing to the Analog to Digital Converter, it is possible to route one of these voltages to a comparator to generate a low or a high voltage interrupt to alert the MCU. 16.1.2 Modes of Operation The BATS module behaves as follows in the system power modes: 1. Run mode The activation of the VSENSE Level Sense Enable (BSESE=1) or ADC connection Enable (BSEAE=1) closes the path from the VSENSE pin through the resistor chain to ground and enables the associated features if selected. The activation of the VSUP Level Sense Enable (BSUSE=1) or ADC connection Enable (BSUAE=1) closes the path from VSUP pin through the resistor chain to ground and enables the associated features if selected. BSESE takes precedence over BSUSE. BSEAE takes precedence over BSUAE. 2. Stop mode During stop mode operation the path from the VSENSE pin through the resistor chain to ground is opened and the low voltage sense features are disabled. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 429 Supply Voltage Sensor - (BATSV2) During stop mode operation the path from the VSUP pin through the resistor chain to ground is opened and the low voltage sense features are disabled. The content of the configuration register is unchanged. 16.1.3 Block Diagram Figure 16-1 shows a block diagram of the BATS module. See device guide for connectivity to ADC channel. Figure 16-1. BATS Block Diagram VSUP ... ... VSENSE BVLC BVLS[1:0] BVHS BVHC Comparator BSUSE BSESE 1 2 BSEAE BSUAE 1 automatically closed if BSESE and/or BSEAE is active, open during Stop mode 2 automatically closed if BSUSE and/or BSUAE is active, open during Stop mode 16.2 to ADC External Signal Description This section lists the name and description of all external ports. 16.2.1 VSENSE — Supply (Battery) Voltage Sense Pin This pin can be connected to the supply (Battery) line for voltage measurements. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a MC9S12VR Family Reference Manual, Rev. 3.11 430 Freescale Semiconductor Supply Voltage Sensor - (BATSV2) comparator via an analog multiplexer. The pin itself is protected against reverse battery connections. To protect the pin from external fast transients an external resistor (RVSENSE_R) is needed for protection. 16.2.2 VSUP — Voltage Supply Pin This pin is the chip supply. It can be internally connected for voltage measurement. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a comparator via an analog multiplexer. 16.3 Memory Map and Register Definition This section provides the detailed information of all registers for the BATS module. 16.3.1 Register Summary Figure 16-2 shows the summary of all implemented registers inside the BATS module. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 431 Supply Voltage Sensor - (BATSV2) NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Register Name 0x0000 BATE Bit 7 R 6 5 4 3 2 1 Bit 0 BSUAE BSUSE BSEAE BSESE BVHC BVLC BVHIE BVLIE BVHIF BVLIF 0 BVHS BVLS[1:0] W 0x0001 BATSR R 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0002 BATIE R W 0x0003 BATIF R 0 0 0 0 0 0 W 0x0004 - 0x0005 Reserved 0x0006 - 0x0007 Reserved R 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R W = Unimplemented Figure 16-2. BATS Register Summary 16.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12VR Family Reference Manual, Rev. 3.11 432 Freescale Semiconductor Supply Voltage Sensor - (BATSV2) 16.3.2.1 BATS Module Enable Register (BATE) Access: User read/write1 Module Base + 0x0000 7 R 6 5 4 3 2 1 0 BSUAE BSUSE BSEAE BSESE 0 0 0 1 0 BVHS BVLS[1:0] W Reset 0 0 0 0 = Unimplemented Figure 16-3. BATS Module Enable Register (BATE) 1 Read: Anytime Write: Anytime Table 16-2. BATE Field Description Field 6 BVHS Description BATS Voltage High Select — This bit selects the trigger level for the Voltage Level High Condition (BVHC). 0 Voltage level VHBI1 is selected 1 Voltage level VHBI2 is selected 5:4 BATS Voltage Low Select — This bit selects the trigger level for the Voltage Level Low Condition (BVLC). BVLS[1:0] 00 Voltage level VLBI1 is selected 01 Voltage level VLBI2 is selected 10 Voltage level VLBI3 is selected 11 Voltage level VLBI4 is selected 3 BSUAE BATS VSUP ADC Connection Enable — This bit connects the VSUP pin through the resistor chain to ground and connects the ADC channel to the divided down voltage. This bit can be set only if the BSEAE bit is cleared. 0 ADC Channel is disconnected 1 ADC Channel is connected 2 BSUSE BATS VSUP Level Sense Enable — This bit connects the VSUP pin through the resistor chain to ground and enables the Voltage Level Sense features measuring BVLC and BVHC. This bit can be set only if the BSESE bit is cleared. 0 Level Sense features disabled 1 Level Sense features enabled 1 BSEAE BATS VSENSE ADC Connection Enable — This bit connects the VSENSE pin through the resistor chain to ground and connects the ADC channel to divided down voltage. Setting this bit will clear bit BSUAE . 0 ADC Channel is disconnected 1 ADC Channel is connected 0 BSESE BATS VSENSE Level Sense Enable — This bit connects the VSENSE pin through the resistor chain to ground and enables the Voltage Level Sense features measuring BVLC and BVHC.Setting this bit will clear bit BSUSE 0 Level Sense features disabled 1 Level Sense features enabled NOTE MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 433 Supply Voltage Sensor - (BATSV2) When opening the resistors path to ground by changing BSESE, BSEAE or BSUSE, BSUAE then for a time TEN_UNC + two bus cycles the measured value is invalid. This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts. MC9S12VR Family Reference Manual, Rev. 3.11 434 Freescale Semiconductor Supply Voltage Sensor - (BATSV2) 16.3.2.2 BATS Module Status Register (BATSR) Access: User read only1 Module Base + 0x0001 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BVHC BVLC 0 0 0 0 0 0 0 0 W Reset = Unimplemented Figure 16-4. BATS Module Status Register (BATSR) 1 Read: Anytime Write: Never Table 16-3. BATSR - Register Field Descriptions Field Description 1 BVHC BATS Voltage Sense High Condition Bit — This status bit indicates that a high voltage at VSENSE or VSUP, depending on selection, is present. 0 Vmeasured < VHBI_A (rising edge) or Vmeasured < VHBI_D (falling edge) 1 Vmeasured ≥ VHBI_A (rising edge) or Vmeasured ≥ VHBI_D (falling edge) 0 BVLC BATS Voltage Sense Low Condition Bit — This status bit indicates that a low voltage at VSENSE or VSUP, depending on selection, is present. 0 Vmeasured ≥ VLBI_A (falling edge) or Vmeasured ≥ VLBI_D (rising edge) 1 Vmeasured < VLBI_A (falling edge) or Vmeasured < VLBI_D (rising edge) Figure 16-5. BATS Voltage Sensing V VHBI_A VHBI_D VLBI_D VLBI_A t MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 435 Supply Voltage Sensor - (BATSV2) 16.3.2.3 BATS Interrupt Enable Register (BATIE) Access: User read/write1 Module Base + 0x0002 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 BVHIE BVLIE 0 0 W Reset 0 0 0 0 0 0 = Unimplemented Figure 16-6. BATS Interrupt Enable Register (BATIE) 1 Read: Anytime Write: Anytime Table 16-4. BATIE Register Field Descriptions Field 1 BVHIE Description BATS Interrupt Enable High — Enables High Voltage Interrupt . 0 No interrupt will be requested whenever BVHIF flag is set . 1 Interrupt will be requested whenever BVHIF flag is set 0 BVLIE BATS Interrupt Enable Low — Enables Low Voltage Interrupt . 0 No interrupt will be requested whenever BVLIF flag is set . 1 Interrupt will be requested whenever BVLIF flag is set . 16.3.2.4 BATS Interrupt Flag Register (BATIF) Access: User read/write1 Module Base + 0x0003 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 BVHIF BVLIF 0 0 W Reset 0 0 0 0 0 0 = Unimplemented Figure 16-7. BATS Interrupt Flag Register (BATIF) 1 Read: Anytime Write: Anytime, write 1 to clear MC9S12VR Family Reference Manual, Rev. 3.11 436 Freescale Semiconductor Supply Voltage Sensor - (BATSV2) Table 16-5. BATIF Register Field Descriptions Field Description 1 BVHIF BATS Interrupt Flag High Detect — The flag is set to 1 when BVHC status bit changes. 0 No change of the BVHC status bit since the last clearing of the flag. 1 BVHC status bit has changed since the last clearing of the flag. 0 BVLIF BATS Interrupt Flag Low Detect — The flag is set to 1 when BVLC status bit changes. 0 No change of the BVLC status bit since the last clearing of the flag. 1 BVLC status bit has changed since the last clearing of the flag. 16.3.2.5 Reserved Register Access: User read/write1 Module Base + 0x0006 Module Base + 0x0007 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x x x R W Reset Figure 16-8. Reserved Register 1 Read: Anytime Write: Only in special mode NOTE These reserved registers are designed for factory test purposes only and are not intended for general user access. Writing to these registers when in special mode can alter the module’s functionality. 16.4 16.4.1 Functional Description General The BATS module allows measuring voltages on the VSENSE and VSUP pins. The VSENSE pin is implemented to allow measurement of the supply Line (Battery) Voltage VBAT directly. By bypassing the device supply capacitor and the external reversed battery protection diode this pin allows to detect under/over voltage conditions without delay. A series resistor (RVSENSE_R) is required to protect the VSENSE pin from fast transients. The voltage at the VSENSE or VSUP pin can be routed via an internal voltage divider to an internal Analog to Digital Converter Channel. Also the BATS module can be configured to generate a low and high voltage interrupt based on VSENSE or VSUP. The trigger level of the high and low interrupt are selectable. In a typical application, the module could be used as follows: The voltage at VSENSE is observed via usage of the interrupt feature (BSESE=1, BVHIE=1), while the VSUP pin voltage is routed to the ADC to allow regular measurement (BSUAE=1). MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 437 Supply Voltage Sensor - (BATSV2) 16.4.2 Interrupts This section describes the interrupt generated by the BATS module. The interrupt is only available in CPU run mode. Entering and exiting CPU stop mode has no effect on the interrupt flags. To make sure the interrupt generation works properly the bus clock frequency must be higher than the Voltage Warning Low Pass Filter frequency (fVWLP_filter). The comparator outputs BVLC and BVHC are forced to zero if the comparator is disabled (configuration bits BSESE and BSUSE are cleared). If the software disables the comparator during a high or low Voltage condition (BVHC or BVLC active), then an additional interrupt is generated. To avoid this behavior the software must disable the interrupt generation before disabling the comparator. The BATS interrupt vector is named in Table 16-6. Vector addresses and interrupt priorities are defined at MCU level. The module internal interrupt sources are combined into one module interrupt signal. Table 16-6. BATS Interrupt Sources Module Interrupt Source BATS Interrupt (BATI) 16.4.2.1 Module Internal Interrupt Source Local Enable BATS Voltage Low Condition Interrupt (BVLI) BVLIE = 1 BATS Voltage High Condition Interrupt (BVHI) BVHIE = 1 BATS Voltage Low Condition Interrupt (BVLI) To use the Voltage Low Interrupt the Level Sensing must be enabled (BSESE =1 or BSUSE =1). If measured when a) VLBI1 selected with BVLS[1:0] = 0x0 at selected pin Vmeasure < VLBI1_A (falling edge) or Vmeasure < VLBI1_D (rising edge) or when b) VLBI2 selected with BVLS[1:0] = 0x1 at selected pin Vmeasure < VLBI2_A (falling edge) or Vmeasure < VLBI2_D (rising edge) or when c) VLBI3 selected with BVLS[1:0] = 0x2 at selected pin Vmeasure < VLBI3_A (falling edge) or Vmeasure < VLBI3_D (rising edge) or when d) VLBI4 selected with BVLS[1:0] = 0x3 at selected pin Vmeasure < VLBI4_A (falling edge) or Vmeasure < VLBI4_D (rising edge) then BVLC is set. BVLC status bit indicates that a low voltage at the selected pin is present. The Low Voltage Interrupt flag (BVLIF) is set to 1 when the Voltage Low Condition (BVLC) changes state . The MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 438 Supply Voltage Sensor - (BATSV2) Interrupt flag BVLIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVLIE the module requests an interrupt to MCU (BATI). 16.4.2.2 BATS Voltage High Condition Interrupt (BVHI) To use the Voltage High Interrupt the Level Sensing must be enabled (BSESE =1 or BSUSE). If measured when a) VHBI1 selected with BVHS = 0 at selected pin Vmeasure ≥ VHBI1_A (rising edge) or Vmeasure ≥ VHBI1_D (falling edge) or when a) VHBI2 selected with BVHS = 1 at selected pin Vmeasure ≥ VHBI2_A (rising edge) or Vmeasure ≥ VHBI2_D (falling edge) then BVHC is set. BVHC status bit indicates that a high voltage at the selected pin is present. The High Voltage Interrupt flag (BVHIF) is set to 1 when a Voltage High Condition (BVHC) changes state. The Interrupt flag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI). MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 439 Supply Voltage Sensor - (BATSV2) MC9S12VR Family Reference Manual, Rev. 3.11 440 Freescale Semiconductor Chapter 17 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-1. Revision History Revision Number Revision Date Sections Affected V01.00 17 Jun 2010 17.4.6.1/17-34 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] 17.4.6.2/17-35 of the register FSTAT. 17.4.6.3/17-35 17.4.6.14/17-45 V01.01 31 aug 2010 17.4.6.2/17-35 Updated description of the commands RD1BLK, MLOADU and MLOADF 17.4.6.12/17-42 17.4.6.13/17-44 V01.02 31 Jan 2011 17.3.2.9/17-18 V01.03 04 Oct 2013 17.3.2.9/17-18 Updated notes regarding restrictions to change Protection in Special Single 17.3.2.10/17-22 Chip Mode (SS) Description of Changes Updated description of protection on Section 17.3.2.9 P-Flash Protection Register (FPROT) MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 1 17.1 Introduction The FTMRG64K512 module implements the following: • 64Kbytes of P-Flash (Program Flash) memory • 64bytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 17.4.5 Allowed Simultaneous P-Flash and EEPROM Operations. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected. 17.1.1 Glossary Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 2 64 KByte Flash Module (S12FTMRG64K512V1) NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 17.1.2 17.1.2.1 • • • • • • • • • • • EEPROM Features 512 bytes of EEPROM memory composed of one 512 byte Flash block divided into 128 sectors of 4 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four words in a burst sequence 17.1.2.3 • • • P-Flash Features 64 Kbytes of P-Flash memory composed of one 64 Kbyte Flash block divided into 128 sectors of 512 bytes Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 17.1.2.2 • Features Other Flash Module Features No external high-voltage power supply required for Flash memory program and erase operations Interrupt generation on Flash command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 3 64 KByte Flash Module (S12FTMRG64K512V1) 17.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 17-1. Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 16Kx39 sector 0 sector 1 Protection sector 127 Security Bus Clock CPU Clock Divider FCLK Memory Controller EEPROM 256x22 sector 0 sector 1 sector 127 Figure 17-1. FTMRG64K512 Block Diagram 17.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12VR Family Reference Manual, Rev. 3.11 4 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) 17.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 17.6 Initialization for a complete description of the reset sequence). . Table 17-2. FTMRG Memory Map Global Address (in Bytes) 0x0_0000 - 0x0_03FF 1 Size (Bytes) 1,024 0x0_0400 – 0x0_05FF 512 0x0_4000 – 0x0_7FFF 16,284 Description Register Space EEPROM Memory NVMRES1=1 : NVM Resource area (see Figure 17-2) See NVMRES description in Section 17.4.3 Internal NVM resource (NVMRES) 17.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x3_0000 and 0x3_FFFF as shown in Table 17-3.The P-Flash memory map is shown in Figure . The FPROT register, described in Section 17.3.2.9 P-Flash Protection Register (FPROT), can be set to Table 17-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x3_0000 – 0x3_FFFF 64 K Description P-Flash Block Contains Flash Configuration Field (see Table 17-4) protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protectio. Two separate memory regions, MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 5 64 KByte Flash Module (S12FTMRG64K512V1) one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protectionThe Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 17-4. Table 17-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 17.4.6.11, “Verify Backdoor Access Key Command,” and Section 17.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 17.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 17.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 17.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 17.3.2.2, “Flash Security Register (FSEC)” Description 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12VR Family Reference Manual, Rev. 3.11 6 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) P-Flash START = 0x3_0000 Flash Protected/Unprotected Region 32 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes Protection Fixed End 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 7 64 KByte Flash Module (S12FTMRG64K512V1) P-Flash Memory Map Table 17-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID1 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 17.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 17.4.2 IFR Version ID Word Table 17-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 17-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 17.4.3 Internal NVM resource (NVMRES) for NVMRES (NVM Resource) detail. MC9S12VR Family Reference Manual, Rev. 3.11 8 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) 0x0_4000 P-Flash IFR 1 Kbyte (NVMRES=1) 0x0_4400 Reserved 5k bytes RAM Start = 0x0_5800 RAM End = 0x0_59FF Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 17-2. Memory Controller Resource Memory Map (NVMRES=1) 17.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 17.3 Memory Map and Registers). A summary of the Flash module registers is given in Figure 17-3 with detailed descriptions in the following subsections. Address & Name 7 R 6 5 4 3 2 1 0 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 FDIVLD FCLKDIV W R FSEC W R FCCOBIX W Figure 17-3. FTMRG64K512 Register Summary MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 9 64 KByte Flash Module (S12FTMRG64K512V1) Address & Name R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD DFDIE SFDIE MGSTAT1 MGSTAT0 DFDIF SFDIF FRSV0 W R FCNFG CCIE IGNSF W R 0 0 0 0 0 0 FERCNFG W R FSTAT 0 CCIF ACCERR FPVIOL 0 0 MGBUSY RSVD 0 0 W R 0 0 FERSTAT W R FPROT RNV6 FPOPEN FPHDIS FPHS1 0 0 FPHS0 FPLDIS FPLS1 FPLS0 DPS3 DPS2 DPS1 DPS0 W R EEPROT 0 DPOPEN W R FCCOBHI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W R FCCOBLO W R FRSV1 W R FRSV2 W R FRSV3 W R FRSV4 W R FOPT W Figure 17-3. FTMRG64K512 Register Summary (continued) MC9S12VR Family Reference Manual, Rev. 3.11 10 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Address & Name R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRSV5 W R FRSV6 W R FRSV7 W = Unimplemented or Reserved Figure 17-3. FTMRG64K512 Register Summary (continued) 17.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIVLCK FDIV[5:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 17-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 17-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 11 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-7. FCLKDIV Field Descriptions (continued) Field Description 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 17-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 17.4.4, “Flash Command Operations,” for more information. Table 17-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) MIN 1 1 2 17.3.2.2 FDIV[5:0] 2 MAX BUSCLK Frequency (MHz) MIN 1 MAX FDIV[5:0] 2 1.0 1.6 0x00 16.6 17.6 0x10 1.6 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12VR Family Reference Manual, Rev. 3.11 12 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 17-5. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 17-4) as indicated by reset condition F in Figure 17-5. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 17-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 17-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 17-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 17-10. Flash KEYEN States KEYEN[1:0] 1 Status of Backdoor Key Access 00 DISABLED 01 DISABLED1 10 ENABLED 11 DISABLED Preferred KEYEN state to disable backdoor key access. Table 17-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 17.5 Security. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 13 64 KByte Flash Module (S12FTMRG64K512V1) 17.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX[2:0] W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-6. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 17-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 17.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 17.3.2.4 Flash Reserved0 Register (FRSV0) This Flash register is reserved for factory testing. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-7. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 17.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-8. Flash Configuration Register (FCNFG) MC9S12VR Family Reference Manual, Rev. 3.11 14 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. Table 17-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 17.3.2.7 Flash Status Register (FSTAT)) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 17.3.2.8 Flash Error Status Register (FERSTAT)). 0 All single bit faults detected during array reads are reported 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see Section 17.3.2.7 Flash Status Register (FSTAT)) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see Section 17.3.2.6 Flash Error Configuration Register (FERCNFG)) 0 FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 17.3.2.7 Flash Status Register (FSTAT)) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 17.3.2.6 Flash Error Configuration Register (FERCNFG)) 17.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DFDIE SFDIE 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-9. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 15 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 17.3.2.8 Flash Error Status Register (FERSTAT)) 0 SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 17.3.2.8 Flash Error Status Register (FERSTAT)) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 17.3.2.8 Flash Error Status Register (FERSTAT)) 17.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. 7 R 6 5 4 ACCERR FPVIOL 0 0 0 CCIF 3 2 MGBUSY RSVD 0 0 1 0 MGSTAT[1:0] W Reset 1 0 01 01 = Unimplemented or Reserved Figure 17-10. Flash Status Register (FSTAT) 1 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 17.6 Initialization). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. Table 17-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation. 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 17.4.4.2 Command Write Sequence) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR. 0 No access error detected 1 Access error detected MC9S12VR Family Reference Manual, Rev. 3.11 16 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-15. FSTAT Field Descriptions (continued) Field Description 4 FPVIOL Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected 1 Protection violation detected 3 MGBUSY 2 RSVD Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0. 1–0 Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 17.4.6, “Flash Command Description,” and Section 17.6, “Initialization” for details. 17.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DFDIF SFDIF 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-11. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. Table 17-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running 0 SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF. 0 No single bit fault detected 1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted while command running MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 17 64 KByte Flash Module (S12FTMRG64K512V1) 1 The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data attempted while command running) is indicated when both SFDIF and DFDIF flags are high. 2 There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. 17.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 17-12. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the FPROT register are writable in Normal Single Chip Mode with the restriction that the size of the protected region can only be increased (see Section 17.3.2.9.1, “P-Flash Protection Restrictions,” and Table 17-21).All (unreserved) bits of the FPROT register are writable without restriction in Special Single Chip Mode . During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 17-4) as indicated by reset condition ‘F’ in Figure 17-12. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 17-17. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 17-18 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits 6 RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. MC9S12VR Family Reference Manual, Rev. 3.11 18 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-17. FPROT Field Descriptions (continued) Field Description 5 FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 17-19. The FPHS bits can only be written to while the FPHDIS bit is set. 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 17-20. The FPLS bits can only be written to while the FPLDIS bit is set. Table 17-18. P-Flash Protection Function 1 Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges For range sizes, refer to Table 17-19 and Table 17-20. Table 17-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 17-20. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x3_8000–0x3_83FF 1 Kbyte 01 0x3_8000–0x3_87FF 2 Kbytes 10 0x3_8000–0x3_8FFF 4 Kbytes 11 0x3_8000–0x3_9FFF 8 Kbytes MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 19 64 KByte Flash Module (S12FTMRG64K512V1) All possible P-Flash protection scenarios are shown in Figure 17-13 . Although the protection scheme is loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in Normal Single Chip Mode while providing as much protection as possible if reprogramming is not required. MC9S12VR Family Reference Manual, Rev. 3.11 20 Freescale Semiconductor FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 Scenario 0x3_8000 0x3_FFFF Scenario FPHS[1:0] FPLS[1:0] FLASH START FPOPEN = 1 64 KByte Flash Module (S12FTMRG64K512V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 17-13. P-Flash Protection Scenarios MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 21 64 KByte Flash Module (S12FTMRG64K512V1) 17.3.2.9.1 P-Flash Protection Restrictions In Normal Single Chip Mode the general guideline is that P-Flash protection can only be added and not removed. Table 17-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 17-21. P-Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X X 1 X 4 X X X X X X X X X X 6 X 7 1 X 6 7 X 3 5 5 X X 2 4 X X X X X X Allowed transitions marked with X, see Figure 17-13 for a definition of the scenarios. 17.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. 7 R 6 5 4 0 0 0 3 2 DPOPEN 1 0 F1 F1 DPS[3:0] W Reset F1 0 0 0 F1 F1 = Unimplemented or Reserved Figure 17-14. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence. The (unreserved) bits of the EEPROT register are writable in Normal Single Chip Mode with the restriction that protection can be added but not removed. Writes in Normal Single Chip Mode must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant.All DPOPEN/DPS bit registers are writable without restriction in Special Single Chip Mode. During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 17-4) as indicated by reset condition F in . To change the EEPROM protection MC9S12VR Family Reference Manual, Rev. 3.11 22 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. Table 17-22. EEPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 3–0 DPS[3:0] EEPROM Protection Size — The DPS[3:0] bits determine the size of the protected area in the EEPROM memory as shown inTable 17-23 . Table 17-23. EEPROM Protection Address Range DPS[3:0] Global Address Range Protected Size 0000 0x0_0400 – 0x0_041F 32 bytes 0001 0x0_0400 – 0x0_043F 64 bytes 0010 0x0_0400 – 0x0_045F 96 bytes 0011 0x0_0400 – 0x0_047F 128 bytes 0100 0x0_0400 – 0x0_049F 160 bytes 0101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . . 1111 0x0_0400 – 0x0_05FF 512 bytes 17.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 23 64 KByte Flash Module (S12FTMRG64K512V1) 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 17-15. Flash Common Command Object High Register (FCCOBHI) 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 17-16. Flash Common Command Object Low Register (FCCOBLO) 17.3.2.11.1 FCCOB - NVM Command Mode NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 17-24. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX = 111) are ignored with reads from these fields returning 0x0000. Table 17-24 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 17.4.6 Flash Command Description. Table 17-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI FCMD[7:0] defining Flash command LO 6’h0, Global address [17:16] HI Global address [15:8] LO Global address [7:0] HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] 000 001 010 011 MC9S12VR Family Reference Manual, Rev. 3.11 24 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 100 101 17.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-17. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. 17.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-18. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 17.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 25 64 KByte Flash Module (S12FTMRG64K512V1) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-19. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 17.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-20. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. 17.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 17-21. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 17-4) as indicated by reset condition F in Figure 17-21. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12VR Family Reference Manual, Rev. 3.11 26 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 17.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-22. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 17.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-23. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 17.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-24. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 27 64 KByte Flash Module (S12FTMRG64K512V1) 17.4 Functional Description 17.4.1 Modes of Operation The FTMRG64K512 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, FPROT and EEPROT registers (see Table 17-27). 17.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 17-26. Table 17-26. IFR Version ID Fields • [15:4] [3:0] Reserved VERNUM VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’. 17.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 17-5. The NVMRES global address map is shown in Table 17-6. 17.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents. The next sections describe: • How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations • The command write sequence used to set Flash command parameters and launch execution • Valid Flash commands available for execution, according to MCU functional mode and MCU security state. MC9S12VR Family Reference Manual, Rev. 3.11 28 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) 17.4.4.1 Writing the FCLKDIV Register Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 17-8 shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set. 17.4.4.2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 17.3.2.7 Flash Status Register (FSTAT)) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. 17.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 17.3.2.3 Flash CCOB Index Register (FCCOBIX)). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 17-25. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 29 64 KByte Flash Module (S12FTMRG64K512V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load. Write to FCCOB register to load required command parameter. More Parameters? yes no Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 17-25. Generic Flash Command Write Sequence Flowchart MC9S12VR Family Reference Manual, Rev. 3.11 30 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) 17.4.4.3 Valid Flash Module Commands Table 17-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 17-27. Flash Commands by Mode and Security State Unsecured FCMD Command Secured NS1 SS2 NS3 SS4 0x01 Erase Verify All Blocks ∗ ∗ ∗ ∗ 0x02 Erase Verify Block ∗ ∗ ∗ ∗ 0x03 Erase Verify P-Flash Section ∗ ∗ ∗ 0x04 Read Once ∗ ∗ ∗ 0x06 Program P-Flash ∗ ∗ ∗ 0x07 Program Once ∗ ∗ ∗ 0x08 Erase All Blocks 0x09 Erase Flash Block ∗ ∗ ∗ 0x0A Erase P-Flash Sector ∗ ∗ ∗ 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key ∗ 0x0D Set User Margin Level ∗ 0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section ∗ ∗ ∗ 0x11 Program EEPROM ∗ ∗ ∗ 0x12 Erase EEPROM Sector ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 1 Unsecured Normal Single Chip mode Unsecured Special Single Chip mode. 3 Secured Normal Single Chip mode. 4 Secured Special Single Chip mode. 2 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 31 64 KByte Flash Module (S12FTMRG64K512V1) 17.4.4.4 P-Flash Commands Table 17-28 summarizes the valid P-Flash commands along with the effects of the commands on the P-Flash block and other resources within the Flash module. Table 17-28. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 17.4.4.5 Function on P-Flash Memory Verify that all P-Flash (and EEPROM) blocks are erased. Verify that a P-Flash block is erased. Verify that a given number of words starting at the address provided are erased. Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. Program a phrase in a P-Flash block. Erase all bytes in a P-Flash sector. Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. EEPROM Commands Table 17-29 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 17-29. EEPROM Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block Function on EEPROM Memory Verify that all EEPROM (and P-Flash) blocks are erased. Verify that the EEPROM block is erased. MC9S12VR Family Reference Manual, Rev. 3.11 32 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block. An erase of the full EEPROM block is only possible when DPOPEN bit in the EEPROT register is set prior to launching the command. 0x0B Unsecure Flash 0x0D Set User Margin Level Specifies a user margin read level for the EEPROM block. 0x0E Set Field Margin Level Specifies a field margin read level for the EEPROM block (special modes only). 0x10 Erase Verify EEPROM Section Verify that a given number of words starting at the address provided are erased. 0x11 Program EEPROM Program up to four words in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block. 17.4.5 Supports a method of releasing MCU security by erasing all EEPROM (and P-Flash) blocks and verifying that all EEPROM (and P-Flash) blocks are erased. Allowed Simultaneous P-Flash and EEPROM Operations Only the operations marked ‘OK’ in Table 17-30 are permitted to be run simultaneously on the Program Flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting Program Flash reads while program and erase operations execute on the EEPROM, providing read (P-Flash) while write (EEPROM) functionality. Table 17-30. Allowed P-Flash and EEPROM Simultaneous Operations EEPROM Program Flash Read Read Margin Read1 Program Sector Erase OK OK OK Mass Erase2 Margin Read1 Program Sector Erase Mass Erase2 1 OK A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 17.4.6.12 Set User Margin Level Command and Section 17.4.6.13 Set Field Margin Level Command. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 33 64 KByte Flash Module (S12FTMRG64K512V1) 2 17.4.6 The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ Flash Command Description This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the Memory Controller: • Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register • Writing an invalid command as part of the command write sequence • For additional possible errors, refer to the error handling table provided for each command If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data if both flags SFDIF and DFDIF are set. If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags will be set. If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write sequence (see Section 17.3.2.7 Flash Status Register (FSTAT)). CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 17.4.6.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. Table 17-31. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed. If all blocks are not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12VR Family Reference Manual, Rev. 3.11 34 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-32. Erase Verify All Blocks Command Error Handling Register Error Bit Error Condition ACCERR Set if CCOBIX[2:0] != 000 at command launch FPVIOL FSTAT 17.4.6.2 None MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0]bits determine which block must be verified. Table 17-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 17-34 See Table 17-34. Flash block selection code description Selection code[1:0] Flash block to be verified 00 EEPROM 01 Invalid (ACCERR) 10 Invalid (ACCERR) 11 P-Flash Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. Table 17-35. Erase Verify Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if an invalid FlashBlockSelectionCode[1:0] is supplied FSTAT FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 35 64 KByte Flash Module (S12FTMRG64K512V1) 17.4.6.3 Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. Table 17-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 17-37. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid global address [17:0] is supplied see ) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT Set if the requested section crosses a the P-Flash address boundary FPVIOL 17.4.6.4 None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 17.4.6.6 Program Once Command. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 17-38. Read Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value MC9S12VR Family Reference Manual, Rev. 3.11 36 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-38. Read Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 17-39. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if command not available in current mode (see Table 17-27) Set if an invalid phrase index is supplied FSTAT FPVIOL 17.4.6.5 None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read Program P-Flash Command The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an embedded algorithm. CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 17-40. Program P-Flash Command FCCOB Requirements CCOBIX[2:0] 000 1 FCCOB Parameters 0x06 Global address [17:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed1 010 Word 0 program value 011 Word 1 program value 100 Word 2 program value 101 Word 3 program value Global address [2:0] must be 000 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 37 64 KByte Flash Module (S12FTMRG64K512V1) Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. Table 17-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid global address [17:0] is supplied see ) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 17.4.6.6 Set if the global address [17:0] points to a protected area MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Program Once Command The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the Read Once command as described in Section 17.4.6.4 Read Once Command. The Program Once command must only be issued once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 17-42. Program Once Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x07 Not Required 001 Program Once phrase index (0x0000 - 0x0007) 010 Program Once word 0 value 011 Program Once word 1 value 100 Program Once word 2 value 101 Program Once word 3 value Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed. The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12VR Family Reference Manual, Rev. 3.11 38 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-43. Program Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 FSTAT FPVIOL 1 None MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will be allowed to execute again on that same phrase. 17.4.6.7 Erase All Blocks Command The Erase All Blocks operation will erase the entire P-Flash and EEPROM memory space. Table 17-44. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. Table 17-45. Erase All Blocks Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if command not available in current mode (see Table 17-27) FSTAT 17.4.6.8 FPVIOL Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 39 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 17-47. Erase Flash Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if the supplied P-Flash address is not phrase-aligned or if the EEPROM address is not word-aligned FSTAT FPVIOL 17.4.6.9 Set if an invalid global address [17:16] is supplied Set if an area of the selected Flash block is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 17-48. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0A Global address [17:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 17.1.2.1 P-Flash Features for the P-Flash sector size. Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12VR Family Reference Manual, Rev. 3.11 40 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-49. Erase P-Flash Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid global address [17:16] is supplied see ) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 17.4.6.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and EEPROM memory space and, if the erase is successful, will release security. Table 17-50. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and EEPROM memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released. If the erase verify is not successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 17-51. Unsecure Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if command not available in current mode (see Table 17-27) FSTAT FPVIOL Set if any area of the P-Flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 17.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 17-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 41 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 17-52. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is set after the Verify Backdoor Access Key operation has completed. Table 17-53. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if an incorrect backdoor key is supplied ACCERR FSTAT Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 17.3.2.2 Flash Security Register (FSEC)) Set if the backdoor key has mismatched since the last reset FPVIOL None MGSTAT1 None MGSTAT0 None 17.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 17-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters 0x0D Flash block selection code [1:0]. Table 17-34 See Margin level setting. MC9S12VR Family Reference Manual, Rev. 3.11 42 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 17-55. Table 17-55. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 17-56. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 17-34) FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 17.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 43 64 KByte Flash Module (S12FTMRG64K512V1) Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 17-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 17-34 See Margin level setting. field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash field margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply field margin levels to the P-Flash block only. Valid margin level settings for the Set Field Margin Level command are defined in Table 17-58. Table 17-58. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level1 0x0002 User Margin-0 Level2 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1 2 Read margin to the erased state Read margin to the programmed state Table 17-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 17-34) FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12VR Family Reference Manual, Rev. 3.11 44 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 17.4.6.14 Erase Verify EEPROM Section Command The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased. The Erase Verify EEPROM Section command defines the starting point of the data to be verified and the number of words. Table 17-60. Erase Verify EEPROM Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x10 Global address [17:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Number of words to be verified Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will verify the selected section of EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. Table 17-61. Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 010 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested section breaches the end of the EEPROM block FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 45 64 KByte Flash Module (S12FTMRG64K512V1) 17.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 17-62. Program EEPROM Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters Global address [17:16] to identify the EEPROM block 0x11 001 Global address [15:0] of word to be programmed 010 Word 0 program value 011 Word 1 program value, if desired 100 Word 2 program value, if desired 101 Word 3 program value, if desired Upon clearing CCIF to launch the Program EEPROM command, the user-supplied words will be transferred to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. Table 17-63. Program EEPROM Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] > 101 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid global address [17:0] is supplied Set if a misaligned word address is supplied (global address [0] != 0) FSTAT Set if the requested group of words breaches the end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation 17.4.6.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. MC9S12VR Family Reference Manual, Rev. 3.11 46 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) Table 17-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 001 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 17.1.2.2 EEPROM Features for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase EEPROM Sector operation has completed. Table 17-65. Erase EEPROM Sector Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 17-27) ACCERR Set if an invalid global address [17:0] is suppliedsee ) Set if a misaligned word address is supplied (global address [0] != 0) FSTAT FPVIOL 17.4.7 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 17-66. Flash Interrupt Sources Interrupt Source Global (CCR) Mask Interrupt Flag Local Enable CCIF (FSTAT register) CCIE (FCNFG register) I Bit ECC Double Bit Fault on Flash Read DFDIF (FERSTAT register) DFDIE (FERCNFG register) I Bit ECC Single Bit Fault on Flash Read SFDIF (FERSTAT register) SFDIE (FERCNFG register) I Bit Flash Command Complete MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 47 64 KByte Flash Module (S12FTMRG64K512V1) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 17.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed description of the register bits involved, refer to Section 17.3.2.5, “Flash Configuration Register (FCNFG)”, Section 17.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 17.3.2.7, “Flash Status Register (FSTAT)”, and Section 17.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 17-26. Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 17-26. Flash Module Interrupts Implementation 17.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 17.4.7, “Interrupts”). 17.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 17.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 17-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F. MC9S12VR Family Reference Manual, Rev. 3.11 48 Freescale Semiconductor 64 KByte Flash Module (S12FTMRG64K512V1) The security state out of reset can be permanently changed by programming the security byte assuming that the MCU is starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset. The following subsections describe these security-related subjects: • Unsecuring the MCU using Backdoor Key Access • Unsecuring the MCU in Special Single Chip Mode using BDM • Mode and Security Effects on Flash Command Availability 17.5.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 17.3.2.2 Flash Security Register (FSEC)), the Verify Backdoor Access Key command (see Section 17.4.6.11 Verify Backdoor Access Key Command) allows the user to present four prospective keys for comparison to the keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 17-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 17.3.2.2 Flash Security Register (FSEC)), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 17.4.6.11 Verify Backdoor Access Key Command 2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte (0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key command sequence. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 49 64 KByte Flash Module (S12FTMRG64K512V1) 17.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if the P-Flash and EEPROM memories are erased 3. Send BDM commands to disable protection in the P-Flash and EEPROM memory 4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below are skeeped. 5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into special single chip mode 6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that the P-Flash and EEPROM memory are erased If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM commands will now be enabled and the Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state 8. Reset the MCU 17.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 17-27. 17.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the initialization sequence is marked by setting CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12VR Family Reference Manual, Rev. 3.11 50 Freescale Semiconductor Appendix A MCU Electrical Specifications A.1 General This supplement contains the most accurate electrical information for the MC9S12VR-Family available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE This classification is shown in the column labeled “C” in the parameter tables where appropriate. P: C: T: D: Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 493 MCU Electrical Specifications Table A-1. Power Supplies Mnemonic Nominal Voltage VSS 0V VDDX1 1 5.0 V VSSX12 0V VDDX2 5.0 V VSSX2 0V VDDA 3 5.0 V Description Ground pin for 1.8V core supply voltage generated by on chip voltage regulator 5V power supply output for I/O drivers generated by on chip voltage regulator Ground pin for I/O drivers 5V power supply output for I/O drivers generated by on chip voltage regulator Ground pin for I/O drivers External power supply for the analog-to-digital converter and for the reference circuit of the internal voltage regulator VSSA 0V Ground pin for VDDA analog supply LGND 0V Ground pin for LIN physical LSGND 0V Ground pin for low-side driver VSUP 12V/18V External power supply for voltage regulator VSUPHS 12V/18V External power supply for high-side driver 1 All VDDX pins are internally connected by metal All VSSX pins are internally connected by metal 3 VDDA, VDDX and VSSA, VSSX are connected by diodes for ESD protection 2 A.1.2 Pins There are four groups of functional pins. A.1.2.1 I/O Pins The I/O pins have a level in the range of 3.13V to 5.5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins. Some functionality may be disabled. A.1.2.2 High Voltage Pins LS[1:0], HS[1:0], PL[3:0], VSENSE have a nominal 12V level. A.1.2.3 Oscillator The pins EXTAL, XTAL dedicated to the oscillator have a nominal 1.8V level. A.1.2.4 TEST This pin is used for production testing only. The TEST pin must be tied to ground in all applications. MC9S12VR Family Reference Manual, Rev. 3.11 494 Freescale Semiconductor MCU Electrical Specifications A.1.3 Current Injection Power supply must maintain regulation within operating VDDX or VDD range during instantaneous and operating maximum current conditions. Figure A-1. shows a 5V GPIO pad driver and the on chip voltage regulator with VDDX output. It shows also the power & gound pins VSUP, VDDX, VSSX and VSSA. Px represents any 5V GPIO pin. Assume Px is configured as an input. The pad driver transistors P1 and N1 are switched off (high impedance). If the voltage Vin on Px is greated than VDDX a positive injection current Iin will flow through diode D1 into VDDX node. If this injection current Iin is greater than ILoad, the internal power supply VDDX may go out of regulation. Ensure external VDDX load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Figure A-1. Current Injection on GPIO Port if Vin > VDDX VSUP Voltage Regulator VBG + _ ISUP Pad Driver P2 IDDX VDDX ILoad C Load Iin P1 D1 Iin Px N1 Vin > VDDX VSSX VSSA A.1.4 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 495 MCU Electrical Specifications maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level. Table A-2. Absolute Maximum Ratings1 Num Rating Symbol Min Max Unit VSUP -0.3 42 V 1 Voltage regulator supply voltage 2 LINPHY supply voltage VLINSUP -32 42 V 3 High side driver supply voltage VSUPHS -0.3 42 V 4 Battery sensor input voltage VSENSE pin VVSENSE_M -27 42 V ∆VDDX –0.3 0.3 V VDDA2 5 Voltage difference VDDX to 6 Voltage difference VSSX to VSSA ∆VSSX –0.3 0.3 V 7 Digital I/O input voltage sources VIN –0.3 6.0 V 8 HVI PL[3:0] input voltage (with external resistor REXT_HVI = 10kΩ) VLx -27 42 V 9 High-side driver HS[1:0] VPHS0/1 0 VSUPHS + 0.3 V 10 Low-side driver LS[1:0] VPLS0/1 0 40 V 11 EXTAL, XTAL3 VILV –0.3 2.16 V 12 Instantaneous maximum current Single pin limit for all digital I/O pins4 I –25 +25 mA 13 Instantaneous maximum current on PP2 / EVDD IEVDD -80 +25 mA 14 Instantaneous maximum current Single pin limit for EXTAL, XTAL IDL –25 +25 mA 15 Storage temperature range Tstg –65 155 °C D 1 Beyond absolute maximum ratings device might be damaged. VDDX and VDDA must be shorted 3 EXTAL and XTAL are shared with PE0 and PE1 5V GPIO’s 4 All digital I/O pins are internally clamped to V SSX and VDDX, or VSSA and VDDA. 2 MC9S12VR Family Reference Manual, Rev. 3.11 496 Freescale Semiconductor MCU Electrical Specifications A.1.5 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charged-Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-3. ESD and Latch-up Test Conditions Model Spec Human Body ChargedDevice Description JESD22-A114 JESD22-C101 Symbol Value Unit Series Resistance R 1500 Ω Storage Capacitance C 100 pF Number of Pulse per pin positive negative 1 1 Series Resistance R 0 Ω Storage Capacitance C 4 pF Latch-up for 5V GPIO’s Minimum Input Voltage Limit -2.5 V Maximum Input Voltage Limit +7.5 V Latch-up for LS/HS/HVI/V SENSE/LIN Minimum Input Voltage Limit -7 V Maximum Input Voltage Limit +21 V Table A-4. ESD Protection and Latch-up Characteristics Num C 1 C 2 Rating Symbol Min Max Unit HBM: LIN to LGND +/- 6 - kV C HBM: VSENSE, HVI[3:0] to GND +/- 4 kV 3 C HBM: HS1, HS2 to GND +/- 4 kV 4 C HBM: LS0, LS1 to GND +/- 2 kV 5 C HBM: Pin to Pin (all Pins LS0, LS1 excluded) +/- 2 kV 6 C HBM: Pin to Pin (all Pins LS0, LS1 included) +/- 1.5 kV 7 C CDM : Corner Pins VCDM +/-750 8 C CDM: All other Pins VCDM +/-500 9 C Direct Contact Discharge IEC61000-4-2 with and with out 220pF capacitor (R=330, C=150pF): LIN vs LGND VESDIEC +/-6 VHBM - V V - kV MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 497 MCU Electrical Specifications Table A-4. ESD Protection and Latch-up Characteristics 10 11 C C Latch-up Current of 5V GPIO’s at T=125°C positive negative ILAT Latch-up Current for LS[1:0], HS[1:0], VSENSE, LIN & HVI[3:0] at T=125°C positive negative ILAT +100 -100 +100 -100 - mA - mA MC9S12VR Family Reference Manual, Rev. 3.11 498 Freescale Semiconductor MCU Electrical Specifications A.1.6 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.7, “Power Dissipation and Thermal Characteristics”. Table A-5. Operating Conditions Num Rating Symbol Min Typ Max Unit 1 V 1 Voltage regulator and LINPHY supply voltage VSUP/ VLINUP 3.5 12 40 2 High side driver supply voltage VSUPHS 7 12 401 V 3 Voltage difference VDDX to VDDA ∆VDDX -0.1 — 0.1 V 4 Voltage difference VSSX to VSSA ∆VSSX -0.1 — 0.1 V 5 Oscillator fosc 4 — 20 MHz 6 Bus frequency fbus see Footnote2 — 25 MHz TJ TA –40 –40 — — 150 125 °C 7 Operating junction temperature range Operating ambient temperature range3 1 Normal operating range is 6V - 18V. Continous operation at 40V is not allowed. Only Transient Conditions (Load Dump) single pulse tmax input voltage > VIL max RPUL 3.8 5 10.5 κΩ 15 P Internal pull up current VIH min > input voltage > VIL max IPUL -10 — -130 µA 16 P Internal pull down current VIH min > input voltage > VIL max IPDH 10 — 130 µA 17 D Input capacitance Cin — 7 — pF IICS IICP –2.5 –25 18 — — OL OL 2 T Injection current Single pin limit Total device Limit, sum of all injected currents — — mA 2.5 25 MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 503 MCU Electrical Specifications 1 Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12 C° in the temperature range from 50°C to 125°C. 2 Refer to Section A.1.3, “Current Injection” for more details A.1.9 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.9.1 Measurement Conditions Current is measured on VSUP & VSUPHS pins. VDDX is connected to VDDA. It does not include the current to drive external loads. Unless otherwise noted the currents are measured in special single chip mode and the CPU code is executed from RAM. For Run and Wait current measurements PLL is on and the reference clock is the IRC1M trimmed to 1MHz. The bus frequency is 25MHz and the CPU frequency is 50MHz. Table A-9, Table A-10 and Table A-11 show the configuration of the CPMU module and the peripherals for Run, Wait and Stop current measurement. Table A-9. CPMU Configuration for Pseudo Stop Current Measurement CPMU REGISTER Bit settings/Conditions CPMUCLKS PLLSEL=0, PSTP=1, CSAD=0 PRE=PCE=RTIOSCSEL=COPOSCSEL=1 CPMUOSC OSCE=1, External Square wave on EXTAL fEXTAL=4MHz, VIH= 1.8V, VIL=0V CPMURTI RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111; CPMUCOP WCOP=1, CR[2:0]=111 Table A-10. CPMU Configuration for Run/Wait and Full Stop Current Measurement CPMU REGISTER CPMUSYNR CPMUPOSTDIV Bit settings/Conditions VCOFRQ[1:0]=01,SYNDIV[5:0] = 24 POSTDIV[4:0]=0 CPMUCLKS PLLSEL=1 CPMUOSC OSCE=0, Reference clock for PLL is fref=firc1m trimmed to 1MHz API settings for STOP current measurement MC9S12VR Family Reference Manual, Rev. 3.11 504 Freescale Semiconductor MCU Electrical Specifications Table A-10. CPMU Configuration for Run/Wait and Full Stop Current Measurement CPMU REGISTER Bit settings/Conditions CPMUAPICTL APIEA=0, APIFE=1, APIE=0 CPMUAPITR trimmed to >=10Khz CPMUAPIRH/RL set to $FFFF Table A-11. Peripheral Configurations for Run & Wait Current Measurement Peripheral Configuration SCI continuously transmit data (0x55) at speed of 19200 baud SPI configured to master mode, continuously transmit data (0x55) at 1Mbit/s PWM configured to toggle its pins at the rate of 40kHz ADC the peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on all input channels in sequence. DBG the module is enabled and the comparators are configured to trigger in outside range.The range covers all the code executed by the core. TIM the peripheral is configured to output compare mode, pulse accumulator and modulus counter enabled. COP & RTI enabled HSDRV 1 & 2 module is enabled but output driver disabled LSDRV 1 & 2 module is enabled but output driver disabled BATS enabled connected to SCI and continuously transmit data (0x55) at speed of 19200 baud LINPHY Table A-12. Run and Wait Current Characteristics Conditions are: VSUP=VSUPHS=18V, TA=105°C, see Table A-10 and Table A-9 Num C Rating 1 P Run Current 2 P Wait Current Symbol Min Typ Max Unit ISUPR 15 22 mA ISUPW 10 15 mA MC9S12VR Family Reference Manual, Rev. 3.11 Freescale Semiconductor 505 MCU Electrical Specifications Table A-13. Stop Current Characteristics Conditions are: VSUP=VSUPHS=12V API see CPMU Configuration for Pseudo Stop Current MeasurementTable A-9. Num C Rating Symbol Min Typ Max Unit ISUPS 29 60 µA Stop Current all modules off 1 P TA = TJ = -40°C 1 1 2 P TA = TJ = 150°C ISUPS 140 600 µA 3 C TA = TJ = 25°C1 ISUPS 33 65 µA 4 C TA = TJ = 105°C1 ISUPS 55 90 µA Stop Current API enabled & LINPHY in standby (see 15.4.3.4 Standby Mode with wake-up feature) 5 1 C TA = TJ = 25°C1 ISUPS 50 80 µA If MCU is in STOP long enough then TA = TJ . Die self heating due to stop current can be ignored. Table A-14. Pseudo Stop Current Characteristics Conditions are: VSUP=VSUPHS=12V, API see CPMU Configuration for Pseudo Stop Current MeasurementTable A-9., COP & RTI enabled Num C 1 C Rating TA= 25°C Symbol Min ISUPPS Typ Max Unit 358 480 µA MC9S12VR Family Reference Manual, Rev. 3.11 506 Freescale Semiconductor Appendix B VREG Electrical Specifications Table B-1. Voltage Regulator Electrical Characteristics -40oC