SPC5125YVN400R

Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5125 Rev. 4 , 09/2011 MPC5125 MPC5125 Microcontroller Data Sheet The MPC5125 integrates a high performance e300 CPU core based on the Power Architecture® Technology with a rich set of peripheral functions focused on communications and systems integration. Major features of the MPC5125 are as follows: • • • • • • • • • • • • • • • • • • • e300 Power Architecture processor core (enhanced version of the MPC603e core), operates as fast as 400 MHz Low power design Display interface unit (DIU) DDR1, DDR2, low-power mobile DDR (LPDDR), and 1.8 V/3.3 V SDR DRAM memory controllers 32 KB on-chip SRAM USB 2.0 OTG controller with ULPI interface DMA subsystem Flexible multi-function external memory bus (EMB) interface NAND flash controller (NFC) LocalPlus interface (LPC) 10/100Base Ethernet MMC/SD/SDIO card host controller (SDHC) Programmable serial controller (PSC) Inter-integrated circuit (I2C) communication interfaces Controller area network (CAN) J1850 byte data link controller (BDLC) interface On-chip real-time clock (RTC) On-chip temperature sensor IC Identification module (IIM) © Freescale Semiconductor, Inc., 2008–2011. All rights reserved. 324 TEPBGA 23 mm x 23 mm Table of Contents 1 2 3 4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 MPC5125 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 324-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .5 3.2 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .6 3.2.1 Power and Ground Supply Summary . . . . . . . .35 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . .36 4.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .36 4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . .36 4.1.2 Recommended Operating Conditions . . . . . . . .36 4.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . .37 4.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . .40 4.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .41 4.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . .42 4.2 Oscillator and PLL Electrical Characteristics . . . . . . . .43 4.2.1 System Oscillator Electrical Characteristics . . .44 4.2.2 RTC Oscillator Electrical Characteristics . . . . . .44 4.2.3 System PLL Electrical Characteristics. . . . . . . .45 4.2.4 e300 Core PLL Electrical Characteristics . . . . .45 4.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .46 4.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .46 4.3.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.3.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .50 4.3.5 SDRAM (DDR) . . . . . . . . . . . . . . . . . . . . . . . . .50 4.3.6 LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 5 6 7 8 4.3.7 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.10 MMC/SD/SDIO Card Host Controller (SDHC) . 4.3.11 DIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.12 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.13 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.14 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.15 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.16 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 4.3.17 Fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.18 IEEE 1149.1 (JTAG) . . . . . . . . . . . . . . . . . . . . . System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . 5.2 System and CPU Core AVDD Power Supply Filtering . 5.3 Connection Recommendations . . . . . . . . . . . . . . . . . . 5.4 Pullup/Pulldown Resistor Requirements . . . . . . . . . . . 5.4.1 Pulldown Resistor Requirements for TEST Pin 5.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 JTAG_TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 e300 COP / BDM Interface . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 63 66 67 68 71 71 72 72 79 79 80 82 82 82 82 83 83 83 83 83 87 87 88 91 91 MPC5125 Microcontroller Data Sheet, Rev. 4 2 Freescale Semiconductor Ordering Information 1 Ordering Information M PC 5125 Y VN 400 R Qualification status Core code Device number Temperature range Package identifier Operating frequency (MHz) Tape and reel status Temperature Range Y = –40 °C to 125 °C, junction Package Identifier VN = 324 TEPBGA Pb-free Operating Frequency 400 = 400 MHz Note: Not all options are available on all devices. Refer to Table 1. Tape and Reel Status R = Tape and reel (blank) = Trays Qualification Status P = Pre qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Figure 1. MPC5125 Orderable Part Number Description Table 1 shows the orderable part numbers for the MPC5125. Table 1. MPC5125 Orderable Part Numbers Freescale Part Number1 MPC5125YVN400 Speed (MHz) Package Description MPC5125 324TEPBGA package Lead-free (PbFree) Operating Temperature2 Max3 (fMAX) Min (TL) Max (TH) 400 MHz core 200 MHz bus –40 °C 125 °C NOTES: 1 All packaged devices are PPC5125, rather than MPC125, until product qualifications are complete. 2 The lowest ambient operating temperature (TA) is referenced by TL; the highest junction temperature is referenced by TH. 3 Maximum speed is the maximum frequency allowed including frequency modulation (FM). MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 3 MPC5125 Block Diagrams 2 MPC5125 Block Diagrams Figure 2 shows a simplified MPC5125 block diagram. Functionally Multiplexed I/O Display SDR, Mobile DDR, DDR1/2 Memory FEC1 DIU Multi-Port Memory Controller EMB LPC FEC2 J1850 CAN × 4 I2C × 3 GPIO × 2 Clock/Reset WDT IPIC JTAG/COP JTAG/COP GPT × 2 PMC USB2 ULPI DMA 64-Channel RTC e300 Power Architecture 32 KB instruction / 32 KB data cache PSC × 10 MPC5125 USB1 ULPI 200 MHz AHB (32 bits) Fuse 32 KB SRAM SDHC × 2 TempSensor 200 MHz CSB Bus (64 bits) 66 MHz IP BUS NFC Figure 2. Simplified MPC5125 Block Diagram MPC5125 Microcontroller Data Sheet, Rev. 4 4 Freescale Semiconductor Pin Assignments 3 Pin Assignments This section details pin assignments. 3.1 324-ball TEPBGA Pin Assignments Figure 3 shows the 324-ball TEPBGA pin assignments. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A VSS VSS EMB_A D01 EMB_A GPIO01 GPIO02 D00 B VSS EMB_A D05 EMB_A D03 EMB_A D02 J1850_ TX C EMB_A D11 EMB_A D09 EMB_A D07 EMB_A D06 D TMPS_ ANAVIZ EMB_A D10 E EMB_A D15 F RTC_X TALO RTC_X TALI SYS_X TALI SYS_X TALO AVDD_ SPLL PSC0_ 1 PSC0_ 2 VDD_I O PSC1_ 4 CAN2_ TX HRESE T_B SRESE T_B I2C1_S DA GPIO00 VSS CAN2_ RX VDD_I O AVSS_ OSC_T MPS_S PLL AVSS_ CPLL VDD_I O PSC0_ 3 PSC1_ 2 CAN1_ TX TDO VDD_I O I2C1_S VDD_I CL O_MEM MA15 MA14 MA11 VDD_I O J1850_ RX GPIO03 HIB_M ODE_B CAN1_ RX AVDD_ OSC_T MPS PSC0_ 0 PSC1_ 0 PSC1_ 1 VDD_I O TDI TCK PORES ET_B MCKE MRAS_ B MA12 VDD_I O_MEM MA09 VDD_I O AVDD_ EMB_A FUSEW D04 R PSC_M CLK_IN VSS VBAT SPLL_A NAVIZ AVDD_ CPLL PSC0_ 4 VSS PSC1_ 3 TEST TMS TRST_ B VDD_I VDD_I MCS_B O_MEM O_MEM MA13 MA08 MA06 EMB_A D13 EMB_A D12 EMB_A D08 MA10 MA07 MA04 MA03 EMB_A D21 VDD_I O EMB_A D16 VSS MA02 MA05 VSS MA01 G EMB_A D25 EMB_A D18 EMB_A D17 VDD_I O VDD_I O_MEM MA00 MBA2 MCK_B H EMB_A D28 VDD_I O EMB_A D20 EMB_A D14 MBA0 MBA1 VDD_I O_MEM MCK J EMB_A D31 EMB_A D26 EMB_A D23 EMB_A D19 VSS VDD VDD VDD VDD VSS MODT MDQ31 MDQ30 MDQ29 K EMB_A X00 VSS EMB_A D24 EMB_A D22 VSS VSS VSS VSS VSS VDD MVTT3 MDQ28 VSS MDM3 L LPC_A X03 EMB_A X02 EMB_A D29 VSS VDD VSS VSS VSS VSS VDD VSS MDQ26 MDQ27 MDQS3 M LPC_C S0_B VDD_I O EMB_A D30 EMB_A D27 VDD VSS VSS VSS VSS VDD MVTT2 MDQ23 MDQ24 MDQ25 N NFC_R B LPC_O E_B LPC_R WB EMB_A X01 VSS VSS VSS VSS VSS VDD MVREF MDQ20 VSS MDQ22 P NFC_C E0_B VSS LPC_A CK_B VSS VSS VDD VDD VDD VDD VSS VDD_I MDQ18 MDQS2 MDQ21 O_MEM R SDHC1 _D2 SDHC1 _D3 VDD_I O LPC_C LK MVTT1 MDQ16 VDD_I O_MEM MDM2 T SDHC1 _CLK SDHC1 _CMD SDHC1 _D0 SDHC1 _D1 VDD_I MDQ13 O_MEM MDQ17 MDQ19 U FEC1_ CRS VSS FEC1_ COL I2C2_S DA MDQ07 MDQS1 VSS MDQ15 V FEC1_ MDC FEC1_ MDIO VDD_I O I2C2_S CL VDD_I MDQ10 O_MEM MDM1 MDQ14 W FEC1_ TX_CL K FEC1_ TX_ER FEC1_ TXD_1 FEC1_ TXD_0 VDD_I O USB1_ STOP USB1_ DIR VSS USB1_ DATA1 VDD_I MDQ06 O_MEM MDQ11 MDQ12 Y FEC1_ TXD_3 VSS FEC1_ TX_EN FEC1_ RXD_2 FEC1_ RX_ER USB1_ DATA6 USB1_ DATA5 USB1_ CLK USB1_ DATA0 DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_VS MDQ01 01 03 07 10 14 17 22 YNC MDM0 AA FEC1_ TXD_2 FEC1_ RXD_3 FEC1_ RXD_1 VDD_I O USB1_ NEXT VSS USB1_ DATA4 DIU_DE VDD_I O DIU_LD DIU_LD 02 04 MDQ02 MDQS0 MDQ04 AB VSS FEC1_ RXD_0 FEC1_ RX_DV FEC1_ RX_CL K USB1_ DATA7 USB1_ DATA3 USB1_ DATA2 DIU_CL DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD K 00 05 06 09 12 15 18 19 20 TOP DOWN VIEW VSS DIU_HS YNC VSS VDD_I O DIU_LD DIU_LD 08 13 DIU_LD 11 VDD_I O VDD_I O DIU_LD 16 DIU_LD 21 VDD_I O VSS DIU_LD 23 MVTT0 VSS VDD_I O MDQ00 20 21 MCAS_ MWE_B B MDQ05 22 VSS VDD_I MDQ09 O_MEM VDD_I MDQ03 O_MEM MDQ08 VSS Figure 3. Ball Map for the MPC5125 324 TEPBGA Package MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 5 Pin Muxing and Reset States Pin Assignments 6 3.2 Table 2 provides the pinout listing for the MPC5125. Table 2. MPC5125 Pin Multiplexing Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor GPIO00 — ALT0 ALT1 ALT2 ALT3 GPIO00 — — — GPIO1 — — — I — — — VBAT Dedicated input can be used to receive an external wakeup. B6 GPIO01 — ALT0 ALT1 ALT2 ALT3 GPIO01 — — — GPIO1 — — — I — — — VBAT Dedicated input can be used to receive an external wakeup. A5 GPIO02 — ALT0 ALT1 ALT2 ALT3 GPIO02 — — — GPIO1 — — — I — — — VBAT Dedicated input can be used to receive an external wakeup. A6 GPIO03 — ALT0 ALT1 ALT2 ALT3 GPIO03 — — — GPIO1 — — — I — — — VBAT Dedicated input can be used to receive an external wakeup. C7 RTC_XTALI — ALT0 ALT1 ALT2 ALT3 RTC_XTALI — — — RTC — — — I — — — VBAT — A8 RTC_XTALO — ALT0 ALT1 ALT2 ALT3 RTC_XTALO — — — RTC — — — O — — — VBAT — A7 HIB_MODE — ALT0 ALT1 ALT2 ALT3 HIB_MODE — — — RTC — — — O — — — VBAT In Hibernation mode , this pin provides a signal to shut down an external power supply. C8 Analog Visible Signal Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin SPLL_ANAVIZ TMPS_ANAVIZ Pad I/O Alternate Control Register1 Function3 and Offset2 — — Functions4 Peripheral5 I/O Power Domain Direction MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 ALT0 ALT1 ALT2 ALT3 SPLL_ANAVIZ — — — — — — — — — ALT0 ALT1 ALT2 ALT3 TMPS_ANAVIZ — — — — — — — — — Notes Pin — — D9 — — D1 — ALT0 ALT1 ALT2 ALT3 SYS_XTALI — — — SysClock — — — I — — — SYS_PLL _AVDD — A9 SYS_XTALO — ALT0 ALT1 ALT2 ALT3 SYS_XTALO — — — SysClock — — — O — — — SYS_PLL _AVDD — A10 MCS 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MCS0 — — — DRAM — — — O — — — VDD_IO_MEM — D18 MCAS 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MCAS — — — DRAM — — — O — — — VDD_IO_MEM — A20 MRAS 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MRAS — — — DRAM — — — O — — — VDD_IO_MEM — C19 MVREF — ALT0 ALT1 ALT2 ALT3 MVREF — — — DRAM — — — I — — — VDD_IO_MEM — N19 7 Pin Assignments SYS_XTALI Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 MVTT0 — ALT0 ALT1 ALT2 ALT3 MVTT0 — — — DRAM — — — I — — — VDD_IO_MEM — W18 MVTT1 — ALT0 ALT1 ALT2 ALT3 MVTT1 — — — DRAM — — — I — — — VDD_IO_MEM — R19 MVTT2 — ALT0 ALT1 ALT2 ALT3 MVTT2 — — — DRAM — — — I — — — VDD_IO_MEM — M19 MVTT3 — ALT0 ALT1 ALT2 ALT3 MVTT3 — — — DRAM — — — I — — — VDD_IO_MEM — K19 Freescale Semiconductor MWE 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MWE — — — DRAM — — — O — — — VDD_IO_MEM — A21 MDQ00 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ00 — — — DRAM — — — I/O — — — VDD_IO_MEM — AB19 MDQ01 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ01 — — — DRAM — — — I/O — — — VDD_IO_MEM — Y18 MDQ02 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ02 — — — DRAM — — — I/O — — — VDD_IO_MEM — AA19 Pin Assignments 8 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ03 — — — DRAM — — — I/O — — — VDD_IO_MEM — AB21 MDQ04 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ04 — — — DRAM — — — I/O — — — VDD_IO_MEM — AA21 MDQ05 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ05 — — — DRAM — — — I/O — — — VDD_IO_MEM — Y20 MDQ06 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ06 — — — DRAM — — — I/O — — — VDD_IO_MEM — W20 MDQ07 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ07 — — — DRAM — — — I/O — — — VDD_IO_MEM — U19 MDQ08 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ08 — — — DRAM — — — I/O — — — VDD_IO_MEM — AA22 MDQ09 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ09 — — — DRAM — — — I/O — — — VDD_IO_MEM — Y22 MDQ10 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ10 — — — DRAM — — — I/O — — — VDD_IO_MEM — V20 9 Pin Assignments MDQ03 Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor MDQ11 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ11 — — — DRAM — — — I/O — — — VDD_IO_MEM — W21 MDQ12 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ12 — — — DRAM — — — I/O — — — VDD_IO_MEM — W22 MDQ13 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ13 — — — DRAM — — — I/O — — — VDD_IO_MEM — T20 MDQ14 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ14 — — — DRAM — — — I/O — — — VDD_IO_MEM — V22 MDQ15 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ15 — — — DRAM — — — I/O — — — VDD_IO_MEM — U22 MDQ16 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ16 — — GPT1[0] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — R20 MDQ17 0x00 ALT0 IO_CON- ALT1 TROL_MEM ALT2 ALT3 MDQ17 — — GPT1[1] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — T21 MDQ18 0x00  IO_CON- TROL_MEM MDQ18 — — GPT1[2] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — P20 ALT0 ALT1 ALT2 ALT3 Pin Assignments 10 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ19 — — GPT1[3] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — T22 MDQ20 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ20 — — GPT1[4] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — N20 MDQ21 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ21 — — GPT1[5] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — P22 MDQ22 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ22 — — GPT1[6] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — N22 MDQ23 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ23 — — GPT1[7] DRAM — — GPT1 I/O — — I/O VDD_IO_MEM — M20 MDQ24 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ24 — — GPIO21 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — M21 MDQ25 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ25 — — GPIO22 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — M22 MDQ26 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ26 — — GPIO23 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — L20 11 Pin Assignments MDQ19 Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor MDQ27 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ27 — — GPIO24 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — L21 MDQ28 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ28 — — GPIO25 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — K20 MDQ29 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ29 — — GPIO26 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — J22 MDQ30 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ30 — — GPIO27 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — J21 MDQ31 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQ31 — — GPIO28 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — J20 MDM0 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDM0 — — — DRAM — — — O — — — VDD_IO_MEM — Y19 MDM1 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDM1 — — — DRAM — — — O — — — VDD_IO_MEM — V21 MDM2 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDM2 — — GPIO29 DRAM — — GPIO1 O — — I/O VDD_IO_MEM — R22 Pin Assignments 12 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDM3 — — GPIO30 DRAM — — GPIO1 O — — I/O VDD_IO_MEM — K22 MDQS0 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQS0 — — — DRAM — — — I/O — — — VDD_IO_MEM — AA20 MDQS1 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQS1 — — — DRAM — — — I/O — — — VDD_IO_MEM — U20 MDQS2 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQS2 — — GPIO31 DRAM — — GPIO1 I/O — — I/O VDD_IO_MEM — P21 MDQS3 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MDQS3 — — GPIO32 DRAM — — GPIO2 I/O — — I/O VDD_IO_MEM — L22 MBA0 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MBA0 — — — DRAM — — — O — — — VDD_IO_MEM — H19 MBA1 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MBA1 — — — DRAM — — — O — — — VDD_IO_MEM — H20 MBA2 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MBA2 — — — DRAM — — — O — — — VDD_IO_MEM — G21 13 Pin Assignments MDM3 Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor MA00 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA00 — — — DRAM — — — O — — — VDD_IO_MEM — G20 MA01 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA01 — — — DRAM — — — O — — — VDD_IO_MEM — F22 MA02 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA02 — — — DRAM — — — O — — — VDD_IO_MEM — F19 MA03 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA03 — — — DRAM — — — O — — — VDD_IO_MEM — E22 MA04 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA04 — — — DRAM — — — O — — — VDD_IO_MEM — E21 MA05 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA05 — — — DRAM — — — O — — — VDD_IO_MEM — F20 MA06 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA06 — — — DRAM — — — O — — — VDD_IO_MEM — D22 MA07 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA07 — — — DRAM — — — O — — — VDD_IO_MEM — E20 Pin Assignments 14 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA08 — — — DRAM — — — O — — — VDD_IO_MEM — D21 MA09 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA09 — — — DRAM — — — O — — — VDD_IO_MEM — C22 MA10 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA10 — — — DRAM — — — O — — — VDD_IO_MEM — E19 MA11 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA11 — — — DRAM — — — O — — — VDD_IO_MEM — B22 MA12 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA12 — — — DRAM — — — O — — — VDD_IO_MEM — C20 MA13 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA13 — — — DRAM — — — O — — — VDD_IO_MEM — D20 MA14 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA14 — — — DRAM — — — O — — — VDD_IO_MEM — B21 MA15 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MA15/MCS1 — — — DRAM — — — O — — — VDD_IO_MEM — B20 15 Pin Assignments MA08 Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor MCK 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MCK — — — DRAM — — — O — — — VDD_IO_MEM — H22 MCK 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MCK — — — DRAM — — — O — — — VDD_IO_MEM — G22 MCKE 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MCKE — — — DRAM — — — O — — — VDD_IO_MEM — C18 MODT 0x00  IO_CON- TROL_MEM ALT0 ALT1 ALT2 ALT3 MODT — — — DRAM — — — O — — — VDD_IO_MEM — J19 0x04  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_CLK TPA1 — GPIO04 LPC — — GPIO1 O VDD_IO — R4 — I/O LPC_OE_B 0x05  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_OE PSC3_3 — GPIO05 LPC PSC3 — GPIO1 O I/O — I/O VDD_IO — N2 LPC_RWB 0x06  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_R/W PSC3_4 — GPIO06 LPC PSC3 — GPIO1 O I/O — I/O VDD_IO — N3 LPC_CS0_B 0x07  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_CS0 — — GPIO07 LPC — — GPIO1 O — — I/O VDD_IO — M1 LPC_CLK Pin Assignments 16 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 LPC_ACK_B 0x08  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_ACK/LPC_BURST NFC_CE1 LPC_CS1 GPIO08 LPC NFC LPC GPIO1 I/O O O I/O VDD_IO — P3 LPC_AX03 0x09  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_AX03/LPC_TS NFC_CE2 LPC_CS2 — LPC NFC LPC — O O O — VDD_IO — L1 EMB_AD00 0x2C  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_AD00/NFC_AD00 — RST_CONF_LOC0 — LPC — I/O — VDD_IO ALT2: Reset configuration Boot ROM Location 0 A4 — — ALT0 ALT1 ALT2 ALT3 LPC_AD01/NFC_AD01 — RST_CONF_LOC1 — LPC — I/O — VDD_IO ALT2: Reset configuration Boot ROM Location 1 A3 — — ALT0 ALT1 ALT2 ALT3 LPC_AD02/NFC_AD02 — RST_CONF_BMS — LPC — I/O — VDD_IO ALT2: Reset configuration Boot Mode Select B4 — — ALT0 ALT1 ALT2 ALT3 LPC_AD03/NFC_AD03 — RST_CONF_LPCDBW0 — LPC — I/O — VDD_IO ALT2: Reset configuration LPC Port Size 0 B3 — — ALT0 ALT1 ALT2 ALT3 LPC_AD04/NFC_AD04 — RST_CONF_LPCDBW1 — LPC — I/O — VDD_IO ALT2: Reset configuration LPC Port Size 1 D5 — — EMB_AD01 EMB_AD02 EMB_AD03 EMB_AD04 0x2B  STD_PU 0x2A  STD_PU 0x29  STD_PU 0x28  STD_PU Pin Assignments 17 Pin EMB_AD05 EMB_AD06 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 EMB_AD07 EMB_AD08 EMB_AD09 EMB_AD10 EMB_AD11 Freescale Semiconductor EMB_AD12 Pad I/O Alternate Control Register1 Function3 and Offset2 0x27  STD_PU 0x26  STD_PU 0x25  STD_PU 0x24  STD_PU 0x23  STD_PU 0x22  STD_PU 0x21  STD_PU 0x20  STD_PU Functions4 Peripheral5 I/O Power Domain Direction ALT0 ALT1 ALT2 ALT3 LPC_AD05/NFC_AD05 — RST_CONF_COREPLL6 — LPC — I/O — — — ALT0 ALT1 ALT2 ALT3 LPC_AD06/NFC_AD06 — RST_CONF_COREPLL5 — LPC — I/O — — — ALT0 ALT1 ALT2 ALT3 LPC_AD07/NFC_AD07 — RST_CONF_COREPLL4 — LPC — I/O — — — ALT0 ALT1 ALT2 ALT3 LPC_AD08/NFC_AD08 PSC3_2 RST_CONF_SPMF0 GPIO28 LPC PSC3 I/O I/O GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD09/NFC_AD09 PSC3_1 RST_CONF_SPMF1 GPIO27 LPC PSC3 I/O I/O GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD10/NFC_AD10 PSC3_0 RST_CONF_SPMF2 GPIO26 LPC PSC3 I/O I/O GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD11/NFC_AD11 PSC2_4 RST_CONF_SPMF3 GPIO25 LPC PSC2 I/O I/O GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD12/NFC_AD12 PSC2_3 RST_CONF_PREDIV0 GPIO24 LPC PSC2 I/O I/O GPIO1 I/O Notes Pin VDD_IO ALT2: Reset configuration Core PLL Multiplication Factor 0 B2 VDD_IO ALT2: Reset configuration Core PLL Multiplication Factor 1 C4 VDD_IO ALT2: Reset configuration Core PLL Multiplication Factor 2 C3 VDD_IO ALT2: Reset configuration System PLL Multiplication Factor 0 E4 VDD_IO ALT2: Reset configuration System PLL Multiplication Factor 1 C2 VDD_IO ALT2: Reset configuration System PLL Multiplication Factor 2 D2 VDD_IO ALT2: Reset configuration C1 VDD_IO ALT2: Reset configuration E3 Pin Assignments 18 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin EMB_AD13 EMB_AD14 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 EMB_AD15 EMB_AD16 EMB_AD17 EMB_AD18 Pad I/O Alternate Control Register1 Function3 and Offset2 0x1F  STD_PU 0x1E  STD_PU 0x1D  STD_PU 0x1C  STD_PU 0x1B  STD_PU 0x1A  STD_PU Functions4 Peripheral5 I/O Power Domain Direction ALT0 ALT1 ALT2 ALT3 LPC_AD13/NFC_AD13 PSC2_2 RST_CONF_PREDIV1 GPIO23 LPC PSC2 I/O I/O GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD14/NFC_AD14 PSC2_1 RST_CONF_PREDIV2 GPIO22 LPC PSC2 I/O I/O GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD15/NFC_AD15 PSC2_0 RST_CONF_SYSOSCEN GPIO21 LPC PSC2 I/O I/O GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD16/LPC_A01/NFC LPC _WE — — — — — I/O — ALT0 ALT1 ALT2 ALT3 LPC_AD17/LPC_A02/NFC LPC — _RE — RST_CONF_PLL_LOCK — — I/O — ALT0 ALT1 ALT2 ALT3 LPC_AD18/LPC_A03/NFC LPC _CLE — — RST_CONF_LPCMX — — I/O — Notes Pin VDD_IO ALT2: Reset configuration E2 VDD_IO ALT2: Reset configuration H4 VDD_IO ALT2: Reset configuration E1 VDD_IO F3 — — VDD_IO ALT2: Reset configuration G3 VDD_IO ALT2: Reset configuration G2 — — Pin Assignments 19 Pin EMB_AD19 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 EMB_AD20 EMB_AD21 EMB_AD22 Pad I/O Alternate Control Register1 Function3 and Offset2 0x19  STD_PU 0x18  STD_PU 0x17  STD_PU 0x16 STD_PU EMB_AD23 EMB_AD24 EMB_AD25 Freescale Semiconductor EMB_AD26 0x15  STD_PU 0x14  STD_PU 0x13  STD_PU 0x12  STD_PU Functions4 Peripheral5 I/O Power Domain Direction Notes Pin ALT0 ALT1 ALT2 ALT3 LPC_AD19/LPC_A04/NFC LPC _ALE — — RST_CONF_LPCWA — — I/O — ALT0 ALT1 ALT2 ALT3 LPC_AD20/LPC_A05 — — GPIO20 LPC I/O — — I/O VDD_IO — H3 ALT0 ALT1 ALT2 ALT3 LPC_AD21/LPC_A06 — — GPIO19 LPC I/O — — I/O VDD_IO — F1 ALT0 ALT1 ALT2 ALT3 LPC_AD22/LPC_A07 — RST_CONF_LPC_TS GPIO18 LPC I/O — VDD_IO GPIO1 I/O ALT0 ALT1 ALT2 ALT3 LPC_AD23/LPC_A08 — — GPIO17 LPC I/O — — I/O VDD_IO — J3 ALT0 ALT1 ALT2 ALT3 LPC_AD24/LPC_A09 — — GPIO16 LPC I/O — — I/O VDD_IO — K3 ALT0 ALT1 ALT2 ALT3 LPC_AD25/LPC_A10 — — GPIO15 LPC I/O — — I/O VDD_IO — G1 ALT0 ALT1 ALT2 ALT3 LPC_AD26/LPC_A11 — — GPIO14 LPC I/O — — I/O VDD_IO — J2 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 VDD_IO ALT2: Reset configuration J4 — ALT2: Reset configuration K4 Pin Assignments 20 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin EMB_AD27 EMB_AD28 Pad I/O Alternate Control Register1 Function3 and Offset2 0x11  STD_PU MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 EMB_AD30 EMB_AD31 EMB_AX00 LPC_AD27/LPC_A12 — — GPIO13 LPC ALT0 ALT1 ALT2 ALT3 LPC_AD28/LPC_A13 — — GPIO12 LPC ALT0 ALT1 ALT2 ALT3 LPC_AD29/LPC_A14 — — GPIO11 LPC 0x0E ALT0  ALT1 STD_PU_ST ALT2 ALT3 LPC_AD30/LPC_A15 CAN_CLK — GPIO10 LPC ALT0 0x0D  ALT1 STD_PU_ST ALT2 ALT3 LPC_AD31/LPC_A16 PSC_MCLK_IN — GPIO09 LPC 0x0C ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 0x10 0x0F  STD_PU STD_PU EMB_AX01 Peripheral5 ALT0 ALT1 ALT2 ALT3 STD_PU EMB_AD29 Functions4 0x0B  STD_PU I/O Power Domain Direction Notes Pin I/O — — I/O VDD_IO — M4 I/O — — I/O VDD_IO — H1 I/O — — I/O VDD_IO — L3 I/O O — I/O VDD_IO — M3 VDD_IO — J1 GPIO1 I/O I — I/O LPC_AX00/LPC_ALE — — — LPC — — — O — — — VDD_IO — K1 LPC_AX01/LPC_TSIZ0 — LPC_CS4 — LPC — LPC — O — O — VDD_IO — N4 GPIO1 GPIO1 GPIO1 GPIO1 Pin Assignments 21 Pin EMB_AX02 Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 0x0A  STD_PU ALT0 ALT1 ALT2 ALT3 LPC_AX02/LPC_TSIZ1 NFC_CE3 LPC_CS3 — LPC 0x02D  STD_PU ALT0 ALT1 ALT2 ALT3 NFC_RB I/O Power Domain Direction Notes Pin VDD_IO — L2 LPC — O O O — NFC_CE0 — — GPIO29 NFC — — GPIO1 O — — I/O VDD_IO — P1 0x02E ALT0  ALT1 STD_PU_ST ALT2 ALT3 NFC_R/B0 — — GPIO30 NFC — — GPIO1 I — — I/O VDD_IO When booting from the NFC, the NFC_RB pin needs an external pullup resistor. N1 DIU_CLK 0x02F  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_CLK PSC4_0 USB1_DATA0 LPC_AX04 DIU PSC4 USB1 LPC O I/O I/O O VDD_IO — AB8 DIU_DE 0x030  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_DE PSC4_1 USB1_DATA1 LPC_AX05 DIU PSC4 USB1 LPC O I/O I/O O VDD_IO — AA8 DIU_HSYNC 0x031  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_HSYNC PSC4_2 USB1_DATA2 LPC_AX06 DIU PSC4 USB1 LPC O I/O I/O O VDD_IO — W11 DIU_VSYNC 0x032  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_VSYNC PSC4_3 USB1_DATA3 GPIO31 DIU PSC4 USB1 GPIO1 I/O I/O I/O I/O VDD_IO — Y17 CAN3_RX CLK_OUT2 DIU_LD00 GPIO32 CAN3 DIU DIU GPIO2 I O I/O I/O VDD_IO — AB9 NFC_CE0_B MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor DIU_LD00 0x033 ALT0  ALT1 STD_PU_ST ALT2 ALT3 Pin Assignments 22 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin VDD_IO — Y10 VDD_IO — AA10 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x034  STD_PU ALT0 ALT1 ALT2 ALT3 CAN3_TX CLK_OUT3 DIU_LD01 GPIO33 CAN3 DIU DIU GPIO2 O O I/O I/O DIU_LD02 0x035  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD02 PSC4_4 USB1_DATA4 LPC_AX07 DIU PSC4 USB1 LPC I/O I/O O DIU_LD03 0x036  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD03 PSC5_0 USB1_DATA5 LPC_AX08 DIU PSC5 USB1 LPC I/O I/O I/O O VDD_IO — Y11 DIU_LD04 0x037  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD04 PSC5_1 USB1_DATA6 LPC_AX09 DIU PSC5 USB1 LPC I/O I/O I/O O VDD_IO — AA11 DIU_LD05 0x038  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD05 PSC5_2 USB1_DATA7 GPIO34 DIU PSC5 USB1 GPIO2 I/O I/O I/O I/O VDD_IO — AB10 DIU_LD06 0x039  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD06 PSC5_3 USB1_STOP GPIO35 DIU PSC5 USB1 GPIO2 I/O I/O O I/O VDD_IO — AB11 DIU_LD07 0x03A ALT0  ALT1 STD_PU_ST ALT2 ALT3 DIU_LD07 PSC5_4 USB1_CLK GPIO36 DIU PSC5 USB1 GPIO2 I/O I/O I I/O VDD_IO — Y12 DIU_LD08 0x03B ALT0  ALT1 STD_PU_ST ALT2 ALT3 CAN4_RX PSC6_0 DIU_LD08 GPIO37 CAN4 PSC6 DIU GPIO2 I I/O I/O I/O VDD_IO — W13 23 Pin Assignments DIU_LD01 Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor DIU_LD09 0x03C  STD_PU ALT0 ALT1 ALT2 ALT3 CAN4_TX PSC6_1 DIU_LD09 GPIO38 CAN4 PSC6 DIU GPIO2 O I/O I/O I/O VDD_IO — AB12 DIU_LD10 0x03D  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD10 PSC6_2 USB1_NEXT GPIO39 DIU PSC6 USB1 GPIO2 I/O I/O O I/O VDD_IO — Y13 DIU_LD11 0x03E  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD11 PSC6_3 USB1_DIR GPIO40 DIU PSC6 USB1 GPIO2 I/O I/O I I/O VDD_IO — AA13 DIU_LD12 0x03F  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD12 PSC6_4 USB2_DATA0 GPT2[0] DIU PSC6 USB2 GPT2 I/O I/O I/O I/O VDD_IO — AB13 DIU_LD13 0x040  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD13 PSC7_0 USB2_DATA1 GPT2[1] DIU PSC7 USB2 GPT2 I/O I/O I/O I/O VDD_IO — W14 DIU_LD14 0x041  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD14 PSC7_1 USB2_DATA2 GPT2[2] DIU PSC7 USB2 GPT2 I/O I/O I/O I/O VDD_IO — Y14 DIU_LD15 0x042  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD15 PSC7_2 USB2_DATA3 GPT2[3] DIU PSC7 USB2 GPT2 I/O I/O I/O I/O VDD_IO — AB14 DIU_LD16 0x043 ALT0  ALT1 STD_PU_ST ALT2 ALT3 CLK_OUT0 I2C3_SCL DIU_LD16 GPIO41 DIU I2C2 DIU GPIO2 O I/O I/O I/O VDD_IO — AA15 Pin Assignments 24 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x044 ALT0  ALT1 STD_PU_ST ALT2 ALT3 CLK_OUT1 I2C3_SDA DIU_LD17 GPIO42 DIU I2C3 DIU GPIO2 O I/O I/O I/O VDD_IO — Y15 DIU_LD18 0x045  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD18 PSC7_3 USB2_DATA4 GPT2[4] DIU PSC7 USB2 GPT2 I/O I/O I/O I/O VDD_IO — AB15 DIU_LD19 0x046  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD19 PSC7_4 USB2_DATA5 GPT2[5] DIU PSC7 USB2 GPT2 I/O I/O I/O I/O VDD_IO — AB16 DIU_LD20 0x047  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD20 PSC8_0 USB2_DATA6 GPT2[6] DIU PSC8 USB2 GPT2 I/O I/O I/O I/O VDD_IO — AB17 DIU_LD21 0x048  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD21 PSC8_1 USB2_DATA7 GPT2[7] DIU PSC8 USB2 GPT2 I/O I/O I/O I/O VDD_IO — W16 DIU_LD22 0x049  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD22 PSC8_2 USB2_DIR GPIO43 DIU PSC8 USB2 GPIO2 I/O I/O I I/O VDD_IO — Y16 DIU_LD23 0x04A  STD_PU ALT0 ALT1 ALT2 ALT3 DIU_LD23 PSC8_3 USB2_NEXT GPIO44 DIU PSC8 USB2 GPIO2 I/O I/O I I/O VDD_IO — AA17 I2C2_SCL 0x4B ALT0  ALT1 STD_PU_ST ALT2 ALT3 I2C2_SCL PSC8_4 USB2_CLK GPIO45 I2C2 PSC8 USB2 GPIO2 I/O I/O I I/O VDD_IO — V4 25 Pin Assignments DIU_LD17 Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 I2C2_SDA 0x4C ALT0  ALT1 STD_PU_ST ALT2 ALT3 I2C2_SDA PSC9_4 USB2_STOP GPIO46 I2C2 PSC9 USB2 GPIO2 I/O I/O O I/O VDD_IO — U4 I2C1_SCL 0x4F ALT0  ALT1 STD_PU_ST ALT2 ALT3 I2C1_SCL PSC9_2 CAN3_RX GPIO49 I2C1 PSC9 CAN3 GPIO2 I/O I/O I I/O VDD_IO — B18 I2C1_SDA 0x50 ALT0  ALT1 STD_PU_ST ALT2 ALT3 I2C1_SDA PSC9_3 CAN3_TX GPIO50 I2C1 PSC9 CAN3 GPIO2 I/O I/O O I/O VDD_IO — A19 Freescale Semiconductor CAN1_RX — ALT0 ALT1 ALT2 ALT3 CAN1_RX — — — CAN1 — — — I — — — VBAT Dedicated input can be used to receive an external wakeup. C9 CAN2_RX — ALT0 ALT1 ALT2 ALT3 CAN2_RX — — — CAN2 — — — I — — — VBAT Dedicated input can be used to receive an external wakeup. B8 CAN1_TX 0x4D ALT0  ALT1 STD_PU_ST ALT2 ALT3 CAN1_TX PSC9_0 I2C2_SCL GPIO47 CAN1 PSC9 I2C2 GPIO2 O I/O I/O I/O VDD_IO — B15 CAN2_TX 0x4E ALT0  ALT1 STD_PU_ST ALT2 ALT3 CAN2_TX PSC9_1 I2C2_SDA GPIO48 CAN2 PSC9 I2C2 GPIO2 O I/O I/O I/O VDD_IO — A16 0x51  STD_PU FEC1_TXD_2 PSC2_0 USB2_DATA0 GPIO51 FEC1 PSC2 USB2 GPIO2 O I/O I/O I/O VDD_IO — AA1 FEC1_TXD_2 ALT0 ALT1 ALT2 ALT3 Pin Assignments 26 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x52  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_TXD_3 PSC2_1 USB2_DATA1 GPIO52 FEC1 PSC2 USB2 GPIO2 O I/O I/O I/O VDD_IO — Y1 FEC1_RXD_2 0x53  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_RXD_2 PSC2_2 USB2_DATA2 GPIO53 FEC1 PSC2 USB2 GPIO2 I I/O I/O I/O VDD_IO — Y4 FEC1_RXD_3 0x54  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_RXD_3 PSC2_3 USB2_DATA3 GPIO54 FEC1 PSC2 USB2 GPIO2 I I/O I/O I/O VDD_IO — AA2 FEC1_CRS 0x55  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_CRS PSC2_4 USB2_DATA4 GPIO55 FEC1 PSC2 USB2 GPIO2 I I/O I/O I/O VDD_IO — U1 FEC1_TX_ER 0x56  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_TX_ER PSC3_0 USB2_DATA5 GPIO56 FEC1 PSC3 USB2 GPIO2 O I/O I/O I/O VDD_IO — W2 FEC1_RXD_1 0x57  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_RXD_1/RMII_RX1 PSC3_1 USB2_DATA6 GPIO57 FEC1 PSC3 USB2 GPIO2 I I/O I/O I/O VDD_IO — AA3 FEC1_TXD_1 0x58  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_TXD_1/RMII_TX1 PSC3_2 USB2_DATA7 GPIO58 FEC1 PSC3 USB2 GPIO2 O I/O I/O I/O VDD_IO — W3 FEC1_MDC 0x59  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_MDC/RMII_MDC PSC3_3 USB2_DIR GPIO59 FEC1 PSC3 USB2 GPIO2 O I/O I I/O VDD_IO — V1 27 Pin Assignments FEC1_TXD_3 Pin FEC1_RX_ER Pad I/O Alternate Control Register1 Function3 and Offset2 0x5A Peripheral5 I/O Power Domain Direction Notes Pin FEC1_RX_ER/RMII_RX_E R PSC3_4 USB2_NEXT GPIO60 FEC1 PSC3 USB2 GPIO2 I I/O I I/O VDD_IO — Y5 0x5B ALT0  ALT1 STD_PU_ST ALT2 ALT3 FEC1_MDIO/RMII_MDIO — USB2_CLK GPIO61 FEC1 — USB2 GPIO2 I/O — I I/O VDD_IO — V2 FEC1_RXD_0 0x5C  STD_PU ALT0 ALT1 ALT2 ALT3 FEC1_RXD_0/RMII_RX0 — USB2_STOP GPIO62 FEC1 — USB2 GPIO2 I — O I/O VDD_IO — AB2 FEC1_TXD_0 ALT0 0x5D ALT1  STD_PU_ST ALT2 ALT3 FEC1_TXD_0/RMII_TX0 — NFC_R/B1 GPIO63 FEC1 — NFC GPIO2 O — I I/O VDD_IO — W4 FEC1_TX_CLK 0x5E ALT0  ALT1 STD_PU_ST ALT2 ALT3 FEC1_TX_CLK/RMII_REF _CLK PSC0_0 — GPIO04 FEC1 PSC0 — GPIO1 I I/O — I/O VDD_IO — W1 FEC1_RX_CLK 0x5F ALT0  ALT1 STD_PU_ST ALT2 ALT3 FEC1_RX_CLK PSC0_1 NFC_R/B2 GPIO05 FEC1 PSC0 — GPIO1 I I/O I I/O VDD_IO — AB4 FEC1_RX_DV 0x60 ALT0  ALT1 STD_PU_ST ALT2 ALT3 FEC1_RX_DV/RMII_CRS_ DV PSC0_2 NFC_R/B3 GPIO06 FEC1 PSC0 NFC GPIO1 I I/O I I/O VDD_IO — AB3 STD_PU MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 FEC1_MDIO ALT0 ALT1 ALT2 ALT3 Functions4 Pin Assignments 28 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin FEC1_TX_EN Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 ALT2 ALT3 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 FEC1 PSC0 — GPIO1 O I/O — I/O VDD_IO — Y3 0x62 ALT0  ALT1 STD_PU_ST ALT2 ALT3 FEC1_COL PSC0_4 — GPIO08 FEC1 PSC0 I I/O — I/O VDD_IO — U3 USB1_DATA0 0x63  STD_PU ALT0 ALT1 ALT2 ALT3 USB1_DATA0 PSC1_0 FEC2_RXD_1/RMII_RX1 — USB2 PSC1 FEC2 I/O I/O I — VDD_IO — Y9 USB1_DATA1 0x64  STD_PU ALT0 ALT1 ALT2 ALT3 USB1_DATA1 PSC1_1 FEC2_TXD_1/RMII_TX1 — USB2 PSC1 FEC2 I/O I/O O — VDD_IO — W9 USB1_DATA2 0x65  STD_PU ALT0 ALT1 ALT2 ALT3 USB1_DATA2 PSC1_2 FEC2_MDC/RMII_MDC — USB2 PSC1 FEC2 I/O I/O O — VDD_IO — AB7 USB1_DATA3 0x66  STD_PU ALT0 ALT1 ALT2 ALT3 USB1_DATA3 USB2 PSC1_3 PSC1 FEC2_RX_ER/RMII_RX_E FEC2 R — I/O I/O I — VDD_IO — AB6 USB1_DATA4 0x67  STD_PU ALT0 ALT1 ALT2 ALT3 USB1_DATA4 PSC1_4 FEC2_MDIO/RMII_MDIO — USB2 PSC1 FEC2 I/O I/O I/O — VDD_IO — AA7 USB1_DATA5 0x68  STD_PU ALT0 ALT1 ALT2 ALT3 USB1_DATA5 PSC4_0 FEC2_RXD_0/RMII_RX0 — USB2 PSC4 FEC2 I/O I/O I — VDD_IO — Y7 GPIO1 29 Pin Assignments FEC1_TX_EN/RMII_TX_E N PSC0_3 — GPIO07 FEC1_COL 0x61  STD_PU Functions4 Pin Pad I/O Alternate Control Register1 Function3 and Offset2 USB1_DATA6 0x69  STD_PU USB1_DATA7 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 Freescale Semiconductor I/O I/O O — VDD_IO — Y6 0x6A ALT0  ALT1 STD_PU_ST ALT2 ALT3 USB1_DATA7 USB2 PSC4 PSC4_2 FEC2_TX_CLK/RMII_REF FEC2 _CLK — I/O I/O I — VDD_IO — AB5 USB1_STOP 0x6B ALT0  ALT1 STD_PU_ST ALT2 ALT3 USB1_STOP PSC4_3 FEC2_RX_CLK — USB2 PSC4 FEC2 O I/O I — VDD_IO — W6 USB1_CLK 0x6C ALT0 ALT1  STD_PU_ST ALT2 ALT3 USB2 USB1_CLK PSC4 PSC4_4 FEC2_RX_DV/RMII_CRS_ FEC2 DV — I I/O I — VDD_IO — Y8 0x6D  STD_PU USB1_NEXT — FEC2_TX_EN/RMII_TX_E N GPIO09 USB2 — FEC2 GPIO1 I — O I/O VDD_IO — AA5 USB1_DIR — FEC2_COL GPIO10 USB2 — FEC2 GPIO1 I — I I/O VDD_IO — W7 O O O I/O VDD_IO — T1 USB1_DIR ALT0 ALT1 ALT2 ALT3 0x6E ALT0  ALT1 STD_PU_ST ALT2 ALT3 USB1_DATA6 PSC4_1 FEC2_TXD_0/RMII_TX0 — Peripheral5 USB2 PSC4 FEC2 USB1_NEXT ALT0 ALT1 ALT2 ALT3 Functions4 SDHC SDHC1_CLK 0x6F  STD_PU ALT0 ALT1 ALT2 ALT3 SDHC1_CLK NFC_CE1 FEC2_TXD_2 GPIO11 SDHC1 NFC FEC2 GPIO1 Pin Assignments 30 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 0x70  STD_PU ALT0 ALT1 ALT2 ALT3 SDHC1_CMD PSC5_0 FEC2_TXD_3 GPIO12 SDHC1 PSC5 FEC2 GPIO1 I/O I/O O I/O VDD_IO — T2 SDHC1_D0 0x71  STD_PU ALT0 ALT1 ALT2 ALT3 SDHC1_D0 PSC5_1 FEC2_RXD_2 GPIO13 SDHC1 PSC5 FEC2 GPIO1 I/O I/O I I/O VDD_IO — T3 SDHC1_D1 0x72  STD_PU ALT0 ALT1 ALT2 ALT3 SDHC1_D1_IRQ PSC5_2 FEC2_RXD_3 LPC_CS5 SDHC1 PSC5 FEC2 LPC I/O I/O I O VDD_IO — T4 SDHC1_D2 0x73  STD_PU ALT0 ALT1 ALT2 ALT3 SDHC1_D2 PSC5_3 FEC2_CRS LPC_CS6 SDHC1 PSC5 FEC2 LPC I/O I/O I O VDD_IO — R1 SDHC1_D3 0x74  STD_PU ALT0 ALT1 ALT2 ALT3 SDHC1_D3_CD PSC5_4 FEC2_TX_ER LPC_CS7 SDHC1 PSC5 FEC2 LPC I/O I/O O O VDD_IO — R2 0x75 ALT0  ALT1 STD_PU_ST ALT2 ALT3 PSC_MCLK_IN — — GPIO14 I — — I/O VDD_IO — D6 — — GPIO1 PSC0_0 0x76  STD_PU ALT0 ALT1 ALT2 ALT3 PSC0_0 SDHC2_CMD GPT1[0] GPIO15 PSC0 SDHC2 GPT1 GPIO1 I/O I/O I/O I/O VDD_IO — C11 PSC0_1 0x77  STD_PU ALT0 ALT1 ALT2 ALT3 PSC0_1 SDHC2_D0 GPT1[1] GPIO16 PSC0 SDHC2 GPT1 GPIO1 I/O I/O I/O I/O VDD_IO — A12 PSC_MCLK_IN 31 Pin Assignments SDHC1_CMD Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 PSC0_2 0x78  STD_PU ALT0 ALT1 ALT2 ALT3 PSC0_2 SDHC2_D1_IRQ GPT1[2] GPIO17 PSC0 SDHC2 GPT1 GPIO1 I/O I/O I/O I/O VDD_IO — A13 PSC0_3 0x79  STD_PU ALT0 ALT1 ALT2 ALT3 PSC0_3 SDHC2_D2 GPT1[3] GPIO18 PSC0 SDHC2 GPT1 GPIO1 I/O I/O I/O I/O VDD_IO — B13 PSC0_4 0x7A ALT0 ALT1 ALT2 ALT3 PSC0_4 SDHC2_D3_CD GPT1[4] CAN1_TX PSC0 SDHC2 GPT1 CAN1 I/O I/O I/O O VDD_IO — D11 STD_PU PSC1_0 0x7B  STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_0 SDHC2_CLK GPT1[5] CAN2_TX PSC1 SDHC2 GPT1 CAN2 I/O O O O VDD_IO — C12 PSC1_1 0x7C  STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_1 CAN_CLK GPT1[6] IRQ0 PSC1 I/O VDD_IO — C13 GPT1 I/O I 0x7D  STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_2 TPA2 GPT1[7] IRQ1 PSC1 I/O VDD_IO — B14 GPT1 I/O I 0x7E  STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_3 CKSTP_IN NFC_R/B2 GPIO19 PSC1 I/O VDD_IO — D13 NFC GPIO1 I I/O 0x7F  STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_4 CKSTP_OUT NFC_CE2 GPIO20 PSC1 I/O VDD_IO — A15 MFC GPIO1 O I/O PSC1_2 PSC1_3 Freescale Semiconductor PSC1_4 Pin Assignments 32 Table 2. MPC5125 Pin Multiplexing (continued) Freescale Semiconductor Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Alternate Control Register1 Function3 and Offset2 Functions4 Peripheral5 I/O Power Domain Direction Notes Pin MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 J1850_TX 0x80 ALT0  ALT1 STD_PU_ST ALT2 ALT3 J1850_TX — NFC_CE3 I2C1_SCL J1850 — NFC I2C1 O — O I/O VDD_IO — B5 J1850_RX 0x81 ALT0  ALT1 STD_PU_ST ALT2 ALT3 J1850_RX — NFC_R/B3 I2C1_SDA J1850 — NFC I2C1 I — I I/O VDD_IO — C6 JTAG TCK — ALT0 ALT1 ALT2 ALT3 TCK — — — JTAG — — — I — — — VDD_IO 5. This pin contains an enabled internal Schmitt trigger. C16 TDI — ALT0 ALT1 ALT2 ALT3 TDI — — — JTAG — — — I — — — VDD_IO 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. C15 TDO — ALT0 ALT1 ALT2 ALT3 TDO — — — JTAG — — — O — — — VDD_IO TMS — ALT0 ALT1 ALT2 ALT3 TMS — — — JTAG — — — I — — — VDD_IO 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. D15 TRST — ALT0 ALT1 ALT2 ALT3 TRST — — — JTAG — — — I — — — VDD_IO 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. D16 B16 33 Pin Assignments System Control — Pin HRESET Pad I/O Alternate Control Register1 Function3 and Offset2 — ALT0 ALT1 ALT2 ALT3 Functions4 HRESET — — — Peripheral5 — — — I/O Power Domain Direction I — — — VDD_IO Notes Pin 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. A17 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 5. This pin contains an enabled internal schmitt-trigger. PORESET — ALT0 ALT1 ALT2 ALT3 PORESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. C17 2. This pin is an input only. This pin cannot be configured. 5. This pin contains an enabled internal schmitt-trigger. SRESET — ALT0 ALT1 ALT2 ALT3 SRESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. A18 5. This pin contains an enabled internal schmitt-trigger. Test/Debug Freescale Semiconductor TEST — ALT0 ALT1 ALT2 ALT3 TEST — — — — — — I — — — VDD_IO 2. This pin is an input only. D14 This pin cannot be configured. 4. This test pin must be tied to VSS. Pin Assignments 34 Table 2. MPC5125 Pin Multiplexing (continued) MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 4 l Pin Assignments 35 NOTES: 1 Pins controlled by the STD_PU_ST register have a Schmitt trigger input; pins controlled by the STD_PU register do not. Pins controlled by the IO_CONTROL_MEM register access their alternate function ALT3 by setting the IO_CONTROL_MEM[16BIT] bit. This setting applies to all pins controlled by IO_CONTROL_MEM. Pins not controlled by these registers are indicated with a “—”. 2 Offset from IOCONTROL_BASE (default is 0xFF40_A000). 3 Except where noted in the Notes column, ALT0 is the primary (default) function for each pin after reset. 4 Alternate functions are chosen by setting the values of the STD_PU[FUNCMUX] bitfields inside the I/O Control module.  – STD_PU[FUNCMUX] = 00  ALT0 (default) – STD_PU[FUNCMUX] = 01  ALT1 – STD_PU[FUNCMUX] = 10  ALT2 – STD_PU[FUNCMUX] = 11 ALT3  For selecting alternate functions, the STD_PU and STD_PU_ST registers function the same. When no function is available on a pin’s given ALTn function (value of STD_PU[FUNCMUX] ), it is shown as “—”. 5 Module included on the MCU. Freescale Semiconductor Pin Assignments 3.2.1 Power and Ground Supply Summary Table 3. MPC5125 324 TEPBGA Power/Ground Pin Name Function Description Voltage1 Package Pin Locations VDD Supply voltage — e300 core and peripheral logic 1.4 V J10, J11, J12, J13, K14, L9, L14, M9, M14, N14, P10, P11, P12, P13 VDD_IO Supply voltage — I/O buffers 3.3 V A14, B9, B12, B17, C5, C14, D3, F2, G4, H2, M2, R3, V3, W5, W15, AA4, AA9, AA12, AA14, AA16, AB18 VDD_IO_MEM Supply voltage — memory —2 B19, C21, D17, D19, G19, H21, P19, R21, T19, V19, W19, Y21, AB20 AVDD_FUSEWR Power 3.3 V D4 AVDD_CPLL Analog power 3.3 V D10 AVDD_SPLL Analog power 3.3 V A11 AVDD_OSC_TMPS Analog power 3.3 V C10 VBAT Power 3.3 V D8 AVSS_CPLL Analog ground 0V B11 AVSS_OSC_TMPS_SPLL Analog ground—Double-bonded AVSS_OSC_TMPS and AVSS_SPLL 0V B10 MVREF Analog input —Voltage reference for SSTL input pads —2 N19 MVTT0 Analog input —SSTL(DDR2) termination (ODT) voltage —2 W18 MVTT1 Analog input —SSTL(DDR2) termination (ODT) voltage —2 R19 MVTT2 Analog input —SSTL(DDR2) termination (ODT) voltage —2 M19 MVTT3 Analog input —SSTL(DDR2) termination (ODT) voltage —2 K19 VSS Ground 0V A1, A2, A22, B1, B7, D7, D12, F4, F21, J9, J14, K2, K[9:13], K21, L4, L[10:13], L19, M[10:13], N[9:13], N21, P2, P4, P9, P14, U2, U21, W8, W10, W12, W17, Y2, AA6, AA18, AB1, AB22 NOTES: 1 Nominal voltages. 2 Dependent on external memory type. See Table 3 NOTE This table indicates only the pins with a permanently enabled internal pullup, pulldown, or Schmitt trigger. Most digital I/O pins can be configured to enable internal pullup, pulldown, or Schmitt trigger. See the MPC5125 Reference Manual (MPC5125RM), “I/O Control” chapter. MPC5125 Microcontroller Data Sheet, Rev. 4 36 Freescale Semiconductor Electrical and Thermal Characteristics 4 Electrical and Thermal Characteristics 4.1 DC Electrical Characteristics 4.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5125 DC electrical characteristics. Table 4 gives the absolute maximum ratings. Table 4. Absolute Maximum Ratings1 Characteristic Sym Min Max Unit SpecID VDD 0.3 1.47 V D1.1 VDD_IO, VDD_IO_MEM 0.3 3.6 V D1.2 MVREF  0.3 3.6 V D1.15 MVTT  0.3 3.6 V D1.16 AVDD_SPLL 0.3 3.6 V D1.3 AVDD_OSC_TMPS 0.3 3.6 V D1.4 AVDD_CPLL – 0.3 3.6 V D1.5 VBAT  0.3 3.6 V D1.6 AVDD_FUSEWR  0.3 3.6 V D1.7 Input voltage (VDD_IO) Vin  0.3 VDD_IO + 0.3 V D1.9 Input voltage (VDD_IO_MEM) Vin  0.3 VDD_IO_MEM + 0.3 V D1.10 Input voltage (VBAT) Vin  0.3 VBAT + 0.3 V D1.11 Input voltage overshoot Vinos — 1 V D1.12 Input voltage undershoot Vinus — 1 V D1.13 Storage temperature range Tstg  55 150 oC D1.14 Supply voltage — e300 core and peripheral logic Supply voltage — I/O buffers Input reference voltage (DDR/DDR2) Termination Voltage (DDR2) Supply voltage — system APLL Supply voltage — system oscillator and temperature sensor Supply voltage — e300 APLL Supply voltage — RTC (hibernation) Supply voltage — FUSE programming NOTES: 1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage. 4.1.2 Recommended Operating Conditions Table 5 gives the recommended operating conditions. Table 5. Recommended Operating Conditions Characteristic Supply voltage — e300 core and peripheral logic State retention voltage — e300 core and peripheral logic 2 Sym Min1 Typ Max1 Unit SpecID VDD 1.33 1.4 1.47 V D2.1 — — V D2.2 1.08 MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 37 Electrical and Thermal Characteristics Table 5. Recommended Operating Conditions (continued) Characteristic Sym Min1 Typ Max1 Unit SpecID Supply voltage — standard I / O buffers VDD_IO 3.0 3.3 3.6 V D2.3 Supply voltage — memory I / O buffers (DDR) VDD_IO_MEM_DDR 2.3 2.5 2.7 V D2.4 VDD_IO_MEM_DDR2 1.7 1.8 1.9 V D2.5 Supply voltage — memory I/O buffers (DDR2, LPDDR, Mobile SDR) VDD_IO_MEM_LPDDR Supply voltage — memory I/O buffers (SDR) VDD_IO_MEM_SDR 3.0 3.3 3.6 V D2.19 Input reference voltage (DDR/DDR2) MVREF 0.49 × VDD_IO_MEM 0.50 VDD_IO_MEM 0.51 VDD_IO_MEM V D2.6 MVTT MVREF – 0.04 MVREF MVREF + 0.04 V D2.7 AVDD_SPLL 3.0 3.3 3.6 V D2.8 AVDD_OSC_TMPS 3.0 3.3 3.6 V D2.9 AVDD_CPLL 3.0 3.3 3.6 V D2.10 3.0 3.3 3.6 V D2.11 AVDD_FUSEWR 3.0 3.3 3.6 V D2.12 Input voltage — standard I/O buffers Vin 0 — VDD_IO V D2.14 Input voltage — memory I/O buffers (DDR) Vin_DDR 0 VDD_IO_ V D2.15 Input voltage — memory I/O buffers (DDR2) Vin_DDR2 V D2.16 Input voltage — memory I/O buffers (SDR) Vin_SDR V D2.20 Input voltage — memory I/O buffers (LPDDR) Vin_LPDDR V D2.18 oC D2.17 Termination voltage (DDR2) Supply voltage — system APLL Supply voltage — system oscillator and temperature sensor Supply voltage — e300 APLL Supply voltage — RTC (hibernation) Supply voltage — FUSE programming VBAT 3 — MEM_DDR 0 — VDD_IO_ MEM_DDR2 0 — VDD_IO_ MEM_SDR 0 — VDD_IO_ MEM_LPDDR Ambient operating temperature range TA –40 — +85 NOTES: 1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. 2 The State Retention voltage can be applied to VDD after the device is placed in deep-sleep mode. 3 VBAT should not be supplied by a battery of voltage less than 3.0 V. 4.1.3 DC Electrical Specifications Table 6 gives the DC electrical characteristics for the MPC5125 at recommended operating conditions. Table 6. DC Electrical Specifications Characteristic Condition Sym Min Max Unit SpecID Input high voltage Input type = TTL VDD_IO VIH 0.51VDD_IO — V D3.1 Input high voltage Input type = TTL VDD_IO_MEM_DDR VIH MVREF + 0.15 — V D3.2 MPC5125 Microcontroller Data Sheet, Rev. 4 38 Freescale Semiconductor Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) Characteristic Condition Sym Min Max Input high voltage Input type = TTL VDD_IO_MEM_DDR2 VIH MVREF + 0.125 — V D3.3 Input high voltage Input type = TTL VDD_IO_MEM_LPDDR VIH 0.7 VDD_IO_ — V D3.4 Input type = TTL VDD_IO_MEM_SDR VIH — V D3.33 Input type = Schmitt VDD_IO Input high voltage Unit SpecID MEM_LPDDR 0.7 VDD_IO_ MEM_SDR VIH 0.65 VDD_IO — V D3.5 Input high voltage mode1 SYS_XTALI crystal bypass mode2 CVIH Vxtal + 0.4 (VDD_IO / 2) + 0.4 — V D3.6 Input high voltage RTC_XTALI crystal mode3 bypass mode4 RVIH (VBAT / 5) + 0.5 (VBAT / 2) + 0.4 — V D3.7 Input low voltage Input type = TTL VDD_IO VIL — 0.42 VDD_IO V D3.8 Input low voltage Input type = TTL VDD_IO_MEM_DDR VIL — MVREF – 0.15 V D3.9 Input low voltage Input type = TTL VDD_IO_MEM_DDR2 VIL — MVREF – 0.125 V D3.10 Input low voltage Input type = TTL VDD_IO_MEM_LPDDR VIL — 0.3 VDD_IO_ V D3.11 Input low voltage Input type = TTL VDD_IO_MEM_SDR VIL — 0.3 VDD_IO_ V D3.34 Input low voltage Input type = Schmitt VDD_IO VIL — 0.35 VDD_IO V D3.12 Input low voltage SYS_XTALI crystal mode bypass mode CVIL — Vxtal – 0.4 × (VDD_IO/2) – 0.4 V D3.13 Input low voltage RTC_XTALI crystal mode bypass mode RVIL — (VBAT/5) – 0.5 (VBAT/2) – 0.4 V D3.14 Input leakage current Vin = 0 or VDD_IO/VDD_IO_MEM_DDR/2 (depending on input type)5 IIN 2.5 2.5 µA D3.15 Input leakage current SYS_XTAL_IN Vin = 0 or VDD_IO IIN — 20 µA D3.16 Input leakage current RTC_XTAL_IN Vin = 0 or VDD_IO IIN — 1.0 µA D3.17 Input current, pullup resistor6 PULLUP VDD_IO Vin = VIL IINpu 25 150 µA D3.18 Input current, pulldown resistor 8 PULLDOWN VDD_IO Vin = VIH IINpd 25 150 µA D3.19 Output high voltage IOH is driver dependent7 VDD_IO VOH 0.8 VDD_IO — V D3.20 VOHDDR 1.94 V D3.21 V D3.22 V D3.23 Input high voltage MEM_LPDDR MEM_SDR 7 Output high voltage IOH is driver dependent VDD_IO_MEM_DDR Output high voltage IOH is driver dependent7 VDD_IO_MEM_DDR2 VOHDDR2 VDD_IO_ MEM – 0.28 Output high voltage IOH is driver dependent7 VDD_IO_MEM_LPDDR VOHLPDD VDD_IO_ MEM – 0.28 R — — — MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 39 Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) Characteristic Condition Sym Output high voltage IOH is driver dependent7 VDD_IO_MEM_SDR Output low voltage IOL is driver dependent7 VDD_IO Min VOHSDR 0.8 × VDD_IO_MEM Max Unit SpecID — V D3.35 VOL — 0.2  VDD_IO V D3.24 Output low voltage 7 IOL is driver dependent VDD_IO_MEM_DDR VOLDDR — 0.36 V D3.25 Output low voltage IOL is driver dependent7 VDD_IO_MEM_DDR2 VOLDDR2 — 0.28 V D3.26 Output low voltage IOL is driver dependent7 VDD_IO_MEM_LPDDR VOLLPDD — 0.28 V D3.27 IOL is driver dependent7 VDD_IO_MEM_SDR VOLSDR — 0.2  VDD_IO_MEM V D3.36 Output low voltage R DC injection current per pin8 — ICS 1.0 1.0 mA D3.29 Input capacitance (digital pins) — Cin — 7 pF D3.30 Input capacitance (analog pins) — Cin — 10 pF D3.31 On-die termination (DDR2) — RODT 120 180  D3.32 NOTES: 1 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal – Vxtal  400 mV criteria has to be met for oscillator’s comparator to produce the output clock. 2 This parameter is meant for those who do not use quartz crystals or resonators, but instead use a signal generator clock to drive the clock in bypass mode. In this case, for the oscillator’s comparator to produce the output clock, drive only the EXTAL pin. Do not connect anything to any other oscillator pin. 3 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode to drive the clock. In that case, for the oscillator’s comparator to produce the output clock, drive one of the XTAL_IN or XTAL_OUT pins. Do not connect anything to the other oscillator pins. 4 This parameter is meant for those who do not use quartz crystals or resonators, but instead use a signal generator clock to drive the clock in bypass mode. In that case, for the oscillator’s comparator to produce the output clock, drive only the XTAL_IN pin. Do not connect anything to any other oscillator pin. 5 Leakage current is measured with output drivers disabled and with pullups and pulldowns inactive. 6 Pullup current is measured at V and pulldown current is measured at V . IL IH 7 See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 2. 8 All injection current is transferred to V DD_IO/VDD_IO_MEM. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. MPC5125 Microcontroller Data Sheet, Rev. 4 40 Freescale Semiconductor Electrical and Thermal Characteristics Table 7. General I/O Pads1 — Drive Current, Slew Rate Pad Type Supply Voltage Drive Select/Slew Rate Control Rise time max (ns) Fall time max (ns) Current Current Ioh (mA) Iol (mA) General IO VDD_IO = 3.3 V Configuration 3 (11) 1.4 1.6 Configuration 2 (10) 9.8 12 D3.42 Configuration 1 (01) 19 24 D3.43 Configuration 0 (00) 140 183 D3.44 35 35 SpecID D3.41 NOTES: 1 General I/O—rise and fall times at drive load 50 pF. Table 8. DDR I/O Pads1 — Drive Current, Slew Rate 1 Pad Type DDR Rising slew max (ns)2 Falling slew max (ns)3 VDD_IO_MEM = 2.5 V (DDR) Configuration 3 (011) 0.45 0.45 16.2 16.2 D3.45 VDD_IO_MEM = 1.8 V (LPDDR Configuration 0 (000) and SDR) Configuration 1 (001) 0.8 0.8 4.6 4.6 D3.46 8.1 8.1 D3.47 VDD_IO_MEM = 1.8 V (DDR2) Configuration 2 (010) 0.7 5.3 5.3 D3.48 13.4 13.4 D3.49 8 8 D3.50 Drive Select/ Slew Rate Control Supply Voltage 0.7 Configuration 6 (110) VDD_IO_MEM = 3.3 V (SDR) Configuration 7 (111) 0.45 0.45 Current Current SpecID Ioh (mA) Iol (mA) NOTES: 1 DDR—rise and fall times at 50  transmission line impedance terminated to MV TT (0.5 VDD_IO_MEM) + 4 pF load. 2 Rising slew rate measured between 0.5 × V – 450 mV and 0.5 × V DD_IO_MEM DD_IO_MEM + 50 mV for all modes. 3 Falling slew rate measured between 0.5 × V DD_IO_MEM + 50 mV and 0.5 × VDD_IO_MEM – 450 mV for all modes. 4.1.4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND or VDD ). Table 11 gives package thermal characteristics for this device. Table 9. ESD and Latch-Up Protection Characteristics Sym Rating Min Max Unit SpecID VHBM Human body model (HBM) — JEDEC JESD22-A114-B 2000 — V D4.1 VMM Machine model (MM) — JEDEC JESD22-A115 200 — V D4.2 VCDM Charge device model (CDM) — JEDEC JESD22-C101 250 — V D4.3 MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 41 Electrical and Thermal Characteristics 4.1.5 Power Dissipation Power dissipation of the MPC5125 is caused by three different components: • • • Dissipation of the internal or core digital logic (supplied by VDD) Dissipation of the analog circuitry (supplied by AVDD_SPLL and AVDD_CPLL) Dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO) Table 10 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins cannot be given in general, but must be calculated for each application case using the following formula: P IO = P IOint +  N  C  VDD_IO 2 f Eqn. 1 M where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency, and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5125 device must not exceed this value, which would cause the maximum junction temperature to be exceeded. Eqn. 2 P total = P core + P analog + P IO Table 10. Power Dissipation Core Power Supply (VDD_core)1 High-Performance Mode Unit SpecID e300 = 400 MHz, CSB = 200 MHz Operational2 620 mW D5.1 3 580 mW D5.3 Nap3 235 mW D5.2 Sleep 230 mW D5.4 Deep-sleep4 38 mW D5.5 µW D5.6 Doze 3 RTC Power Supply (VBAT) Hibernation 20 PLL/OSC Power Supplies (AVDD_SPLL, AVDD_CPLL, AVDD_OSC_TMPS)5 Operational 18 mW D5.7 Deep-sleep 55 µW D5.8 Unloaded I/O Power Supplies (VDD_IO, VDD_IO_MEM)6 VDD_IO VDD_IO_MEM Operational 180 40 mW D5.9 Deep-sleep 5 1 mW D5.10 NOTES: 1 Typical core power is measured at V DD_core = 1.4 V, TJ = 25 C. 2 Operational power is measured while running an entirely cache-resident program with floating-point multiplication instructions in parallel with DDR write operation. MPC5125 Microcontroller Data Sheet, Rev. 4 42 Freescale Semiconductor Electrical and Thermal Characteristics 3 Doze, Nap, and Sleep power are measured with the e300 core in Doze/Nap/Sleep mode; the system oscillator, system PLL, and core PLL active; and all other system modules inactive. 4 Deep-sleep power is measured with the e300 core in Sleep mode. The system oscillator, system PLL, core PLL, and other system modules are inactive. 5 PLL power is measured at AVDD_SPLL = AVDD_CPLL = AVDD_OSC_TMPS = 3.3 V, TJ = 25 C. 6 Unloaded typical I/O power is measured at V DD_IO = 3.3 V, VDD_MEM_IO = 1.8 V, TJ = 25 C. NOTE The maximum power depends on the supply voltage, process corner, junction temperature, and the concrete application and clock configurations. 4.1.6 Thermal Characteristics Table 11. Thermal Resistance Data1 Rating Conditions Sym Value Unit SpecID Thermal resistance junction-to-ambient natural convection2 Single layer board – 1s RJA 35 °C/W D6.1 Thermal resistance junction-to-ambient natural convection2 Four layer board – 2s2p RJA 25 °C/W D6.2 Thermal resistance junction-to-moving-air ambient2 @ 200 ft./min., single layer board – 1s RJMA 29 °C/W D6.3 Thermal resistance junction-to-moving-air ambient2 @ 200 ft./min., four layer board 2s2p RJMA 22 °C/W D6.4 — RJB 16 °C/W D6.5 — RJC 11 °C/W D6.6 JT 3 °C/W D6.7 Thermal resistance junction-to-board3 Thermal resistance junction-to-case Junction-to-package-top natural 4 convection5 Natural convection NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 4.1.6.1 Heat Dissipation An estimation of the chip-junction temperature, TJ, can be obtained from the following equation: TJ = TA + ( R JA  PD ) Eqn. 3 where: TA = ambient temperature for the package ( º C ) R JA = junction to ambient thermal resistance ( º C / W ) PD = power dissipation in package (W) MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 43 Electrical and Thermal Characteristics The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R JA = R JC + R CA Eqn. 4 where: R JA = junction to ambient thermal resistance ( º C / W ) R JC = junction to case thermal resistance ( º C / W ) R CA = case to ambient thermal resistance ( º C / W ) R JC is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient thermal resistance, R CA. For instance, you can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (  JT  PD ) Eqn. 5 where: TT = thermocouple temperature on top of package ( º C )  JT = thermal characterization parameter ( º C / W ) PD = power dissipation in package ( W ) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 4.2 Oscillator and PLL Electrical Characteristics The MPC5125 system requires a system-level clock input SYS_XTALI. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent real-time clock (RTC) system. The MPC5125 clock generation uses two phase-locked loop (PLL) blocks. MPC5125 Microcontroller Data Sheet, Rev. 4 44 Freescale Semiconductor Electrical and Thermal Characteristics • The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration. • 4.2.1 System Oscillator Electrical Characteristics Table 12. System Oscillator Electrical Characteristics Characteristic SYS_XTAL frequency Sym Min Typical Max Unit SpecID fsys_xtal 15.6 33.3 35.0 MHz O1.1 The system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference. t CYCLE t DUTY t DUTY t FALL t RISE CV IH VM SYS_XTAL_I CLK VM VM CV IL Figure 4. Timing Diagram — SYS_XTAL_IN Table 13. SYS_XTAL_IN Timing Sym Description t CYCLE SYS_XTALI cycle time1,2 Max Units SpecID 64.1 28.57 ns O.1.2 1 4 ns O.1.3 1 4 ns O.1.4 40 60 % O.1.5 time3 t RISE SYS_XTALI rise t FALL SYS_XTALI fall time4 t DUTY Min SYS_XTALI duty cycle ( measured at V M )5 NOTES: 1 The SYS_XTALI frequency and system PLL settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5125 Reference Manual (MPC5125RM). 2 The min/max cycle times are calculated using 1/f sys_xtal (MIN/MAX) where the fsys_xtal (MIN/MAX) (15.6 / 35 MHz) are taken from Table 12 (system oscillator electrical characteristics). 3 Rise time is measured from 20% of VDD to 80% of VDD. 4 Fall time is measured from 20% of VDD to 80% of VDD. 5 SYS_XTALI duty cycle is measured at V M. 4.2.2 RTC Oscillator Electrical Characteristics Table 14. RTC Oscillator Electrical Characteristics Characteristic RTC_XTAL frequency Sym Min Typical Max Unit SpecID frtc_xtal — 32.768 — kHz O2.1 MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 45 Electrical and Thermal Characteristics 4.2.3 System PLL Electrical Characteristics Table 15. System PLL Specifications Characteristic Sym Min Typical Max Unit SpecID fsys_xtal 16 33.3 67 MHz O3.1 tjitter — — 10 ps O3.2 fVCOsys 400 — 800 MHz O3.3 Sys PLL VCO output jitter (Dj), peak to peak / cycle fVCOjitterDj — — 40 ps O3.4 Sys PLL VCO output jitter (Rj), RMS 1 sigma fVCOjitterRj — — 12 ps O3.5 tlock1 — — 200 µs O3.6 tlock2 — — 170 µs O3.7 Sys PLL input clock frequency1 Sys PLL input clock jitter 2 Sys PLL VCO frequency1 Sys PLL relock time — after power up 3 Sys PLL relock time — when power was on 4 NOTES: 1 The SYS_XTAL frequency and PLL configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 2 This represents total input jitter — short term and long term combined. Two different types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the PLL to the internal clock circuitry. 3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. 4 PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently re-enabled during sleep modes. 4.2.4 e300 Core PLL Electrical Characteristics The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Table 16. e300 PLL Specifications Characteristic Sym Min Typical Max Unit SpecID fcore 200 — 400 MHz O4.1 fVCOcore 400 — 800 MHz O4.3 e300 PLL input clock frequency fCSB_CLK 50 — 200 MHz O4.4 e300 PLL input clock cycle time tCSB_CLK 5 — 20 ns O4.5 tlock — — 200 µs O4.6 e300 frequency1, 2 e300 PLL VCO frequency e300 PLL relock time 3 1 NOTES: 1 The frequency and e300 PLL configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in Table 17. 2 The following hard-coded relationship exists between fcore and fVCOcore: (fcore = fVCOcore). 3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable V DD and CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. MPC5125 Microcontroller Data Sheet, Rev. 4 46 Freescale Semiconductor Electrical and Thermal Characteristics 4.3 AC Electrical Characteristics 4.3.1 Overview The following list provides hyperlinks to the indicated timing specification sections. • AC Operating Frequency Data • DIU • Resets • CAN • SDRAM (DDR) • I2C • LPC • J1850 • NFC • PSC • FEC • GPIOs and Timers • USB ULPI • Fusebox • MMC/SD/SDIO Card Host Controller (SDHC) • IEEE 1149.1 (JTAG) AC test timing conditions: Unless otherwise noted, all test conditions are as follows: • • • • TA = –40 to 85 oC VDD = 1.33 to 1.47 V VDD_IO = 3.0 to 3.6 V Input conditions: All inputs: trise, tfall  1 ns Output Loading: All outputs: 50 pF 4.3.2 AC Operating Frequency Data Table 17 provides the operating frequency information for the MPC5125. Table 17. Clock Frequencies Min Max Units SpecID e300 Processor Core 200 400 MHz A1.1 SDRAM clock 50 200 MHz A1.2 CSB bus clock 50 200 MHz A1.3 IP bus clock 8.3 66 MHz A1.4 LPC clock 2.08 66 MHz A1.6 NFC clock 3.13 50 MHz A1.7 DIU clock 0.78 66 MHz A1.8 SDHC clock 0.78 50 MHz A1.9 CLKx 0.78 66 MHZ A1.10 NOTES: MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 47 Electrical and Thermal Characteristics 1. The SYS_XTAL_IN frequency, Sys PLL, and Core PLL settings must be chosen so that the resulting e300 clk, csb_clk, and MCK frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The values are valid for the user-operation mode. There can be deviations for test modes. 3. When selecting the peripheral clock frequencies, care needs to be taken about requirements for baud rates and minimum frequency limitation. 4.The DDR data rate is 2x the DDR memory bus frequency.  SYS_XTAL_IN is the input clock multiplied by the system phase-locked loop (Sys PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the clocks for the peripherals.The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word, which is loaded at power-on reset.  See the MPC5125 Reference Manual (MPC5125RM), for more information on the clock subsystem. 4.3.3 Resets The MPC5125 has three reset pins: • • • PORESET — Power-on reset HRESET — Hard reset SRESET — Software reset These signals are asynchronous I / O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5125 inputs, as specified in Section 4.1, “DC Electrical Characteristics.” As long as VDD is not stable the HRESET output is not stable. Table 18. Reset Rise / Fall Timing Description Min Max Unit SpecID PORESET fall time — 1 ms A3.4 PORESET rise time — 1 ms A3.5 2,3 — 1 ms A3.6 HRESET rise time — 1 ms A3.7 SRESET fall time — 1 ms A3.8 SRESET rise time — 1 ms A3.9 1 HRESET fall time NOTES: 1 Make sure that the PORESET does not carry any glitches. The MPC5125 has no filter to prevent them from getting into the chip. 2 HRESET and SRESET must have a monotonous rise time. 3 The assertion of HRESET becomes active at power-on reset without any SYS_XTAL clock. The timing relationship can be seen in the following figures. MPC5125 Microcontroller Data Sheet, Rev. 4 48 Freescale Semiconductor Electrical and Thermal Characteristics XTALI CLOCK PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF tEXEC RST_CONF[31:0] ADDR[31:0] tH_POR_CONF Figure 5. Power-Up Behavior XTALI CLOCK tPORHold PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF tEXEC RST_CONF[31:0] ADDR[31:0] tH_POR_CONF Figure 6. Power-On Reset Behavior MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 49 Electrical and Thermal Characteristics XTALI CLOCK PORESET tHRHOLD tHRVAL HRESET tSRVAL SRESET tHR_SR_Delay tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF Figure 7. HRESET Behavior XTALI CLOCK PORESET HRESET tSRHOLD tSRMIN SRESET tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF Figure 8. SRESET Behavior Table 19. Reset Timing Symbol tPORHOLD Description Time PORESET must be held low before a qualified reset occurs. Value (XTALI CLOCK) SpecID 4 cycles A3.10 tHRVAL Time HRESET is asserted after a qualified reset occurs. tSRVAL Time SRESET is asserted after assertion of HRESET. 21 cycles A3.12 tEXEC Time between SRESET assertion and first core instruction fetch. 4 cycles A3.13 Reset configuration setup time before assertion of PORESET. 1 cycle A3.14 tS_POR_CONF 26810 cycles1 A3.11 MPC5125 Microcontroller Data Sheet, Rev. 4 50 Freescale Semiconductor Electrical and Thermal Characteristics Table 19. Reset Timing (continued) Symbol Description Value (XTALI CLOCK) SpecID tH_POR_CONF Reset configuration hold time after assertion of PORESET. 1 cycle A3.15 tHR_SR_DELAY Time from falling edge of HRESET to falling edge of SRESET. 4 cycles A3.16 tHRHOLD Time HRESET must be held low before a qualified reset occurs. 4 cycles A3.17 tSRHOLD Time SRESET must be held low before a qualified reset occurs. 4 cycles A3.18 Time SRESET is asserted after it has been qualified. 1 cycles A3.19 tSRMIN NOTES: 1 The timings will change when using the PLL lock detection circuit. 4.3.4 External Interrupts The MPC5125 provides three different kinds of external interrupts: • • • IRQ interrupts GPIO interrupts with simple interrupt capability (not available in power-down mode) Wakeup interrupts Table 20. IPIC Input AC Timing Specifications Descriptions IPIC inputs — minimum pulse width Symbol Min Unit Spec ID tPICWID 2T ns A4.1 IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge-triggered mode. 4.3.5 SDRAM (DDR) The MPC5125 memory controller supports these types of DDR devices: • • • • DDR-1 (SSTL_2 class II interface) DDR-2 (SSTL_18 interface) LPDDR (1.8V I/O supply voltage) SDR D-RAM JEDEC standards define the minimum set of requirements for compliant memory devices: • • • JEDEC standard, DDR2 SDRAM specification, JESD79-2C, May 2006 JEDEC standard, Double Data Rate (DDR) SDRAM specification, JESD79E, May 2005 JEDEC standard, Low Power Double Data Rate (LPDDR) SDRAM specification, JESD79-4, May 2006 The MPC5125 supports the configuration of two output drive strengths for DDR2 and LPDDR: • • Full drive strength Half drive strength (intended for lighter loads or point-to-point environments) The MPC5125 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device. This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in Section 4.1, “DC Electrical Characteristics.” MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 51 Electrical and Thermal Characteristics 4.3.5.1 DDR SDRAM AC Timing Specifications Table 21. DDR SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of 5% Parameter Clock cycle time, CL = x MCK AC differential crosspoint voltage Symbol Min Max tCK 6000 — ps (VDD_IO_MEM 0.5)– 0.15 (VDD_IO_MEM  0.5) + 0.15 VOX-AC CK HIGH pulse width Unit Notes SpecID 0.47 tCH 0.53 A5.1 V 1 A5.2 tCK 1,3 A5.3 A5.4 tCL 0.47 0.53 tCK 1,3 tDQSS 0.25 0.25 tCK 2,3 A5.5 Address and control output setup time relative to MCK rising edge tOS(base) tCK/2 – 1000 — ps 2,3 A5.6 Address and control output hold time relative to MCK rising edge tOH(base) tCK/2 – 1000 — ps 2,3 A5.7 DQ and DM output setup time relative to DQS tDS1(base) tCK/4 – 750 — ps 2,3 A5.8 DQ and DM output hold time relative to DQS tDH1(base) tCK/4 – 750 — ps 2,3 A5.9 DQS-DQ skew for DQS and associated DQ inputs tDQSQ – (tCK/4 – 600) tCK/4 – 600 ps 3 A5.10 DQS window position related to CAS read command tDQSEN 2tCK + 1500 3tCK – 1000 ps 1,2,3,4, CK LOW pulse width Skew between MCK and DQS transitions A5.11 5 NOTES: 1 Measured with clock pin loaded with differential 100  termination resistor. 2 Measured with all outputs except the clock loaded with 50  termination resistor to V DD_IO_MEM/2. 3 All transitions measured at mid-supply (V /2). DD_IO_MEM 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5 The window position is given for t DQSEN = 2.0 tCK (RDLY = 2, HALF DQS DLY = QUART DQS DLY = 0) with CL = 3 DDR SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. 4.3.5.2 MobileDDR/LPDDR SDRAM AC Timing Specifications Table 22. MobileDDR/LPDDR SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of 5% Parameter Clock cycle time, CL = x MCK AC differential crosspoint voltage CK HIGH pulse width CK LOW pulse width Skew between MCK and DQS transitions Address and control output setup time relative to MCK rising edge Symbol Min Max tCK 6000 — VOX-AC tCH Unit Notes SpecID ps (VDD_IO_MEM 0.5) – 0.1 (VDD_IO_MEM  0.5) + 0.1 0.47 0.53 A5.1 V 1 A5.2 tCK 1,3 A5.3 A5.4 tCL 0.47 0.53 tCK 1,3 tDQSS 0.25 0.25 tCK 2,3 A5.5 tOS(base) tCK/2 – 1000 — ps 2,3 A5.6 MPC5125 Microcontroller Data Sheet, Rev. 4 52 Freescale Semiconductor Electrical and Thermal Characteristics Table 22. MobileDDR/LPDDR SDRAM Timing Specifications (continued) At recommended operating conditions with VDD_IO_MEM of 5% Parameter Symbol Min Max tOH(base) tCK/2 – 1000 — ps 2,3 A5.7 DQ and DM output setup time relative to tDS1(base) DQS tCK/4 – 750 — ps 2,3 A5.8 DQ and DM output hold time relative to DQS tDH1(base) tCK/4 – 750 — ps 2,3 A5.9 DQS-DQ skew for DQS and associated DQ inputs tDQSQ – (tCK/4 – 600) tCK/4 – 600 ps 3 A5.10 DQS window position related to CAS read command tDQSEN 2tCK – 500 3tCK – 1000 ps 1,2,3,4,5 A5.11 Address and control output hold time relative to MCK rising edge Unit Notes SpecID NOTES: 1 Measured with clock pin loaded with differential 100  termination resistor. 2 Measured with all outputs except the clock loaded with 50  termination resistor to V DD_IO_MEM/2. 3 All transitions measured at mid-supply (V /2). DD_IO_MEM 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5 The window position is given for t DQSEN = 2.0 tCK (RDLY = 2, HALF DQS DLY = QUART DQS DLY = 0) with CL = 3 MobileDDR/LPDDR SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. 4.3.5.3 DDR2 SDRAM AC Timing Specifications Table 23. DDR2 (DDR2-400) SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of ±5% Parameter Clock cycle time, CL = x MCK AC differential crosspoint voltage Symbol Min Max tCK 5000 — VOX-AC (VDD_IO_MEM 0.5) – 0.1 (VDD_IO_MEM 0.5) + 0.1 Unit Notes SpecID ps A5.1 V 1 A5.2 A5.3 CK HIGH pulse width tCH 0.47 0.53 tCK 1,3 CK LOW pulse width tCL 0.47 0.53 tCK 1,3 A5.4 tDQSS 0.25 0.25 tCK 2,3 A5.5 A5.6 Skew between MCK and DQS transitions Address and control output setup time relative to MCK rising edge tOS(base) tCK/2750 — ps 2,3 Address and control output hold time relative to MCK rising edge tOH(base) tCK/2750 — ps 2,3 A5.7 DQ and DM output setup time relative to tDS1(base) DQS tCK/4500 — ps 2,3 A5.8 DQ and DM output hold time relative to DQS tDH1(base) tCK/4500 — ps 2,3 A5.9 DQS-DQ skew for DQS and associated DQ inputs tDQSQ – (tCK/4 – 600) tCK/4600 ps 3 A5.10 DQS window position related to CAS read command tDQSEN 2.5tCK 3tCK + 1500 ps 1,2,3,4, A5.11 5 MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 53 Electrical and Thermal Characteristics NOTES: 1 Measured with clock pin loaded with differential 100  termination resistor. 2 Measured with all outputs except the clock loaded with 50  termination resistor to VDD_IO_MEM/2. 3 All transitions measured at mid-supply (VDD_IO_MEM/2). 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5 The window position is given for tDQSEN = 2.5 tCK (RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0) with CL = 3 DDR2 SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. 4.3.5.4 SDR SDRAM AC Timing Specifications Table 24. SDR SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of 5% Parameter Symbol Min Max tCK 7500 — Clock cycle time, CL = x CK HIGH pulse width tCH 0.43 0.57 Unit Notes SpecID ps A5.1 tCK 1,3 A5.3 A5.4 0.43 0.57 tCK 1,3 Address, control, and data output setup time relative tOS(base) to MCK rising edge tCK/2 – 1000 — ps 2,3 A5.6 Address, control, and data output hold time relative to tOH(base) MCK rising edge tCK/2 – 1000 — ps 2,3 A5.7 CK LOW pulse width tCL Input data set-up time, relative to MCK tIS 1000 — ps 3 A5.15 Input data hold time, relative to MCK tIH 1000 — ps 3 A5.16 NOTES: 1 Measured with clock pin loaded with 50  termination resistor to mid-supply. 2 Measured with all outputs except the clock loaded with 50  termination resistor to V DD_IO_MEM/2. 3 All transitions measured at mid-supply (V DD_IO_MEM/2). NOTE To achieve better timing, balance the loading of DQS as MCK although DQS is not used in SDR mode. Figure 9 shows the DDR SDRAM write timing. tCL tCH MCK tCK DQS tDQSS DQ, DM(out) tDS tDH Figure 9. DDR Write Timing MPC5125 Microcontroller Data Sheet, Rev. 4 54 Freescale Semiconductor Electrical and Thermal Characteristics Figure 10 and Figure 11 show the DDR SDRAM read timing. DQS(in) Any DQ(in) tDQSQ tDQSQ Figure 10. DDR Read Timing, DQ vs DQS MCK Command Address tOS tOH DQS(in) tDQSEN (MIN) tDQSEN (MAX) Figure 11. DDR Read Timing, DQSEN Figure 12 shows the SDR AC timing. MCK Output tOS tOH Input tIS tIH Figure 12. SDR AC Timing Figure 13 provides the AC test load for the DDR bus. Output Z0 = 50  RL= 50  VDD_IO_MEM / 2 Figure 13. DDR AC Test Load MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 55 Electrical and Thermal Characteristics 4.3.6 LPC The local-plus bus is the external bus interface of the MPC5125. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed and MUXed. The reference clock is the LPC CLK. The maximum bus frequency is 66 MHz. Definition of terms: WS = Wait state DC = Dead cycle HC = Hold cycle DS = Data size in bytes BBT =Burst bytes per transfer AL = Address latch enable length ALT = Chip select/Address Latch Timing tLPCck = LPC clock period Table 25. LPC Timing Sym Description tOD CS[x], ADDR, R/W, TSIZ, DATA (wr), TS, OE valid after LPC CLK (Output delay related to LPC CLK) Min Max Units SpecID 0 5 ns A7.1 (2 + WS) tLPCck (2 + WS)  tLPCck ns A7.2 t1 Non-burst CS[x] pulse width t2 ADDR, R/W, TSIZ, DATA (wr) valid before CS[x] assertion tLPCcktOD tLPCck + tOD ns A7.3 t3 OE assertion after CS[x] assertion tLPCcktOD tLPCck + tOD ns A7.4 t4 ADDR, R/W, TSIZ, data (wr) hold after CS[x] negation tLPCcktOD (HC + 1)  tLPCck + tOD ns A7.5 t5 TS pulse width tLPCck tLPCck ns A7.6 t6 DATA (rd) setup before LPC CLK 5 — ns A7.7 t7 DATA (rd) input hold 0 (DC + 1)  tLPCck ns A7.8 t8 Read burst CS[x] pulse width (2 + WS + BBT/DS)  tLPCck (2 +WS + BBT/DS)  tLPCck ns A7.9 t9 Burst ACK pulse width (BBT/DS) tLPCck (BBT/DS)tLPCck ns A7.10 t10 Burst DATA (rd) input hold 0 — ns A7.11 (2+WS) tLPCck (2+WS) tLPCck ns A7.12 ns A7.13 t11 Read burst ACK assertion after CS[x] assertion t12 Non-MUXed write burst CS[x] pulse width (2.5 + WS + BBT/DS) tLPCck (2.5 + WS + BBT/DS) tLPCck t13 Write burst ADDR, R/W, TSIZ, DATA (wr) hold after CS[x] negation 0.5 tLPCck – tOD (HC + 0.5) tLPCck + tOD ns A7.14 t14 Write burst ACK assertion after CS[x] assertion (2.5 + WS) tLPCck – tOD (2.5 + WS) tLPCck + tOD ns A7.15 tLPCck – tOD — ns A7.16 0.5 tLPCck – tOD 0.5 tLPCck + tOD ns A7.17 AL 2 tLPCck – tOD AL 2 tLPCck ns A7.18 AL tLPCck AL tLPCck ns A7.19 t15 Write burst DATA valid t16 Non-MUXed mode: asynchronous write burst ADDR valid before write DATA valid t17 MUXed mode: ADDR cycle t18 MUXed mode: ALE cycle MPC5125 Microcontroller Data Sheet, Rev. 4 56 Freescale Semiconductor Electrical and Thermal Characteristics Table 25. LPC Timing (continued) Sym Description Min Max t19 Non-MUXed mode page burst: ADDR cycle tLPCck – tOD tLPCck ns A7.20 t20 Non-MUXed mode page burst: burst DATA (rd) input setup before next ADDR cycle tOD + t6 — ns A7.21 t21 Non-MUXed mode page burst: burst DATA (rd) input hold after next ADDR cycle 0 — ns A7.22 t22 MUXed mode: non-burst CS[x] pulse width (ALT × (AL 2) + WS) ×tLPCck (ALT × (AL 2) + WS) ×tLPCck ns A7.23 t23 MUXed mode: read-burst CS[x] pulse width (ALT × (AL 2) + WS) + BBT/DS) ×tLPCck (ALT × (AL 2) + WS) + BBT/DS) ×tLPCck ns A7.23 t24 MUXed mode: write-burst CS[x] pulse width (ALT × (AL 2) + 2.5 WS) + BBT/DS)×tLPCck (ALT × (AL 2) + 2.5 WS) + BBT/DS)×tLPCck ns A7.23 4.3.6.1 Units SpecID Non-MUXed Mode 4.3.6.1.1 Non-MUXed Non-Burst Mode tLPCck LPC CLK t1 CS[x] ADDR t2 t3 t4 OE R/W DATA (wr) t6 t7 DATA (rd) ACK t5 TS TSIZ[1:0] Figure 14. Timing Diagram — Non-MUXed non-Burst Mode MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 57 Electrical and Thermal Characteristics NOTE ACK is asynchronous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. 4.3.6.1.2 Non-MUXed Synchronous Read Burst Mode LPC_CLK t8 CS[x] t2 t4 Valid Address ADDR t5 TS t3 OE R/W t10 t6 t7 DATA (rd) t11 t9 ACK Figure 15. Timing Diagram — Non-MUXed Synchronous Read Burst Mode 4.3.6.1.3 Non-MUXed Synchronous Write Burst Mode LPC_CLK CS[x] t12 t13 t2 Valid Address ADDR t5 TS R/W t15 t15 DATA (wr) t9 ACK t14 Figure 16. Timing Diagram — Non-MUXed Synchronous Write Burst MPC5125 Microcontroller Data Sheet, Rev. 4 58 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.6.1.4 Non-MUXed Asynchronous Read Burst Mode (Page Mode) LPC_CLK t8 CS[x] t2 t4 Valid Address (Page address) ADDR[31:n+1] t19 Valid Address ADDR[n:0] Valid Address t5 TS t3 OE R/W t20 t21 t6 t10 t7 DATA (rd) t11 t9 ACK Figure 17. Timing Diagram — Non-MUXed Asynchronous Read Burst 4.3.6.1.5 Non-MUXed Asynchronous Write Burst Mode LPC_CLK t12 CS[x] t2 t13 Valid Address (Page address) ADDR[31:n+1] Valid Address ADDR[n:0] Valid Address t16 t5 TS R/W t15 t15 DATA (wr) t9 ACK t14 Figure 18. Timing Diagram — Non-MUXed Asynchronous Write Burst MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 59 Electrical and Thermal Characteristics 4.3.6.2 MUXed Mode 4.3.6.2.1 MUXed Non-Burst Mode LPC_CLK t17 AD[31:0] (wr) Address Valid Write Data t6 AD[31:0] (rd) t7 Address t4 R/W t18 ALE t5 TS t22 CS[x] t3 OE ACK TSIZ[1:0] Figure 19. Timing Diagram — MUXed non-Burst Mode NOTE ACK is asynchronous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. MPC5125 Microcontroller Data Sheet, Rev. 4 60 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.6.2.2 MUXed Synchronous Read Burst Mode LPC_CLK t6 t17 AD[31:0] (rd) t7 t10 Address t18 ALE t5 TS t23 CS[x] t3 OE R/W t9 t11 ACK Figure 20. Timing Diagram — MUXed Synchronous Read Burst 4.3.6.2.3 MUXed Synchronous Write Burst Mode LPC_CLK t15 t17 AD[31:0] (wr) t15 t13 Address t18 ALE t5 TS t24 CS[x] R/W t14 t9 ACK Figure 21. Timing Diagram — MUXed Synchronous Write Burst MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 61 Electrical and Thermal Characteristics 4.3.7 NFC The NAND flash controller (NFC) implements the interface to standard NAND flash memory devices. This section describes the timing parameters of the NFC. TH is the flash clock high time, TL is flash clock low time, where TH = 5 × NFC_RATIO_H / 8 (ns) Eqn. 6 TL = 5 × NFC_RATIO_L / 8 (ns) Eqn. 7 Refer to the MPC5125 Reference Manual (MPC5125RM) for more information about NFC_RATIO_H and NFC_RATIO_L. Table 26. NFC Target Timing Characteristics Timing Parameter Description Min. value Max. value Unit SpecID tCLS NFC_CLE setup time 2TH + TL – 1 — ns A8.1 tCLH NFC_CLE hold time TH + TL – 1 — ns A8.2 tCS NFC_CE[3:0] setup time 2TH + TL – 1 — ns A8.3 tCH NFC_CE[3:0] hold time TH + TL — ns A8.4 tWP NFC_WP pulse width TL – 1 — ns A8.5 tALS NFC_ALE setup time 2TH + TL — ns A8.6 tALH NFC_ALE hold time TH + TL — ns A8.7 tDS Data setup time TL – 1 — ns A8.8 tDH Data hold time TH – 1 — ns A8.9 tWC Write cycle time TH + TL – 1 — ns A8.10 tWH NFC_WE hold time TH – 1 — ns A8.11 tRR Ready to NFC_RE low 4TH + 3TL + 90 — ns A8.12 tRP NFC_RE pulse width TL + 1 — ns A8.13 tRC READ cycle time TL + TH – 1 — ns A8.14 tREH NFC_RE high hold time TH – 1 — ns A8.15 6 — ns A8.16 tIS Data input setup time MPC5125 Microcontroller Data Sheet, Rev. 4 62 Freescale Semiconductor Electrical and Thermal Characteristics NFC_CLE tCLS tCLH tCS tCH NFC_CE[3:0] tWP NFC_WE command NFIO[7:0] tDS tDH Figure 22. Command Latch Cycle Timing NFC_ALE tALS tALH tCS tCH NFC_CE[3:0] tWP NFC_WE address NFIO[7:0] tDS tDH Figure 23. Address Latch Cycle Timing tCS tWC tCH NFC_CE[3:0] tWP tWH NFC_WE data data NFIO[15:0] tDS data tDH Figure 24. Write Data Latch Timing MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 63 Electrical and Thermal Characteristics tRC tCH NFC_CE[3:0] tRP tREH NFC_RE data NFIO[15:0] data data tIS tRR NFC_RB Figure 25. Read Data Latch Timing in Non-Fast Mode tRC tCH NFC_CE[3:0] tRP tREH NFC_RE data NFIO[15:0] data data tIS tRR NFC_RB Figure 26. Read Data Latch Timing in Fast Mode 4.3.8 FEC AC test timing conditions: • Output Loading All Outputs: 25 pF Table 27. MII Rx Signal Timing Sym Description Min Max Unit SpecID t1 RXD [ 3 : 0 ], RX_DV, RX_ER to RX_CLK setup 5 — ns A11.1 t2 RX_CLK to RXD [ 3 : 0 ], RX_DV, RX_ER hold 5 — ns A11.2 t3 RX_CLK pulse width high 35% 65% RX_CLK period1 A11.3 65% period1 A11.4 t4 RX_CLK pulse width low 35% RX_CLK NOTES: 1 RX_CLK shall have a frequency of 25% of the data rate of the received signal. See the IEEE 802.3 specification. MPC5125 Microcontroller Data Sheet, Rev. 4 64 Freescale Semiconductor Electrical and Thermal Characteristics Table 28. RMII Rx Signal Timing Sym Description Min Max Unit SpecID A11.5 t5 RXD [ 1 : 0 ], RX_DV, RX_ER to TX_CLK setup 4 — ns t6 TX_CLK to RXD [ 1 : 0 ], RX_DV, RX_ER hold 2 — ns t7 t8 TX_CLK pulse width high 35% TX_CLK pulse width low 65% 35% 65% A11.6 TX_CLK period 1 A11.7 TX_CLK period 1 A11.8 NOTES: 1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification. t3, t7 REF_CLK (Input) t4, t8 RXD[3:0] (inputs) RX_DV RX_ER t1. t5 t2. t6 REF_CLK is TX_CLK in RMII mode, and is RX_CLK in non-RMII mode Figure 27. Ethernet Timing Diagram — MII and RMII Rx Signal Table 29. MII Tx Signal Timing Sym Description Min Max Unit SpecID t9 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER invalid 3 — ns A11.9 t10 TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER valid — 25 ns A11.10 t11 t12 TX_CLK pulse width high 35% TX_CLK pulse width low 35% 65% 65% TX_CLK Period1 A11.11 TX_CLK Period1 A11.12 NOTES: 1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, for example, a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 specification. Table 30. RMII Tx Signal Timing Sym Description Min Max Unit SpecID t13 TX_CLK rising edge to TXD [ 1 : 0 ], TX_EN, TX_ER invalid 3 — ns A11.13 t14 TX_CLK rising edge to TXD [ 1 : 0 ], TX_EN, TX_ER valid — 14 ns A11.14 Period1 A11.15 A11.16 t15 TX_CLK pulse width high 35% 65% TX_CLK t16 TX_CLK pulse width low 35% 65% TX_CLK Period1 NOTES: 1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 65 Electrical and Thermal Characteristics t11, t15 TX_CLK (Input) t9, t13 t12, t16 TXD[3:0] (Outputs) TX_EN TX_ER t10, t14 Figure 28. Ethernet Timing Diagram — MII Tx Signal Table 31. MII Async Signal Timing Sym t17 Description CRS, COL minimum pulse width Min Max Unit SpecID 1.5 — TX_CLK Period A11.17 CRS, COL t17 Figure 29. Ethernet Timing Diagram — MII Async Table 32. MII Serial Management Channel Signal Timing Sym Description Min Max Unit SpecID t18 MDC falling edge to MDIO output delay 0 25 ns A11.18 t19 MDIO ( input ) to MDC rising edge setup 10 — ns A11.19 t20 MDIO ( input ) to MDC rising edge hold t21 t22 t23 0 — ns A11.20 MDC pulse width high1 160 — ns A11.21 MDC pulse width low1 160 — ns A11.22 400 — ns A11.23 MDC period2 NOTES: 1 MDC is generated by the MPC5125 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5125 Reference Manual (MPC5125RM). 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5125 Reference Manual (MPC5125RM). MPC5125 Microcontroller Data Sheet, Rev. 4 66 Freescale Semiconductor Electrical and Thermal Characteristics t21 t22 MDC (Output) t23 t18 MDIO (Output) MDIO (Input) t19 t20 Figure 30. Ethernet Timing Diagram — MII Serial Management 4.3.9 USB ULPI This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004. Clock TSC THC TSD THD Control Out (stp) Data Out (8-bit) TDC TDC Control In (dir,nxt) TDD Data In (8-bit) Figure 31. ULPI Timing Diagram Table 33. Timing Specifications — USB Output Line 1 Sym Min Max Units SpecID 15 — ns A12.1 TSC, TSD Setup time (control in, 8-bit data in) — 6.0 ns A12.2 THC, THD Hold time (control in, 8-bit data in) 0.0 — ns A12.3 TDC, TDD Output delay (control out, 8-bit data out) — 9.0 ns A12.4 TCK Description Clock period NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 67 Electrical and Thermal Characteristics 4.3.10 MMC/SD/SDIO Card Host Controller (SDHC) Figure 32 depicts the timings of the SDHC. SD4 SD2 SD1 SD5 MMCx_CLK SD3 MMCx_CMD MMCx_DAT_0 Output from SDHC to card MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD6 MMCx_CMD MMCx_DAT_0 Input from card to SDHC MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD7 SD8 Figure 32. SDHC Timing Diagram Table 34 lists the timing parameters. . Table 34. MMC/SD Interface Timing Parameters ID Parameter Symbols Min Max Unit SpecID Card Input Clock Clock frequency (low speed) fPP1 0 400 kHz A14.1 Clock frequency (SD/SDIO full speed/high speed) fPP2 0 25/50 MHz A14.2 Clock frequency (MMC full speed/high speed) fPP3 0 20/52 MHz A14.3 Clock frequency (identification mode) fOD4 100 400 kHz A14.4 SD2 Clock low time (full speed/high speed) tWL 10/7 ns A14.5 SD3 Clock high time (full speed/high speed) tWH 10/7 ns A14.6 SD4 Clock rise time (full speed/high speed) tTLH 10/3 ns A14.7 SD5 Clock fall time (full speed/high speed) tTHL 10/3 ns A14.8 TH + 3 ns A14.9 SD1 SDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SDHC output delay tOD TH – 3 5 SDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD7 SDHC input setup time tISU 2.5 ns A14.10 SD8 SDHC input hold time tIH 2.5 ns A14.11 NOTES: 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0–20 MHz. MPC5125 Microcontroller Data Sheet, Rev. 4 68 Freescale Semiconductor Electrical and Thermal Characteristics 4 5 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V. Suggested Clock Period = T, CLK_DIVIDER (in SDHC Clock Rate register) = D, then TH = [(D + 1)/2] / (D + 1)T where [] is round. 4.3.11 DIU The DIU is a display controller designed to manage the TFT LCD display. 4.3.11.1 Interface to TFT LCD Panels, Functional Description Figure 33 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: • • • • DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, DIU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type. DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse. DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse. DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. DIU_VSYNC DIU_HSYNC LINE 1 LINE 3 LINE 2 LINE 4 LINE n-1 LINE n DIU_HSYNC DIU_DE 1 2 3 m-1 m DIU_CLK DIU_LD[23:0] Figure 33. Interface Timing Diagram for TFT LCD Panels 4.3.11.2 Interface to TFT LCD Panels, Electrical Characteristics Figure 34 depicts the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal (meaning the data and sync signals change at its rising edge) and active-high polarity of the DIU_HSYNC, DIU_VSYNC, and DIU_DE signal. Signal polarity of DIU_HSYNC and DIU_VSYNC are selectable via the SYN_POL register, whether active-high or active-low. The default is active-high. The DIU_DE signal is always active-high. Also, pixel clock inversion and a flexible programmable pixel clock delay are also supported, programmed via the DIU Clock Config register (DCCR) in the system clock module. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 69 Electrical and Thermal Characteristics tHSP Start of line tPWH tFPH tSW tBPH tPCP DIU_CLK DIU_LD[23:0] Invalid Data 11 2 DELTA_X Invalid Data 3 DIU_HSYNC DIU_DE Figure 34. TFT LCD Interface Timing Diagram — Horizontal Sync Pulse Figure 35 depicts the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown in the diagram are programmable. tVSP Start of Frame tSH tBPV tPWV tFPV tHSP DIU_HSYNC DIU_LD[23:0] (Line Data) Invalid Data 11 2 3 DELTA_Y Invalid Data DIU_VSYNC DIU_DE Figure 35. TFT LCD Interface Timing Diagram — Vertical Sync Pulse Table 35 shows timing parameters of signals. Table 35. LCD Interface Timing Parameters — Pixel Level Sym Description Value Unit SpecID tPCP Display Pixel Clock Period 151 ns A15.1 tPWH HSYNC Pulse Width PW_H  tPCP ns A15.2 tBPH HSYNC Back Porch Width BP_H  tPCP ns A15.3 MPC5125 Microcontroller Data Sheet, Rev. 4 70 Freescale Semiconductor Electrical and Thermal Characteristics Table 35. LCD Interface Timing Parameters — Pixel Level Sym Description Value Unit SpecID tFPH HSYNC Front Porch Width FP_H  tPCP ns A15.4 tSW Screen Width DELTA_X  tPCP ns A15.5 tHSP HSYNC (Line) Period (PW_H + BP_H + DELTA_X + FP_H)  tPCP ns A15.6 tPWV VSYNC Pulse Width PW_V  tHSP ns A15.7 tBPV VSYNC Back Porch Width BP_V  tHSP ns A15.8 tFPV VSYNC Front Porch Width FP_V  tHSP ns A15.9 tSH Screen Height DELTA_Y  tHSP ns A15.10 tVSP VSYNC (Frame) Period (PW_V + BP_V + DELTA_Y + FP_H)  tHSP ns A15.11 NOTES: 1 Display interface pixel clock period immediate value (in nanoseconds). The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H parameters are programmed via the HSYN_PARA register; and the PW_V, BP_V, and FP_V parameters are programmed via the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions of these parameters. Figure 36 depicts the synchronous display interface timing for access level, and Table 36 lists the timing parameters. tCHD tCSU tDHD tDSU DIU_HSYNC DIU_VSYNC DIU_DE DIU_CLK tCKH tCKL DIU_LD[23:0] Figure 36. LCD Interface Timing Diagram — Access Level Table 36. LCD Interface Timing Parameters — Access Level Parameter Description Min Typ Max Unit SpecID tCKH LCD interface pixel clock high time tPCP  0.4 tPCP  0.5 tPCP  0.6 ns A15.12 tCKL LCD interface pixel clock low time tPCP  0.4 tPCP  0.5 tPCP  0.6 ns A15.13 tDSU LCD interface data setup time 5.0 — — ns A15.14 tDHD LCD interface data hold time 6.0 — — ns A15.15 tCSU LCD interface control signal setup time 5.0 — — ns A15.16 tCHD LCD interface control signal hold time 6.0 — — ns A15.17 MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 71 Electrical and Thermal Characteristics 4.3.12 CAN The CAN functions are available as TX pins at normal IO pads and as RX pins at the VBAT domain. There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup, if configured. 4.3.13 I2C This section specifies the timing parameters of the inter-integrated circuit (I2C) interface. Refer to the I2C bus specification. Table 37. I2C Input Timing Specifications — SCL and SDA Sym 1 Description Start condition hold time Min Max Units SpecID 2 — IP bus cycle1 A18.1 1 A18.2 2 Clock low time 8 — IP bus cycle 4 Data hold time 0.0 — ns A18.3 6 Clock high time 4 — IP bus cycle1 A18.4 7 Data setup time 0.0 — ns A18.5 8 9 Start condition setup time ( for repeated start condition only ) Stop condition setup time 2 2 — — IP bus cycle1 A18.6 1 A18.7 IP bus cycle NOTES: 1 Inter-peripheral clock is defined in the MPC5125 Reference Manual (MPC5125RM) Table 38. I2C Output Timing Specifications — SCL and SDA 1 Sym Description Min Max Units SpecID 12 Start condition hold time 6 — IP bus cycle3 A18.8 22 Clock low time 10 — IP bus cycle3 A18.9 SCL / SDA rise time — 7.9 ns A18.10 4 3 2 4 Data hold time 7 — 52 SCL / SDA fall time — 7.9 ns A18.12 62 Clock high time 10 — IP bus cycle3 A18.13 — IP bus cycle3 A18.14 cycle3 A18.15 A18.16 2 7 Data setup time 2 IP bus cycle3 82 Start condition setup time ( for repeated start condition only ) 20 — IP bus 92 Stop condition setup time 10 — IP bus cycle3 A18.11 NOTES: 1 Output timing is specified at a nominal 50 pF load. 2 Programming IFDR with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time that SCL or SDA takes to reach a high level depends on external signal capacitance and pullup resistor values. 4 Inter -peripheral Clock is defined in the MPC5125 Reference Manual (MPC5125RM). MPC5125 Microcontroller Data Sheet, Rev. 4 72 Freescale Semiconductor Electrical and Thermal Characteristics 2 5 6 SCL 1 4 7 3 8 9 SDA Figure 37. Timing Diagram — I2C Input / Output 4.3.14 J1850 See the MPC5125 Reference Manual (MPC5125RM). 4.3.15 PSC The programmable serial controllers (PSC) support different modes of operation (UART, codec, AC97, SPI). All the timing numbers specified for different PSC modes are design targets. 4.3.15.1 Codec Mode (8-, 16-, 24-, and 32-Bit) / I2S Mode Table 39. Timing Specifications — 8-, 16-, 24-, and 32-Bit CODEC/I2S Master Mode1 Sym 1 Description Bit clock cycle time, programmed in CCS register Min Typ Max Units SpecID 40.0 — — ns A20.1 A20.2 2 Clock duty cycle 45 50 55 %2 3 Bit clock fall time — — 7.9 ns A20.3 4 Bit clock rise time — — 7.9 ns A20.4 5 FrameSync valid after clock edge — — 8.4 ns A20.5 6 FrameSync invalid after clock edge — — 8.4 ns A20.6 7 Output data valid after clock edge — — 9.3 ns A20.7 8 Input data setup time 6.0 — — ns A20.8 NOTES: 1 Output timing is specified at a nominal 50 pF load. 2 Bit clock cycle time. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 73 Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Output 3 2 2 4 BitClk (CLKPOL=1) Output 4 3 5 FrameSync (SyncPol= 1) Output FrameSync (SyncPol= 0) Output 6 7 TxD Output 8 RxD Input Figure 38. Timing Diagram — 8-,16-, 24-, and 32-bit CODEC/I2S Master Mode Table 40. Timing Specifications — 8-,16-, 24-, and 32-bit CODEC/I2S Slave Mode 1 Sym 1 Description Bit clock cycle time Min Typ Max Units SpecID 40.0 — — ns A20.9 A20.10 2 Clock duty cycle — 50 — %2 3 Frame sync setup time 1.0 — — ns A20.11 4 Output data valid after clock edge — — 14.0 ns A20.12 5 Input data setup time 1.0 — — ns A20.13 6 Input data hold time 1.0 — — ns A20.14 NOTES: 1 Output timing is specified at a nominal 50 pF load. 2 Bit clock cycle time. MPC5125 Microcontroller Data Sheet, Rev. 4 74 Freescale Semiconductor Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 2 2 BitClk (CLKPOL=1) Input 3 FrameSync (SyncPol= 1) Input FrameSync (SyncPol= 0) Input 4 TxD Output 5 RxD Input 6 Figure 39. Timing Diagram — 8-,16-, 24-, and 32-bit CODEC/I2S Slave Mode 4.3.15.2 AC97 Mode Table 41. Timing Specifications — AC97 Mode 1 Sym Description Min Typ Max Units SpecID 1 Bit clock cycle time — 81.4 — ns A20.15 2 Clock pulse high time — 40.7 — ns A20.16 3 Clock pulse low time — 40.7 — ns A20.17 4 Frame sync valid after rising clock edge — — 13.0 ns A20.18 5 Output data valid after rising clock edge — — 14.0 ns A20.19 6 Input data setup time 1.0 — — ns A20.20 7 Input data hold time 1.0 — — ns A20.21 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 75 Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 4 FrameSync (SyncPol= 1) Output 5 3 2 Sdata_out Output 6 7 Sdata_in Input Figure 40. Timing Diagram — AC97 Mode 4.3.15.3 SPI Mode Table 42. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) 1 Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.26 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.27 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A20.28 4 Output data valid after slave select (SS) — 8.9 ns A20.29 5 Output data valid after SCK — 8.9 ns A20.30 6 Input data setup time 6.0 — ns A20.31 7 Input data hold time 1.0 — ns A20.32 8 Slave disable lag time — TSCK ns A20.33 9 Sequential transfer delay, programable in the PSC CTUR / CTLR register 15.0 — ns A20.34 10 Clock falling time — 7.9 ns A20.35 11 Clock rising time — 7.9 ns A20.36 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 4 76 Freescale Semiconductor Electrical and Thermal Characteristics 1 10 SCK (CLKPOL=0) Output 2 2 11 SCK (CLKPOL=1) Output 11 10 9 8 3 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 43. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) 1 Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.37 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.38 3 Slave select clock delay 1.0 — ns A20.39 4 Input data setup time 1.0 — ns A20.40 5 Input data hold time 1.0 — ns A20.41 6 Output data valid after SS — 14.0 ns A20.42 7 Output data valid after SCK — 14.0 ns A20.43 8 Slave disable lag time 0.0 — ns A20.44 9 Minimum sequential transfer delay = 2  IP bus clock cycle time 30.0 — — A20.45 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 77 Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 3 9 SS Input 5 4 MOSI Input 6 7 MISO Output Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 44. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) 1 Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.46 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.47 3 Slave select clock delay, programmable in the PSC CCS register 30.0 — ns A20.48 4 Output data valid — 8.9 ns A20.49 5 Input data setup time 6.0 — ns A20.50 6 Input data hold time 1.0 — ns A20.51 7 Slave disable lag time — TSCK ns A20.52 8 Sequential transfer delay, programable in the PSC CTUR / CTLR register 15.0 — ns A20.53 9 Clock falling time — 7.9 ns A20.54 10 Clock rising time — 7.9 ns A20.55 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 4 78 Freescale Semiconductor Electrical and Thermal Characteristics 1 9 SCK (CLKPOL=0) Output 2 2 10 SCK (CLKPOL=1) Output 10 9 8 7 3 SS Output 4 MOSI Output 5 MISO Input 6 Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 45. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) 1 Sym Description Min Max Units SpecID 1 SCK cycle time, programmable in the PSC CCS register 30.0 — ns A20.56 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.57 3 Slave select clock delay 0.0 — ns A20.58 4 Output data valid — 14.0 ns A20.59 5 Input data setup time 2.0 — ns A20.60 6 Input data hold time 1.0 — ns A20.61 7 Slave disable lag time 0.0 — ns A20.62 8 Minimum sequential transfer delay = 2  IP bus clock cycle time 30.0 — ns A20.63 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 79 Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 7 3 SS Input 5 6 MOSI Input 4 MISO Output Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 4.3.16 GPIOs and Timers The MPC5125 contains several sets of I/Os that do not require special setup, hold, or valid requirements. The external events (GPIO or timer inputs) are asynchronous to the system clock. The inputs must be valid for at least tIOWID to ensure proper capture by the internal IP clock. Table 46. GPIO/Timers Input AC Timing Specifications Symbol tIOWID Description GPIO/Timers inputs — minimum pulse width Min Unit SpecID 2T1 ns A21.1 NOTES: 1 T is the IP bus clock cycle. T = 15 ns is the minimum value (for the maximum IP bus frequency of 66 MHz). 4.3.17 Fusebox Table 47 gives the Fusebox timing specification. Table 47. Fusebox Timing Characteristics Sym Description tFUSEWR Program time1 for fuse IFUSEWR Program current to program one fuse bit Min Max Units SpecID 62.5 — s A22.1 — 10 mA A22.2 NOTES: 1 The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module. MPC5125 Microcontroller Data Sheet, Rev. 4 80 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.18 IEEE 1149.1 (JTAG) Table 48. JTAG Timing Specification Sym Characteristic Min Max Unit SpecID — TCK frequency of operation 0 25 MHz A23.1 1 TCK cycle time 40 — ns A23.2 2 TCK clock pulse width measured at 1.5 V 1.08 — ns A23.3 3 TCK rise and fall times 0 3 ns A23.4 1 4 TRST setup time to TCK falling edge 10 — ns A23.5 5 TRST assert time 5 — ns A23.6 5 — ns A23.7 15 — ns A23.8 0 30 ns A23.9 2 6 Input data setup time 7 Input data hold time 8 3 TCK to output data valid 3 9 TCK to output high impedance 0 30 ns A23.10 10 TMS, TDI data setup time 5 — ns A23.11 11 TMS, TDI data hold time 4.5 — ns A23.12 12 TCK to TDO data valid 0 15 ns A23.13 13 TCK to TDO high impedance 0 15 ns A23.14 NOTES: 1 TRST is an asynchronous signal. The setup time is for test purposes only. 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK. 1 2 VM TCK 3 2 VM 3 VM VM = Midpoint Voltage Numbers shown reference JTAG Timing Specification T Figure 45. Timing Diagram — JTAG Clock Input MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 81 Electrical and Thermal Characteristics TCK 4 TRST 5 Numbers shown reference JTAG Timing Specification Table Figure 46. Timing Diagram — JTAG TRST TCK 6 7 Input Data Valid Data Inputs 8 Output Data Valid Data Outputs 9 Data Outputs Numbers shown reference JTAG Timing Specification Table Figure 47. Timing Diagram — JTAG Boundary Scan TCK 10 11 Input Data Valid TDI, TMS 12 Output Data Valid TDO 13 TDO Numbers shown reference JTAG Timing Specification Table Figure 48. Timing Diagram — Test Access Port MPC5125 Microcontroller Data Sheet, Rev. 4 82 Freescale Semiconductor System Design Information 5 System Design Information 5.1 Power Up/Down Sequencing Power sequencing between the 1.4 V power supply VDD and the remaining supplies is required to prevent excessive current during power-up phase. The required power sequence is as follows: • • • • • 5.2 Use 12 V/ms or slower time for all supplies. Power up VDD_IO, AVDD_PLLs, VBAT (if not applied permanently), and VDD_IO_MEM supplies first in any order, and then power up VDD. If required AVDD_FUSEWR should be powered up afterwards. All the supplies must reach the specified operating conditions before the PORESET can be released. For power down, drop AVDD_FUSEWR to 0 V first, drop VDD to 0 V, and then drop all other supplies. VDD should not exceed VDD_IO, VDD_IO_MEM, VBAT, or AVDD_PLLs by more than 0.4 V at any time, including power-up. System and CPU Core AVDD Power Supply Filtering Each of the independent PLL power supplies require filtering external to the device. Figure 49 shows a recommendation for the required filter circuit. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. All traces should be as low impedance as possible, especially ground pins to the ground plane. The filter for system/core PLLVDD to VSS should be connected to the power and ground planes, respectively, not fingers of the planes. In addition to keeping the filter components for system/core PLLVDD as close as practical to the body of the MPC5125 as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise onto the portion of that supply between the filter and the MPC5125. The capacitors for C2 in the figure below should be rated X5R or better due to temperature performance. It is recommended to add a bypass capacitance of at least 1 µF for the VBAT pin. R1= 10  AVDD device pin Power supply source C1= 1 µF C2= 0.1 µF Figure 49. Power Supply Filtering 5.3 Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD and VSS pins of the MPC5125. The unused AVDD_FUSEWR power should be connected to VSS directly or via a resistor. For DDR or LPDDR modes, the unused pins VTT[3:0] for DDR2 termination voltage can be unconnected. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 83 System Design Information 5.4 Pullup/Pulldown Resistor Requirements The MPC5125 requires external pullup or pulldown resistors on certain pins. 5.4.1 Pulldown Resistor Requirements for TEST Pin The MPC5125 requires a pulldown resistor on the test pin TEST. 5.5 JTAG The MPC5125 has an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a common on-chip processor (COP) interface, which shares the IEEE 1149.1 JTAG port. The COP interface provides access to the MPC5125’s embedded e300 processor and to other on-chip resources. This interface provides a means for executing test routines and for performing software development and debug functions. 5.5.1 JTAG_TRST Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted during power-on reset. 5.5.1.1 TRST and PORESET The JTAG interface can control the direction of the MPC5125 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5125 comes out of power-on reset; do this by asserting TRST before PORESET is released. For more details, see the Reset and JTAG Timing Specification. PORESET Required assertion of TRST Optional assertion of TRST TRST Figure 50. PORESET vs. TRST 5.5.2 e300 COP / BDM Interface There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector. 5.5.2.1 Boards Interfacing the JTAG Port via a COP Connector The MPC5125 functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale standard COP / BDM interface. Table 49 gives the COP / BDM interface signals. The pin order shown reflects only the COP / BDM connector order. MPC5125 Microcontroller Data Sheet, Rev. 4 84 Freescale Semiconductor System Design Information Table 49. COP / BDM Interface Signals Internal External Pullup / Pulldown Pullup / Pulldown I/O1 BDM Pin # I / O Pin BDM Connector 16 — GND — — — 15 CKSTP_OUT ckstp_out — 10 k Pullup I 14 — KEY — — — 13 HRESET hreset Pullup 10 k Pullup O 12 — GND — — — 11 SRESET sreset Pullup 10 k Pullup O 10 — N/C — — — 9 TMS tms Pullup 10 k Pullup O 8 CKSTP_IN ckstp_in — 10 k Pullup O 7 TCK tck Pullup 10 k Pullup O 6 — VDD 2 — — — 5 Note3 halted — — I See 3 4 TRST trst Pullup 10 k Pullup O 3 TDI tdi Pullup 10 k Pullup O 2 See Notepci_frame qack4 — — O 1 TDO tdo — — I NOTES: 1 With respect to the emulator tool’s perspective: Input is really an output from the embedded e300 core. Output is really an input to the core. 2 From the board under test, power sense for chip power. 3 HALTED is not available from e300 core. For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG module, it is not recommended to wire only TRST and PORESET. To reset the MPC5125 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5125. The circuitry shown in Figure 51 allows the COP to assert HRESET or TRST separately, while any other board sources can drive PORESET. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 85 System Design Information PORESET PORESET COP Header 13 11 HRESET 1 2 3 4 5 6 7 8 10 11 12 13 K 15 16 VDD_IO 10 k 10 k SRESET VDD_IO 4 TRST TRST 14 9 10 k TMS VDD_IO TMS 12 7 9 HRESET VDD_IO SRESET 16 COP Connector Physical Pinout 10 k 6 (2) 1 3 10 k TCK VDD_IO VDD_IO TCK TDO TDO 10 k TDI VDD_IO TDI 15 CKSTP_OUT 10 k VDD_IO CKSTP_OUT 8 CKSTP_IN 5 (3) halted 2 (4) qack 10 10 k VDD_IO CKSTP_IN NC NC NC Figure 51. COP Connector Diagram 5.5.2.2 Boards Without COP Connector If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal (PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 52 shows the connection of the JTAG interface without COP connector. MPC5125 Microcontroller Data Sheet, Rev. 4 86 Freescale Semiconductor System Design Information PORESET HRESET SRESET PORESET 10 k HRESET VDD_IO 10 k VDD_IO SRESET TRST 10 k VDD_IO JTAG_TMS 10 k VDD_IO TCK 10 k VDD_IO TDI CKSTP_OUT TDO Figure 52. TRST Wiring for Boards without COP Connector MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 87 Package Information 6 Package Information This section details package parameters and dimensions. The MPC5125 is available in a thermally enhanced plastic ball grid array (TEPBGA). Section 6.1, “Package Parameters,” and Section 6.2, “Mechanical Dimensions,” provide information on the TEPBGA. 6.1 Package Parameters Table 50. TEPBGA Parameters Package outline 23 mm  23 mm Interconnects 324 Pitch 1.00 mm Module height (typical) 2.25 mm Solder balls 96.5 Sn/3.5Ag (VN package) Ball diameter (typical) 0.6 mm MPC5125 Microcontroller Data Sheet, Rev. 4 88 Freescale Semiconductor Package Information 6.2 Mechanical Dimensions Figure 3 shows the mechanical dimensions and bottom surface nomenclature of the MPC5125 324 TEPBGA package. Figure 53. Mechanical Drawing of MPC5125 PBGA (1 of 3) MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 89 Package Information Figure 54. Mechanical Drawing of MPC5125 PBGA (2 of 3) MPC5125 Microcontroller Data Sheet, Rev. 4 90 Freescale Semiconductor Package Information Figure 55. Mechanical Drawing of MPC5125 PBGA (3 of 3) MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 91 7 Product Documentation This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com . The following documents are required for a complete description of the device and are necessary to design properly with the parts: • • MPC5125 Microprocessor Reference Manual (document number MPC5125RM) MPC5125 (0M01S) Errata (document number MSE5125_0M01S) Revision History 8 Revision History Table 51 describes the changes made to this document between revisions. Table 51. Revision History Revision Date 1 October 2008 Initial public release, NDA required, Advance Information. 2 October 2009 Public release, Technical Data.  — Updated specifications according to characterized data.  — Updated Table 1, orderable part numbers.  — Updated Table 2, pin multiplexing.  — Editorial updates. 3 4 Description November 2009 Public release, Technical Data.  — Corrected part number. August 2011 Public release, Technical Data.  —Incorporated TKT052929. Updated Table 2, “pin multiplexing”.FEC1_TX_CLK I/O direction changed from O to I. —Incorporated TKT052932. Updated Table 2, “pin multiplexing”. NFC_R/B changed to NFC_R/B0 for ALT0 of NFC_RB ; the ALT2 function of the PSC1_3 signal lists NFC_R/B2 signal direction changed as an input; the ALT2 function of the J1850_RX signal lists NFC_R/B3 signal direction changed as an input. —Incorporated TKT068361.Updated Table 2, “pin multiplexing”. FEC1_TX_ER I/O direction changed from I to O, FEC1_MDC I/O direction changed from I to O,FEC2_TX_ER changed from I to O,FEC2_MDC I/O direction changed from I to O. —Updated Table 2, “pin multiplexing”. "ALT3" replaced with "ALT2" for "RST_CONF" (reset configuration);FEC1_MDIO/RMII_MDIO I/O direction changed from I to I/O ; FEC_TX_EN I/O direction changed to O from I;USB1_DATA1and USB1_NEXT I/O direction changed to O from I —Updated Table 6, ”DC Electrical Specifications”.The unit of “RODT” changed to ‘ohm’ from ‘W’. MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 93 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MPC5125 Rev. 4 09/2011 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008–2011. All rights reserved.