TDF8591TH
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
Rev. 01 — 5 March 2008
Product data sheet
1. General description
The TDF8591TH is a high-efficiency class-D audio power amplifier with low power
dissipation for application in car audio systems. The typical output power is 2 × 100 W
into 4 Ω.
The TDF8591TH is available in an HSOP24 power package with a small internal heat
sink. Depending on the supply voltage and load conditions, a small or even no external
heat sink is required. The amplifier operates over a wide supply voltage range from ±14 V
to ±29 V and consumes a low quiescent current.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Zero dead time switching
Advanced output current protection
No DC offset induced pop noise at mode transitions
High efficiency
Supply voltage from ±14 V to ±29 V
Low quiescent current
Usable as a stereo Single-Ended (SE) amplifier or as a mono amplifier in Bridge-Tied
Load (BTL)
Fixed gain of 26 dB in SE and 32 dB in BTL
High BTL output power: 310 W into 4 Ω
Suitable for speakers in the 2 Ω to 8 Ω range
High supply voltage ripple rejection
Internal oscillator or synchronized to an external clock
Full short-circuit proof outputs across load and to supply lines
Thermal foldback and thermal protection
AEC-Q100 qualified
3. Ordering information
Table 1.
Ordering information
Type number
TDF8591TH
Package
Name
Description
Version
HSOP24
plastic, heatsink small outline package; 24 leads; low stand-off height
SOT566-3
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
4. Block diagram
VDDA2
VDDA1
3
STABI DIAG
10
18
VDDP2
VDDP1
23
14
13
15
IN1M
IN1P
9
8
RELEASE1
PWM
MODULATOR
INPUT
STAGE
SWITCH1
ENABLE1
SGND1
OSC
MODE
SGND2
mute
11
IN2M
DRIVER
HIGH
STABI
6
OSCILLATOR
OUT1
VSSP1
TDF8591TH
TEMPERATURE SENSOR
CURRENT PROTECTION
VOLTAGE PROTECTION
MANAGER
MODE
16
DRIVER
LOW
7
VDDP2
22
BOOT2
2
ENABLE2
mute
IN2P
CONTROL
AND
HANDSHAKE
BOOT1
5
4
SWITCH2
INPUT
STAGE
1
VSSA2
PWM
MODULATOR
CONTROL
AND
HANDSHAKE
RELEASE2
12
24
VSSA1
VSSD
DRIVER
HIGH
21
OUT2
DRIVER
LOW
19
n.c.
17
20
VSSP1
VSSP2
001aah194
Fig 1. Block diagram
5. Pinning information
5.1 Pinning
VSSD 24
1
VDDP2 23
2
SGND2
BOOT2 22
3
VDDA2
IN2M
VSSA2
OUT2 21
4
VSSP2 20
5
IN2P
n.c. 19
6
MODE
7
OSC
STABI 18
TDF8591TH
VSSP1 17
8
IN1P
OUT1 16
9
IN1M
BOOT1 15
VDDP1 14
10 VDDA1
11 SGND1
DIAG 13
12 VSSA1
001aah195
Fig 2. Pin configuration (top view)
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
2 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VSSA2
1
negative analog supply voltage for channel 2
SGND2
2
signal ground for channel 2
VDDA2
3
positive analog supply voltage for channel 2
IN2M
4
negative audio input for channel 2
IN2P
5
positive audio input for channel 2
MODE
6
mode selection input: standby, mute or operating
OSC
7
oscillator frequency adjustment or tracking input
IN1P
8
positive audio input for channel 1
IN1M
9
negative audio input for channel 1
VDDA1
10
positive analog supply voltage for channel 1
SGND1
11
signal ground for channel 1
VSSA1
12
negative analog supply voltage for channel 1
DIAG
13
diagnostic for activated current protection
VDDP1
14
positive power supply voltage for channel 1
BOOT1
15
bootstrap capacitor for channel 1
OUT1
16
PWM output from channel 1
VSSP1
17
negative power supply voltage for channel 1
STABI
18
decoupling of internal stabilizer for logic supply
n.c.
19
not connected
VSSP2
20
negative power supply voltage for channel 2
OUT2
21
PWM output from channel 2
BOOT2
22
bootstrap capacitor for channel 2
VDDP2
23
positive power supply voltage for channel 2
VSSD
24
negative digital supply voltage[1]
[1]
The heatsink is internally connected to VSSD.
6. Functional description
6.1 Introduction
The TDF8591TH is a dual channel audio power amplifier using class-D technology. The
audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog
input stage and PWM modulator. To enable the output power transistors to be driven, this
digital PWM signal is applied to a control and handshake block and driver circuits for both
the high-side and low-side. An external 2nd-order low-pass filter converts the PWM output
signal to an analog audio signal across the loudspeakers.
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
3 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
The TDF8591TH contains two independent amplifier channels with a differential input
stage, high output power, high efficiency (90 %), low distortion and a low quiescent
current. The amplifier channels can be connected in the following configurations:
• Mono Bridge-Tied Load (BTL) amplifier
• Dual Single-Ended (SE) amplifiers
The TDF8591TH also contains circuits common to both channels such as the oscillator, all
reference sources, the mode functionality and a digital timing manager. For protection a
thermal foldback, temperature, current and voltage protection are built in.
6.2 Mode selection
The TDF8591TH can be switched in three operating modes via pin MODE:
• Standby mode; the amplifiers are switched off to achieve a very low supply current
• Mute mode; the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the VI-converter input stages
• Operating mode; the amplifiers are fully operational with output signal
The input stage (see Figure 1) contributes to the DC offset measured at the amplifier
output. To avoid pop noise the DC output offset voltage should be increased gradually at a
mode transition from mute to operating, or vice versa, by limiting the dVMODE/dt on pin
MODE, resulting in a small dVO(offset)/dt for the DC output offset voltage. The required time
constant for a gradually increase of the DC output offset voltage between mute and
operating is generated via an RC network on pin MODE. An example of a switching circuit
for driving pin MODE is illustrated in Figure 3 and explained in Table 3.
VDDP
5.6 kΩ
5.6 kΩ
MODE
5.6 kΩ
100 µF
(10 V)
5.6 V
S1
S2
SGND
001aad836
Fig 3. Example of mode selection circuit
Table 3.
Mode selection
S1
S2
Mode selection
closed
closed
Standby mode
closed
open
Standby mode
open
closed
Mute mode
open
open
Operating mode
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
4 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
The value of the RC time constant should be dimensioned for 500 ms. If the 100 µF
capacitor is left out of the application the voltage on pin MODE will be applied with a much
smaller time constant, which might result in audible pop noises during start-up (depending
on DC output offset voltage and used loudspeaker).
In order to fully charge the coupling capacitors at the inputs, the amplifier will remain
automatically in Mute mode for approximately 150 ms before switching to Operating
mode. A complete overview of the start-up timing is given in Figure 4.
audio
switching
VMODE
operating
5V
mute
2.5 V
0 V (SGND)
standby
100 ms
>50 ms
time
audio
switching
VMODE
operating
5V
0 V (SGND)
standby
100 ms
50 ms
time
001aad837
Fig 4. Timing on mode selection input
6.3 Pulse width modulation frequency
The output signal of the amplifier is a PWM signal with a switching frequency that is set by
an external resistor Rext(OSC) connected between pins OSC and VSSA. An optimum setting
for the carrier frequency is between 300 kHz and 350 kHz. An external resistor Rext(OSC) of
30 kΩ sets the frequency to 310 kHz.
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
5 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
If two or more class-D amplifiers are used in the same audio application, it is
recommended to synchronize the switching frequency of all devices to an external clock
(see Section 12.3).
6.4 Protections
The following protections are included in TDF8591TH:
•
•
•
•
•
Thermal Foldback (TF)
OverTemperature Protection (OTP)
OverCurrent Protection (OCP)
Window Protection (WP)
Supply voltage protections
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– Unbalance Protection (UBP)
The reaction of the device on the different fault conditions differs per protection and is
described in Section 6.4.1 to Section 6.4.5.
6.4.1 Thermal foldback
If the junction temperature Tj > 145 °C, then the TF gradually reduced the gain, resulting in
a smaller output signal and less dissipation. At Tj = 155 °C the outputs are fully muted.
6.4.2 Overtemperature protection
If Tj > 160 °C, then the OTP will shut down the power stage immediately.
6.4.3 Overcurrent protection
The OCP will detect a short-circuit between the loudspeaker terminals or if one of the
loudspeaker terminals is short-circuited to one of the supply lines.
If the output current tends to exceed the maximum output current of 12 A, the output
voltage of the TDF8591TH will be regulated to a level where the maximum output current
is limited to 12 A while the amplifier outputs remain switching, the amplifier does not shut
down. When this active current limiting continues longer than a time τ (see Figure 5) the
capacitor on pin DIAG is discharged below a threshold value and the TDF8591TH shuts
down. Activation of current limiting and the triggering of the OCP is observed at pin DIAG
(see Figure 5).
A maximum value for the capacitor on pin DIAG is 47 pF. The reference voltage on pin
DIAG is VSSA. Pin DIAG should not be connected to an external pull-up.
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
6 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
≈ VSSA + 8 V
Ch1 mean
5.03 V
≈ VSSA + 2 V
VSSA
τ
M 20.0 ms A Ch1 ~ 1.28 V
001aad838
Fig 5. Pin DIAG with activated current limiting
input voltage 2
current in the 3
short-circuit
(between the
speaker terminals)
PWM output 1
pin DIAG 4
Ch1
Ch3
50.0 V∼
5.00 VΩ
50 ms
Ch2 500 mV
Ch4 10.0 V
M 25.0 ms
50 ms
50 ms
Ch3
1.80 V
001aah365
Fig 6. Restart of the TDF8591TH
When the loudspeaker terminals are short-circuited and the OCP is triggered the
TDF8591TH is switched off completely and will try to restart every 100 ms (see Figure 6):
• 50 ms after switch off pin DIAG will be released
• 100 ms after switch off the amplifier will return to mute
• 150 ms after switch off the amplifier will return to operation. If the short-circuit
condition is still present after this time this cycle will be repeated. The average
dissipation will be low because of the small duty cycle
A short-circuit of the loudspeaker terminals to one of the supply lines will also trigger the
activation of the OCP and the amplifier will shut down. During restart the window
protection will be activated. As a result the amplifier will not start up after 100 ms and pin
DIAG will remain LOW until the short-circuit to the supply lines is removed.
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
7 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
6.4.4 Window protection
The WP checks the conditions at the output pins of the power stage and is activated:
• During the start-up sequence, when pin MODE is switched from standby to mute. In
the event of a short-circuit at one of the output pins to VDD or VSS the start-up
procedure is interrupted and the TDF8591TH waits until the short-circuit to the supply
lines has been removed. Because the test is done before enabling the power stages,
no large currents will flow in the event of a short-circuit.
• When the amplifier is completely shut down due to activation of the OCP by a
short-circuit to one of the supply lines, the window protection will then be activated
during restart (after 100 ms). As a result the amplifier will not start up until the
short-circuit to the supply lines is removed.
6.4.5 Supply voltage protections
If the supply voltage drops below ±12.5 V, the UVP circuit is activated and the
TDF8591TH switch-off will be silent and without pop noise. When the supply voltage rises
above ±12.5 V, the TDF8591TH is restarted again after 100 ms.
If the supply voltage exceeds ±33 V the OVP circuit is activated and the power stages will
shut down. It is re-enabled as soon as the supply voltage drops below ±33 V. So in this
case no timer of 100 ms is started. The maximum operating supply voltage is ±29 V and if
the supply voltage is above the maximal allowable voltage of ±34 V (see Section 7), the
TDF8591TH can be damaged, irrespective of an activated OVP. See Section 12.6
“Pumping effects” for more information about the use of the OVP.
An additional UBP circuit compares the positive analog (VDDA) and the negative analog
(VSSA) supply voltages and is triggered if the voltage difference between them exceeds
the unbalance threshold level, which is expressed as follows:
V th ( unb ) ≈ 0.15 × ( V DDA – V SSA ) V
When the supply voltage difference VDDA − VSSA exceeds Vth(unb), the TDF8591TH
switches off and is restarted again after 100 ms.
Example: With a symmetrical supply of VDDA = 20 V and VSSA = −20 V, the unbalance
protection circuit will be triggered if the unbalance exceeds approximately 6 V.
In Table 4 an overview is given of all protections and the effect on the output signal.
Table 4.
Overview protections TDF8591TH
Protection name Complete shut down Restart directly
DIAG
TF
N
N
N
OTP
Y
Y[2]
N[2]
N
OCP
N[3]
Y[3]
N[3]
Y
WP
Y[4]
Y
N
Y
UVP
Y
N
Y
N
OVP
Y
Y
N
N
UBP
Y
N
Y
N
[1]
Amplifier gain will depend on junction temperature and heat sink size.
[2]
Thermal foldback will influence restart timing depending on heat sink size.
TDF8591TH_1
Product data sheet
Restart every 100 ms
Y[1]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
8 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
[3]
Only complete shut down of amplifier in case of a short-circuit. In all other cases current limiting resulting in
clipping output signal.
[4]
Fault condition detected during (every) transition between standby-to-mute and during restart after
activation of OCP (short-circuit to one of the supply lines).
6.5 Diagnostic output
Pin DIAG is pulled LOW when the OCP is triggered. With a continuous short-circuited load
a switching pattern in the voltage on pin DIAG is observed (see Figure 6). A permanent
LOW on pin DIAG indicates a short-circuit to the supply lines whereas a short-circuited
load causes a switching DIAG pin (see Section 6.4.3).
The pin DIAG reference voltage is VSSA. Pin DIAG should not be connected to an external
pull-up. An example of a circuit to read out and level shift the diagnostic data is given in
Figure 7. V5V represents a logic supply that is used in the application by the
microprocessor that reads out the DIAG data.
V5V
VDDA
5.6 V
100 kΩ
10 kΩ
DIAG
out
M2
100 kΩ
DIAG
M1
SGND
27 kΩ
VSSA
001aad840
Fig 7. DIAG readout circuit with level shift
6.6 Differential inputs
For a high Common Mode Rejection Ratio (CMRR) and a maximum of flexibility in the
application, the audio inputs are fully differential. By connecting the inputs anti-parallel the
phase of one of the channels can be inverted, so that a load can be connected between
the two output filters. In this case the system operates as a mono BTL amplifier.
The input configuration for a mono BTL application is illustrated in Figure 8.
In the stereo SE configuration it is also recommended to connect the two differential
inputs in anti-phase. This has advantages for the current handling of the supply voltage at
low signal frequencies (supply pumping).
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
9 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
IN1P
IN1M
SGND
IN2P
IN2M
001aad841
Input resistors are referred to SGND.
a. Internal circuitry
OUT1
IN1P
IN1M
Vin
SGND
IN2P
IN2M
OUT2
power stage
mbl466
b. External connections
Fig 8. Input configuration for mono BTL application
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
VDDP1 and VDDA1 referred to
SGND1; VDDP2 and VDDA2 referred
to SGND2
−0.3
+34
V
VSS
negative supply voltage
VSSP1 and VSSA1 referred to
SGND1; VSSP2 and VSSA2 referred
to SGND2
−34
+0.3
V
VP
supply voltage
−0.3
+66
V
IOSM
non-repetitive peak output current
-
12
A
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
VBOOT1
voltage on pin BOOT1
−40
+150
°C
referred to OUT1
[1]
0
14
V
0
14
V
-
14
V
VBOOT2
voltage on pin BOOT2
referred to OUT2
[1]
VSTABI
voltage on pin STABI
referred to VSSD
[2]
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
10 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
Table 5.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VMODE
voltage on pin MODE
referred to SGND2
0
8
V
VOSC
voltage on pin OSC
referred to VSSD
0
40
V
VIN1M
voltage on pin IN1M
referred to SGND1
−5
+5
V
VIN1P
voltage on pin IN1P
referred to SGND1
−5
+5
V
VIN2M
voltage on pin IN2M
referred to SGND2
−5
+5
V
VIN2P
voltage on pin IN2P
referred to SGND2
−5
+5
V
0
9
V
VSSP − 0.3
VDDP + 0.3 V
VDIAG
voltage on pin DIAG
VO
output voltage
referred to VSSD
[3]
[1]
Pin BOOT should not be loaded by any other means than the boot capacitor. A short-circuit between pin BOOT and VSS will damage the
device.
[2]
Pin STABI should not be loaded by an external circuit. A short-circuit between pin STABI and a voltage source or VSS will damage the
device.
[3]
Pin DIAG should not be connected to a voltage source or to a pull-up resistor. An example of a circuit that can be used to read out
diagnostic data is given in Figure 7.
8. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Rth(j-c)
thermal resistance from junction to case
Rth(j-a)
thermal resistance from junction to ambient
Conditions
In free air
Typ
Unit
1
K/W
35
K/W
9. Static characteristics
Table 7.
Static characteristics
VP = ±27 V; fosc = 310 kHz; Tamb = −40 °C to +85 °C; Tj = −40 °C to +150 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
±14
±27
±29
V
Supply
[1]
VP
supply voltage
Iq(tot)
total quiescent current
no load, no filter, no snubber
network connected
-
50
65
mA
Istb
standby current
Tj = −40 °C to +85 °C
-
150
500
µA
Mode select input; pin MODE (reference to SGND2)
IMODE
VMODE
current on pin MODE
voltage on pin MODE
-
100
300
µA
Standby mode
[2][3]
0
-
0.8
V
Mute mode
[2][3]
2.2
-
2.8
V
Operating mode
[2][3]
4.2
-
6
V
VMODE = 5.5 V
Diagnostic output; pin DIAG (reference to VSSD)
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
activated OCP or WP
[4]
-
-
0.8
V
no activated OCP or WP
[4]
-
8.4
9
V
-
V
Audio inputs; pins IN1M, IN1P (reference to SGND1), IN2P and IN2M (reference to SGND2)
VI
[2]
input voltage
TDF8591TH_1
Product data sheet
-
0
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
11 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
Table 7.
Static characteristics …continued
VP = ±27 V; fosc = 310 kHz; Tamb = −40 °C to +85 °C; Tj = −40 °C to +150 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
20
mV
Amplifier outputs; pins OUT1 and OUT2
VO(offset)
output offset voltage
SE; mute
[5]
SE; operating
BTL; mute
[5]
BTL; operating
-
-
170
mV
-
-
30
mV
-
-
240
mV
11
12.5
14
V
-
160
180
°C
145
150
-
°C
Stabilizer output; pin STABI (reference to VSSP1)
output voltage
VO
mute and operating; with respect
to VSSD
Temperature protection
Tprot
Tact(th_fold)
protection temperature
thermal foldback activation
temperature
[6]
closed loop SE voltage gain
reduced with 6 dB
[1]
The circuit is DC adjusted at VP = ±12.5 V to ±30 V.
[2]
Refers to usage in a symmetrical supply application (see Section 12.7). In an asymmetrical supply application the SGND voltage should
be defined by an external circuit.
[3]
The transition between Standby and Mute mode contains hysteresis, while the slope of the transition between Mute and Operating
mode is determined by the time constant on pin MODE (see Figure 9).
[4]
Pin DIAG should not be connected to an external pull-up.
[5]
DC output offset voltage is applied to the output during the transition between Mute and Operating mode in a gradual way. The
dVO(offset)/dt caused by any DC output offset is determined by the time constant on pin MODE.
[6]
At a junction temperature of approximately Tact(th_fold) − 5 °C the gain reduction will commence and at a junction temperature of
approximately Tact(th_fold) + 5 °C the amplifier mutes.
slope is directly related to the
time constant on pin MODE
VO(offset)
operating
STBY
MUTE
ON
mute
0
0.8
2.2
2.8
5.5
4.2
VMODE (V)
001aad842
Fig 9. Behavior of pin MODE
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
12 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
10. Dynamic characteristics
10.1 Dynamic characteristics (SE)
Table 8.
Dynamic characteristics (SE)
VP = ±27 V; RL = 4 Ω; fi = 1 kHz; fosc = 310 kHz; Rs(L) < 0.1 Ω [1]; Tamb = −40 °C to +85 °C; Tj = −40 °C to +150 °C; unless
otherwise specified. See Section 12.7 for the SE application schematics. The 2nd-order demodulation filter coil is referred to
as L and the capacitor as C.
Symbol
Po
Parameter
Conditions
output power
peak output current
IOM
THD
Min
Typ
Max
Unit
L = 10 µH; C = 1 µF; Tj = 85 °C; RL = 2 Ω;
VP = ±28 V; THD = 0.5 %
[2]
-
130
-
W
L = 10 µH; C = 1 µF; Tj = 85 °C; RL = 2 Ω;
VP = ±28 V; THD = 10 %
[2]
-
158
-
W
L = 22 µH; C = 680 nF; Tj = 85 °C;
RL = 4 Ω; VP = ±29 V; THD = 0.5 %
[2]
-
82
-
W
L = 22 µH; C = 680 nF; Tj = 85 °C;
RL = 4 Ω; VP = ±29 V; THD = 10 %
[2]
-
100
-
W
current limiting, see Section 6.4.3
total harmonic distortion Po = 1 W; fi = 1 kHz
Po = 1 W; fi = 10 kHz
Gv(cl)
closed-loop voltage gain
SVRR
supply voltage ripple
rejection
12
-
-
A
[3]
-
0.02
0.2
%
[3]
-
0.10
-
%
25
26
27
dB
operating; fripple = 100 Hz
[4]
-
55
-
dB
operating; fripple = 1 kHz
[4]
40
50
-
dB
mute; fripple = 1 kHz
[4]
-
55
-
dB
standby; fripple = 100 Hz
[4]
-
80
-
dB
45
68
-
kΩ
|Zi(dif)|
differential input
impedance
between the input pins INxP and INxM
Vn(o)
noise output voltage
operating; VP = ±27 V; RS = 0 Ω
[5]
-
170
-
µV
operating; VP = ±18 V; RS = 0 Ω
[5]
-
145
-
µV
mute; VP = ±27 V
[6]
-
125
-
µV
mute; VP = ±18 V
[6]
-
85
-
µV
-
70
-
dB
-
-
1
dB
-
73
-
dB
-
75
-
dB
αcs
channel separation
|∆Gv|
voltage gain difference
αmute
mute attenuation
CMRR
Po = 1 W; RS = 0 Ω; fi = 1 kHz
fi = 1 kHz; Vi = 1 V (RMS value)
common mode rejection fi(CM) = 1 kHz; Vi(CM) = 1 V (RMS value)
ratio
[7]
[1]
Rs(L) is the series resistance of inductor of low-pass LC filter in the application.
[2]
Output power is measured indirectly; based on RDSon measurement (see Section 12.2).
[3]
THD is measured in a bandwidth of 22 Hz to 20 kHz, AES brick wall. Maximum limit is guaranteed but may not be 100 % tested.
[4]
Vripple = Vripple(max) = 2 V (peak-to-peak value); source resistance RS = 0 Ω.
[5]
B = 22 Hz to 20 kHz, AES brick wall (see Section 12.4).
[6]
B = 22 Hz to 20 kHz, AES brick wall, independent of RS (see Section 12.4).
[7]
Vi(CM) is the input common mode voltage.
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
13 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
10.2 Dynamic characteristics (BTL)
Table 9.
Dynamic characteristics (BTL)
VP = ±27 V; RL = 8 Ω; fi = 1 kHz; fosc = 310 kHz; Rs(L) < 0.1 Ω [1]; Tamb = −40 °C to +85 °C; Tj = −40 °C to +150 °C; unless
otherwise specified. See Section 12.7 for the BTL application schematics. The 2nd order demodulation filter coil is referred to
as L and the capacitor as C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Po
output power
L = 10 µH, C = 1 µF; Tj = 85 °C; RL = 4 Ω;
VP = ±18 V; THD = 0.5 %
[2]
-
110
-
W
L = 10 µH; C = 1 µF; Tj = 85 °C; RL = 4 Ω;
VP = ±18 V; THD = 10 %
[2]
-
139
-
W
L = 22 µH; C = 680 nF; Tj = 85 °C;
RL = 4 Ω; VP = ±27 V; THD = 0.5 %
[2]
-
250
-
W
L = 22 µH; C = 680 nF; Tj = 85 °C;
RL = 4 Ω; VP = ±27 V; THD = 10 %
[2]
-
310
-
W
peak output current
IOM
THD
current limiting, see Section 6.4.3
12
-
-
A
[3]
-
0.02
0.2
%
Po = 1 W; fi = 10 kHz
[3]
-
0.15
-
%
31
32
33
dB
operating; fripple = 100 Hz
[4]
-
68
-
dB
operating; fripple = 1 kHz
[4]
50
68
-
dB
mute; fripple = 1 kHz
[4]
-
68
-
dB
standby; fripple = 100 Hz
[4]
-
80
-
dB
22
34
-
kΩ
total harmonic distortion Po = 1 W; fi = 1 kHz
Gv(cl)
closed-loop voltage gain
SVRR
supply voltage ripple
rejection
|Zi(dif)|
differential input
impedance
measured between the input pins INxP
and INxM
Vn(o)
noise output voltage
operating; VP = ±27 V; RS = 0 Ω
[5]
-
240
-
µV
operating; VP = ±18 V; RS = 0 Ω
[5]
-
200
-
µV
mute; VP = ±27 V
[6]
-
180
-
µV
mute; VP = ±18 V
[6]
-
125
-
µV
-
70
-
dB
-
75
-
dB
αmute
mute attenuation
CMRR
common mode rejection fi(CM) = 1 kHz; Vi(CM) = 1 V (RMS value)
ratio
fi = 1 kHz; Vi = 1 V (RMS value)
[1]
Rs(L) is the series resistance of inductor of low-pass LC filter in the application.
[2]
Output power is measured indirectly; based on RDSon measurement (see Section 12.2).
[3]
THD is measured in a bandwidth of 22 Hz to 20 kHz, AES brick wall. Maximum limit is guaranteed but may not be 100 % tested.
[4]
Vripple = Vripple(max) = 2 V (peak-to-peak value); RS = 0 Ω.
[5]
B = 22 Hz to 20 kHz, AES brick wall (see Section 12.4).
[6]
B = 22 Hz to 20 kHz, AES brick wall, independent on RS (see Section 12.4).
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
14 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
11. Switching characteristics
Table 10. Switching characteristics
VDD = 27 V; Tamb = −40 °C to +85 °C; Tj = −40 °C to +150 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal oscillator
fosc
oscillator frequency
typical; Rext(OSC) = 30.0 kΩ
290
310
344
kHz
maximum; Rext(OSC) = 15.4 kΩ
-
560
-
kHz
minimum; Rext(OSC) = 48.9 kΩ
-
200
-
kHz
External oscillator or frequency tracking
VH(OSC)min minimum HIGH-level voltage on pin OSC
referred to SGND
4
-
6
V
VL(OSC)max maximum LOW-level voltage on pin OSC
referred to SGND
0
-
1
V
210
-
600
kHz
∆ftrack
tracking frequency range
Drain source on-state resistance of the output transistors
RDSon(ls)
RDSon(hs)
low-side drain-source on-state resistance
high-side drain-source on-state resistance
Tj = 85 °C; IDS = 6 A
-
185
205
mΩ
Tj = 25 °C; IDS = 6 A
-
140
155
mΩ
Tj = 85 °C; IDS = 6 A
-
220
245
mΩ
Tj = 25 °C; IDS = 6 A
-
160
175
mΩ
12. Application information
12.1 BTL application
When using the power amplifier in a mono BTL application the inputs of both channels
must be connected in parallel and the phase of one of the inputs must be inverted (see
Figure 8). The loudspeaker is connected between the outputs of the two single-ended
demodulation filters.
12.2 Output power estimation
The achievable output powers in SE and BTL applications can be estimated using the
following expressions:
SE: P o ( 0.5% )
RL
f osc 2
-----------------------------------------------------× V P × 1 – t w ( min ) × ----------
R L + R DSon ( hs ) + R s ( L )
2
= ---------------------------------------------------------------------------------------------------------------------------------- W
2 × RL
BTL: P o ( 0.5% )
RL
f osc 2
------------------------------------------------------------------------------------------× 2V P × 1 – t w ( min ) × ----------
R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R s ( L )
2
= -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- W
2 × RL
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
15 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
Peak output current, internally limited to 12 A:
SE: I OM
f osc
V P × 1 – t w ( min ) × ----------
2
= ------------------------------------------------------------- A
R L + R DSon ( hs ) + R s ( L )
BTL: I OM
f osc
2V P × 1 – t w ( min ) × ---------
2
= ------------------------------------------------------------------------------------------- A
R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R s ( L )
Variables:
RL = load resistance
Rs(L) = series resistance of the filter coil
RDSon(hs) = high side drain source on-state resistance (temperature dependent)
RDSon(ls) = low side drain source on-state resistance (temperature dependent)
fosc = oscillator frequency
tw(min) = minimum pulse width (typical 150 ns, temperature dependent)
VP = single sided supply voltage [or 0.5 (VDD + |VSS|)]
Po(0.5%) = output power at the onset of clipping
IOM should be below 12 A (see Section 6.4.3). IOM is the sum of the current through the
load and the ripple current. The value of the ripple current is dependent on the coil
inductance and voltage drop over the coil.
12.3 External clock
If two or more class-D amplifiers are used it is recommended that all devices run at the
same switching frequency. This can be realized by connecting all OSC pins together and
feed them from an external oscillator.
The internal oscillator requires an external Rext(OSC) and Cext(OSC) between pins OSC and
VSSA. For application of an external oscillator it is necessary to force OSC to a DC level
above SGND. The internal oscillator is disabled and the PWM modulator will switch with
the external frequency. The duty cycle of the external clock should be between 47.5 %
and 52.5 %.
The noise contribution of the internal oscillator is supply voltage dependent. In low noise
applications running at high supply voltage an external low noise oscillator is
recommended.
12.4 Noise
Noise should be measured using a high-order low-pass filter with a cut-off frequency of
20 kHz. The standard audio band pass filters used in audio analyzers do not suppress the
residue of the carrier frequency sufficiently to ensure a reliable measurement of the
audible noise. Noise measurements should preferably be carried out using AES 17 (Brick
Wall) filters or the Audio Precision AUX 0025 filter, which was designed especially for
measuring switching (class-D) amplifiers.
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
16 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
12.5 Heat sink requirements
In some applications it may be necessary to connect an external heat sink to the
TDF8591TH. The thermal foldback activates on Tj = 140 °C. The expression below shows
the relationship between the maximum power dissipation before activation of the thermal
foldback and the total thermal resistance from junction to ambient:
T j – T amb
R th ( j –a ) = ----------------------- Ω
P
The power dissipation (P) is determined by the efficiency (η) of the TDF8591TH. The
efficiency measured as a function of output power is given in Figure 30 and 31. The power
dissipation can be derived as function of output power (see Figure 32 and 33).
Example of a heatsink calculation for the 4 Ω BTL application with ±18 V supply:
• An audio signal with a crest factor of 10 (the ratio between peak power and average
power is 10 dB), this means that the average output power is 1⁄10 of the peak power
•
•
•
•
•
•
The peak RMS output power level is 110 W (0.5 % THD level)
The average power is 0.1 × 110 W = 11 W
The dissipated power at an output power of 11 W is approximately 5 W
The total Rth(j-a) = (140 − 85) / 5 = 11 K/W, if the maximum expected Tamb = 85 °C
The total thermal resistance Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a)
Rth(j-c) = 1 K/W, Rth(c-h) = 0.5 K/W to 1 K/W (dependent on mounting), so Rth(h-a) would
then be: 11 − (1 + 1) = 9 K/W
12.6 Pumping effects
When the TDF8591TH is used in a SE configuration, a so-called pumping effect can
occur. During one switching interval, energy is taken from one supply (e.g. VDDA1), while a
part of that energy is delivered back to the other supply line (e.g. VSSA1) and visa versa.
When the voltage supply source cannot sink energy, the voltage across the output
capacitors of that voltage supply source will increase: the supply voltage is pumped to
higher levels. The voltage increase caused by the pumping effect depends on:
•
•
•
•
•
Speaker impedance
Supply voltage
Audio signal frequency
Value of decoupling capacitors on supply lines
Source and sink currents of other channels
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
17 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
The pumping effect should not cause a malfunction of either the audio amplifier and/or the
voltage supply source. For instance, this malfunction can be caused by triggering of the
UVP, OVP or UBP of the amplifier. Best remedy for pumping effects is to use the
TDF8591TH in a mono full-bridge application. In case of dual half-bridge application adapt
the supply voltage (e.g. increase supply decoupling capacitors).
12.7 Application schematics
For SE application (see Figure 10):
• A solid ground plane around the TDF8591TH is necessary to prevent emission
• 100 nF Surface Mounted Device (SMD) capacitors must be placed as close as
possible to the supply voltage pins of the TDF8591TH
• The heatsink of the HSOP24 package of the TDF8591TH is connected to pin VSSD
• The external heatsink must be connected to the ground plane
• Use a thermal conductive, electrically isolating Sil-Pad between the backside of the
TDF8591TH and the external heatsink
For BTL application (see Figure 11):
• A solid ground plane around the TDF8591TH is necessary to prevent emission
• 100 nF SMD capacitors must be placed as close as possible to the supply voltage
pins of the TDF8591TH
• The heatsink of the HSOP24 package of the TDF8591TH is connected to pin VSSD
• The external heatsink must be connected to the ground plane
• Use a thermal conductive, electrically isolating Sil-Pad between the backside of the
TDF8591TH and the external heatsink
• The differential inputs enable the best system level audio performance with
unbalanced signal sources. In case of hum due to floating inputs connect the
shielding or source ground to the amplifier ground
• Minimum total required capacity per supply voltage line is 3300 µF
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
18 of 34
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10 Ω
L1 BEAD
VDDA
R1
5.6 kΩ
VDDP
C1
100 nF
C2
47 µF
(35 V)
C3
470 µF
(35 V)
C7
100 nF
C5
47 µF
(35 V)
C6
470 µF
(35 V)
VDDA
C12
C13
100 nF
100 nF
470 nF
R10
C20
5.6 kΩ
470 nF
12
IN1M
VSSP1
VDDP1
14
C10
220 pF
VSSP
2Ω
4Ω
6Ω
8Ω
OUT1
10 µH
22 µH
33 µH
47 µH
1 µF
680 nF
470 nF
330 nF
OUT1P
L3
LS1
R9
22 Ω
BOOT1 C21
15 nF
C22
OUT1M
C24
100 nF
TDF8591TH
22
BOOT2 C27
5
15 nF
C28
220 pF
21
IN2M
LS2
R14
22 Ω
R13
10 Ω
19
19 of 34
© NXP B.V. 2008. All rights reserved.
C35
100 nF
100 nF
FB GND
VSSA
FB
GND
24
18
23
C33
47 pF
C36
100 nF
VSSA
20
VSSP
C31
VSSP2
13
VDDP2
1
C34
VDDA
OUT2M
L4
4
3
FB
GND
OUT2
470 nF
Fig 10. SE application schematic
SINGLE-ENDED
OUTPUT FILTER VALUES
LS1/LS2 L3/L4 C22/C31
C11
220 pF
R7
10 Ω
17
2
VDDA2
5.6 kΩ
VDDP
C37
C38
C39
100 nF
100 nF
100 nF
VDDP
VSSP
C40
220 pF
VDDP
C41
220 pF
OUT2P
C32
100 nF
FB
GND
VSSP
001aah232
TDF8591TH
C30
1 nF
6
11
IN2P
C29
100 nF
STABI
R12
100 nF
15
DIAG
IN2
100 nF
9
SGND1
C26
470 nF
C16
16
VSSA2
5.6 kΩ
C15
C19
220 pF
SGND2
R11
C14
MODE
7
FB GND
C25
1 nF
47 µF
(63 V)
R6
30 kΩ
OSC
VSSA1
VDDA1
5.6 kΩ
C9
100 nF
VSSD
C23
1 nF
C18
VSSP
C8
FB GND
IN1P 10
8
R8
VDDP
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
Rev. 01 — 5 March 2008
C17
1 nF
OPERATE/MUTE
VSSA
VSSA
C4
100 µF
(10 V)
S2
ON/OFF
VSSA
FB GND
R4
5.6 kΩ
S1
R5
10 Ω
IN1
5.6 kΩ
VSSP
L2 BEAD
R3
DZ1
5V6
n.c.
CON1
+25 V VDD
1
GND
2
3
−25 V VSS
NXP Semiconductors
TDF8591TH_1
Product data sheet
VDDP
R2
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
10 Ω
L1 BEAD
VDDA
R1
5.6 kΩ
VDDP
C1
100 nF
C2
47 µF
(35 V)
C3
470 µF
(35 V)
C7
100 nF
C5
47 µF
(35 V)
C6
470 µF
(35 V)
VDDA
C9
100 nF
47 µF
(63 V)
R6
30 kΩ
C14
C15
C16
100 nF
100 nF
100 nF
R10
C20
IN1M
5.6 kΩ
1 µF
SGND1
12
7
6
VSSP1
VDDP1
OSC
VSSA1
VDDA1
1 µF
14
VSSP
9
4Ω
8Ω
10 µH
22 µH
15
1 µF
680 nF
OUT1P
L3
OUT1
LS1
R9
22 Ω
BOOT1 C21
11
15 nF
C22
OUT2M
C24
100 nF
TDF8591TH
SGND2
2
IN2P
22
BOOT2 C27
21
IN2M
L4
OUT2
4
20 of 34
C35
100 nF
100 nF
FB GND
VSSA
FB
GND
23
C33
47 pF
C36
100 nF
VSSA
20
VSSP
C31
VSSP2
18
VDDP2
24
VSSD
n.c.
19
DIAG
VSSA2
13
STABI
© NXP B.V. 2008. All rights reserved.
VDDA2
1
C34
VDDA
R14
22 Ω
R13
10 Ω
C37
C38
C39
100 nF
100 nF
100 nF
VDDP
VSSP
C40
220 pF
VDDP
C41
220 pF
C32
100 nF
FB
GND
VSSP
001aah233
TDF8591TH
3
FB
GND
15 nF
5
C28
220 pF
Fig 11. BTL application schematic
C11
220 pF
BRIDGE-TIED LOAD
OUTPUT FILTER VALUES
LOAD
L
C
R7
10 Ω
16
C25
1 nF
C10
220 pF
17
C19
220 pF
FB GND
VDDP
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
Rev. 01 — 5 March 2008
100 nF
IN1P 10
8
5.6 kΩ
J1
VSSP
C8
FB GND
100 nF
R8
VDDP
C13
FB GND
IN1
OPERATE/MUTE
VSSA
VSSA
C4
100 µF
(10 V)
S2
ON/OFF
VSSA
C12
R4
5.6 kΩ
S1
R5
10 Ω
C23
1 nF
C18
5.6 kΩ
DZ1
5V6
VSSP
L2 BEAD
R3
MODE
CON1
+25 V VDD
1
GND
2
3
−25 V VSS
NXP Semiconductors
TDF8591TH_1
Product data sheet
VDDP
R2
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
12.8 Application graphs
001aah197
102
THD
(%)
001aah196
102
THD
(%)
10
10
1
1
(1)
(1)
10−1
10−1
(2)
(2)
10−2
10−3
10−1
1
10
(3)
10−2
(3)
102
103
10−3
10−1
1
10
102
Po (W)
103
Po (W)
VP = ±27 V; double coils; C = 680 nF.
VP = ±27 V; double coils; C = 680 nF.
(1) f = 10 kHz.
(1) f = 10 kHz.
(2) f = 1 kHz.
(2) f = 1 kHz.
(3) f = 100 Hz.
(3) f = 100 Hz.
a. RL = 4 Ω.
b. RL = 2 Ω.
Fig 12. Total harmonic distortion as a function of output power, SE application
001aah199
102
THD
(%)
001aah198
102
THD
(%)
10
10
1
1
(1)
10−1
10−1
(1)
(2)
(2)
10−2
10−2
(3)
(3)
10−3
10−1
1
10
102
103
10−3
10−1
1
10
102
Po (W)
VP = ±27 V; double coils; C = 680 nF.
103
Po (W)
VP = ±27 V; double coils; C = 680 nF.
(1) f = 10 kHz.
(1) f = 10 kHz.
(2) f = 1 kHz.
(2) f = 1 kHz.
(3) f = 100 Hz.
(3) f = 100 Hz.
a. RL = 8 Ω
b. RL = 4 Ω
Fig 13. Total harmonic distortion as a function of output power, BTL application
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
21 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah200
1
(1)
(2)
(3)
(4)
THD
(%)
THD
(%)
10−1
10−1
10−2
10−2
10−3
10−2
10−1
001aah201
1
1
10−3
10−2
102
10
(1)
(2)
(3)
(4)
10−1
1
f (kHz)
102
10
f (kHz)
Po = 1 W; C = 680 nF; L = 22 µH.
Po = 1 W; C = 680 nF; L = 22 µH.
(1) VP = ±14 V.
(1) VP = ±14 V.
(2) VP = ±18 V.
(2) VP = ±18 V.
(3) VP = ±27 V.
(3) VP = ±27 V.
(4) VP = ±29 V.
(4) VP = ±29 V.
Fig 14. Total harmonic distortion as a function of
frequency, SE application with 2 Ω load
Fig 15. Total harmonic distortion as a function of
frequency, SE application with 4 Ω load
001aah202
1
THD
(%)
10−1
(1)
(2)
(3)
(4)
10−2
10−3
10−2
10−1
1
102
10
f (kHz)
Po = 1 W; C = 680 nF; L = 22 µH.
(1) VP = ±14 V.
(2) VP = ±29 V.
(3) VP = ±18 V.
(4) VP = ±27 V.
Fig 16. Total harmonic distortion as a function of frequency, SE application with 8 Ω load
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
22 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah203
1
(1)
(2)
(3)
(4)
THD
(%)
THD
(%)
10−1
10−1
10−2
10−2
10−3
10−2
10−1
001aah204
1
1
10−3
10−2
102
10
(1)
(2)
(3)
(4)
10−1
1
102
10
f (kHz)
f (kHz)
Po = 1 W; C = 680 nF; L = 22 µH.
Po = 1 W; C = 680 nF; L = 22 µH.
(1) VP = ±14 V.
(1) VP = ±14 V.
(2) VP = ±18 V.
(2) VP = ±18 V.
(3) VP = ±27 V.
(3) VP = ±27 V.
(4) VP = ±29 V.
(4) VP = ±29 V.
Fig 17. Total harmonic distortion as a function of
frequency, BTL application with 2 Ω load
Fig 18. Total harmonic distortion as a function of
frequency, BTL application with 4 Ω load
001aah205
1
THD
(%)
(1)
(2)
(3)
(4)
10−1
10−2
10−3
10−2
10−1
1
102
10
f (kHz)
Po = 1 W; C = 680 nF; L = 22 µH.
(1) VP = ±14 V.
(2) VP = ±18 V.
(3) VP = ±27 V.
(4) VP = ±29 V.
Fig 19. Total harmonic distortion as a function of frequency, BTL application with 8 Ω load
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
23 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah206
100
αcs
(dB)
001aah207
100
αcs
(dB)
80
80
(1)
(2)
(3)
60
60
40
40
20
20
(1)
(2)
(3)
0
10−2
10−1
1
102
10
0
10−2
10−1
1
102
10
f (kHz)
f (kHz)
RL = 4 Ω.
RL = 4 Ω.
(1) VP = ±29 V.
(1) VP = ±27 V.
(2) VP = ±27 V.
(2) VP = ±29 V.
(3) VP = ±14 V.
(3) VP = ±14 V.
a. Channel 2 to channel 1.
b. Channel 1 to channel 2.
Fig 20. Channel separation as a function of frequency, SE application
001aah208
100
CMRR
(dB)
(1)
(2)
(3)
CMRR
(dB)
(1)
(2)
60
20
10−2
001aah209
100
60
10−1
1
102
10
20
10−2
10−1
1
102
10
f (kHz)
f (kHz)
(1) VP = ±29 V.
(1) VP = ±14 V.
(2) VP = ±27 V.
(2) VP = ±29 V.
(3) VP = ±14 V.
(3) VP = ±27 V.
a. Channel 1.
b. Channel 2.
Fig 21. Common mode rejection ratio as a function of frequency, SE application
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
24 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah210
100
CMRR
(dB)
(1)
(2)
60
20
10−2
10−1
1
102
10
f (kHz)
(1) VP = ±14 V.
(2) VP = ±27 V and ±29 V.
Fig 22. Common mode rejection ratio as a function of frequency; BTL application
001aah211
120
SVRR
(dB)
SVRR
(dB)
(1)
(2)
(3)
(4)
100
(1)
(2)
(3)
(4)
100
80
60
10−2
001aah212
120
80
10−1
1
102
10
60
10−2
10−1
1
(1) ripple in antiphase.
(1) ripple on VSS only.
(2) ripple on VDD only.
(2) ripple on VDD only.
(3) ripple on VSS only.
(3) ripple in phase.
(4) ripple in phase.
(4) ripple in antiphase.
a. SE application; RL = 4 Ω
102
10
f (kHz)
f (kHz)
b. BTL application; RL = 8 Ω
Fig 23. Supply voltage ripple rejection as a function of frequency; Standby mode
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
25 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah213
80
(1)
(2)
(3)
(4)
SVRR
(dB)
001aah214
80
SVRR
(dB)
60
60
(1)
(2)
(3)
(4)
40
40
20
0
10−2
10−1
1
102
10
20
10−2
10−1
1
102
10
f (kHz)
f (kHz)
(1) ripple on VDD only.
(1) ripple on VSS only.
(2) ripple in antiphase.
(2) ripple on VDD only.
(3) ripple on VSS only.
(3) ripple in antiphase.
(4) ripple in phase.
(4) ripple in phase.
a. SE application; RL = 4 Ω
b. BTL application; RL = 8 Ω
Fig 24. Supply voltage ripple rejection as a function of frequency; Mute mode
001aah215
80
SVRR
(dB)
SVRR
(dB)
(1)
(2)
(3)
(4)
60
001aah216
80
60
40
(1)
40
(2)
(3)
(4)
20
0
10−2
10−1
1
102
10
20
10−2
10−1
1
f (kHz)
f (kHz)
(1) ripple on VDD only.
(1) ripple in phase.
(2) ripple in antiphase.
(2) ripple on VSS only.
(3) ripple on VSS only.
(3) ripple on VDD only.
(4) ripple in phase.
(4) ripple in antiphase.
a. SE application; RL = 4 Ω
102
10
b. BTL application; RL = 8 Ω
Fig 25. Supply voltage ripple rejection as a function of frequency; Operating mode
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
26 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah217
100
αmute
(dB)
αmute
(dB)
80
80
(1)
(2)
(3)
60
40
20
20
10−1
(1)
(2)
(3)
60
40
0
10−2
001aah218
100
1
0
10−2
102
10
10−1
f (kHz)
1
102
10
f (kHz)
(1) VP = ±14 V.
(1) VP = ±14 V.
(2) VP = ±27 V.
(2) VP = ±27 V.
(3) VP = ±29 V.
(3) VP = ±29 V.
a. Channel 1
b. Channel 2
Fig 26. Mute attenuation as a function of frequency, SE application
001aah219
100
αmute
(dB)
80
(1)
(2)
(3)
60
40
20
0
10−2
10−1
1
102
10
f (kHz)
(1) VP = ±14 V.
(2) VP = ±27 V.
(3) VP = ±29 V.
Fig 27. Mute attenuation as a function of frequency, BTL application
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
27 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah220
200
Po
(W)
Po
(W)
(1)
160
001aah221
120
(1)
80
(2)
(2)
120
80
40
40
0
0
25
35
45
55
65
20
30
40
50
60
VP (V)
70
VP (V)
f = 1 kHz; double coils; C = 680 nF.
f = 1 kHz; double coils; C = 680 nF.
(1) THD = 10 %.
(1) THD = 10 %.
(2) THD = 0.5 %.
(2) THD = 0.5 %.
a. RL = 2 Ω
b. RL = 4 Ω
Fig 28. Output power as a function of supply voltage, SE application
001aah222
400
Po
(W)
001aah223
260
Po
(W)
(1)
300
(1)
180
(2)
(2)
200
100
100
20
0
20
30
40
50
60
70
20
30
40
50
VP (V)
f = 1 kHz; double coils; C = 680 nF.
70
VP (V)
f = 1 kHz; double coils; C = 680 nF.
(1) THD = 10 %.
(1) THD = 10 %.
(2) THD = 0.5 %.
(2) THD = 0.5 %.
a. RL = 4 Ω
60
b. RL = 8 Ω
Fig 29. Output power as a function of supply voltage, BTL application
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
28 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah224
100
001aah225
100
η
(%)
η
(%)
80
80
60
60
40
40
20
20
0
0
0
40
80
120
160
200
Po (W)
a. RL = 2 Ω; VP = ±28 V.
0
40
80
120
Po (W)
b. RL = 4 Ω; VP = ±29 V
Fig 30. Efficiency as a function of output power (one channel), SE application
001aah226
100
η
(%)
001aah227
100
η
(%)
80
80
60
60
40
40
20
20
0
0
0
50
100
150
0
50
Po (W)
a. RL = 4 Ω; VP = ±18 V.
100
150
Po (W)
b. RL = 4 Ω; VP = ±27 V
Fig 31. Efficiency as a function of output power, BTL application
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
29 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
001aah228
40
P
(W)
001aah229
12
P
(W)
30
8
20
4
10
0
0
0
40
80
120
160
200
Po (W)
a. RL = 2 Ω; VP = ±28 V.
0
20
40
60
80
100
Po (W)
b. RL = 4 Ω; VP = ±29 V
Fig 32. Power dissipation as a function of output power (one channel), SE application
001aah230
16
001aah231
20
P
(W)
P
(W)
16
12
12
8
8
4
4
0
0
0
40
80
120
160
0
40
80
Po (W)
120
160
Po (W)
a. RL = 4 Ω; VP = ±18 V.
b. RL = 4 Ω; VP = ±27 V
Fig 33. Power dissipation as a function of output power, BTL application
13. Test information
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for
use in automotive applications.
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
30 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
14. Package outline
HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height
SOT566-3
E
D
A
x
X
c
E2
y
HE
v M A
D1
D2
12
1
pin 1 index
Q
A
A2
E1
(A3)
A4
θ
Lp
detail X
24
13
Z
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
A2
max.
3.5
3.5
3.2
A3
0.35
A4(1)
D1
D2
E(2)
E1
E2
e
HE
Lp
Q
+0.08 0.53 0.32 16.0 13.0
−0.04 0.40 0.23 15.8 12.6
1.1
0.9
11.1
10.9
6.2
5.8
2.9
2.5
1
14.5
13.9
1.1
0.8
1.7
1.5
bp
c
D(2)
v
w
x
y
0.25 0.25 0.03 0.07
Z
θ
2.7
2.2
8°
0°
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-02-18
03-07-23
SOT566-3
Fig 34. Package outline SOT566-3 (HSOP24)
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
31 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
15. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDF8591TH_1
20080305
Product data sheet
-
-
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
32 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
TDF8591TH_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 5 March 2008
33 of 34
TDF8591TH
NXP Semiconductors
2 × 100 W SE (4 Ω) or 1 × 310 W BTL (4 Ω) class-D amplifier
18. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
7
8
9
10
10.1
10.2
11
12
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
13
13.1
14
15
16
16.1
16.2
16.3
16.4
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pulse width modulation frequency . . . . . . . . . . 5
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal foldback . . . . . . . . . . . . . . . . . . . . . . . 6
Overtemperature protection . . . . . . . . . . . . . . . 6
Overcurrent protection . . . . . . . . . . . . . . . . . . . 6
Window protection . . . . . . . . . . . . . . . . . . . . . . 8
Supply voltage protections . . . . . . . . . . . . . . . . 8
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . 9
Differential inputs . . . . . . . . . . . . . . . . . . . . . . . 9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal characteristics. . . . . . . . . . . . . . . . . . 11
Static characteristics. . . . . . . . . . . . . . . . . . . . 11
Dynamic characteristics . . . . . . . . . . . . . . . . . 13
Dynamic characteristics (SE) . . . . . . . . . . . . . 13
Dynamic characteristics (BTL) . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . 15
Application information. . . . . . . . . . . . . . . . . . 15
BTL application . . . . . . . . . . . . . . . . . . . . . . . . 15
Output power estimation. . . . . . . . . . . . . . . . . 15
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Heat sink requirements. . . . . . . . . . . . . . . . . . 17
Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 17
Application schematics . . . . . . . . . . . . . . . . . . 18
Application graphs . . . . . . . . . . . . . . . . . . . . . 21
Test information . . . . . . . . . . . . . . . . . . . . . . . . 30
Quality information . . . . . . . . . . . . . . . . . . . . . 30
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32
Legal information. . . . . . . . . . . . . . . . . . . . . . . 33
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Contact information. . . . . . . . . . . . . . . . . . . . . 33
18
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 March 2008
Document identifier: TDF8591TH_1
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