TJA1081TS,112

TJA1081 FlexRay node transceiver Rev. 5 — 28 November 2012 Product data sheet 1. General description The TJA1081 is a FlexRay node transceiver that is fully compliant with the FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1). In addition, it incorporates features and parameters included in V3.0.1 (see Ref. 2 and Section 14). It is primarily intended for communication systems from 1 Mbit/s to 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1081 features enhanced low-power modes, optimized for ECUs that are permanently connected to the battery. The TJA1081 provides differential transmit capability to the network and differential receive capability to the FlexRay controller. It offers excellent EMC performance as well as high ESD protection. The TJA1081 actively monitors system performance using dedicated error and status information (that can be read by any microcontroller), along with internal voltage and temperature monitoring. The TJA1081 supports mode control as used in the TJA1080A (see Ref. 3). 2. Features and benefits 2.1 Optimized for time triggered communication systems           Compliant with FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1) Automotive product qualification in accordance with AEC-Q100 Data transfer up to 10 Mbit/s Support of 60 ns minimum bit time Very low ElectroMagnetic Emission (EME) to support unshielded cable Differential receiver with wide common-mode range for high ElectroMagnetic Immunity (EMI) Auto I/O level adaptation to host controller supply voltage VIO Can be used in 14 V and 42 V powered systems Instant shut-down interface (via BGE pin) Independent power supply ramp-up for VBAT, VCC and VIO 2.2 Low power management  Low power management including inhibit switch  Very low current in Sleep and Standby modes TJA1081 NXP Semiconductors FlexRay node transceiver  Local and remote wake-up  Supports remote wake-up via dedicated data frames  Wake-up source recognition 2.3 Diagnosis (detection and signalling)       Overtemperature detection Short-circuit on bus lines VBAT power-on flag (first battery connection and cold start) Pin TXEN and pin BGE clamping Undervoltage detection on pins VBAT, VCC and VIO Wake source indication 2.4 Protection  Bus pins protected against 8 kV HBM ESD pulses  Bus pins protected against transients in automotive environment (according to ISO 7637 class C)  Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground  Fail-silent behavior in the event of an undervoltage on pins VBAT, VCC or VIO  Passive behavior of bus lines while the transceiver is not powered 2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1)  Bus driver voltage regulator control  Bus driver - bus guardian control interface  Bus driver logic level adaptation 3. Ordering information Table 1. Ordering information Type number TJA1081TS TJA1081 Product data sheet Package Name Description Version SSOP16 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 2 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 4. Block diagram VIO VCC 3 VBAT 16 11 1 INH TJA1081 15 SIGNAL ROUTER TRANSMITTER 14 BP BM VIO TXD TXEN BGE STBN EN RXD ERRN RXEN 4 5 INPUT VOLTAGE ADAPTATION 7 8 BUS FAILURE DETECTION 2 6 10 9 RXDINT OUTPUT VOLTAGE ADAPTATION STATE MACHINE VBAT WAKE 12 RXDINT NORMAL RECEIVER OVERTEMPERATURE DETECTION WAKE-UP DETECTION OSCILLATOR LOWPOWER RECEIVER UNDERVOLTAGE DETECTION 13 015aaa066 GND Fig 1. Block diagram TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 3 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 5. Pinning information 5.1 Pinning INH 1 EN 2 16 VCC 15 BP 14 BM VIO 3 TXD 4 TXEN 5 RXD 6 11 VBAT BGE 7 10 ERRN STBN 8 13 GND TJA1081 12 WAKE 9 RXEN 015aaa067 Fig 2. Pin configuration 5.2 Pin description Table 2. Symbol TJA1081 Product data sheet Pin description Pin Type Description INH 1 O inhibit output for switching external voltage regulator EN 2 I enable input; enabled when HIGH; internal pull-down VIO 3 P supply voltage for VIO voltage level adaptation TXD 4 I transmit data input; internal pull-down TXEN 5 I transmitter enable input; when HIGH transmitter disabled; internal pull-up RXD 6 O receive data output BGE 7 I bus guardian enable input; when LOW transmitter disabled; internal pull-down STBN 8 I standby input; low-power mode when LOW; internal pull-down RXEN 9 O receive data enable output; when LOW bus activity detected ERRN 10 O error diagnoses output; when LOW error detected VBAT 11 P battery supply voltage WAKE 12 I local wake-up input; internal pull-up or pull-down (depends on voltage at pin WAKE) GND 13 P ground BM 14 I/O bus line minus BP 15 I/O bus line plus VCC 16 P supply voltage (+5 V) All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 4 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 6. Functional description The block diagram of the transceiver is shown in Figure 1. 6.1 Operating modes The TJA1081 supports the following operating modes: • • • • • Normal (normal-power mode) Receive-only (normal-power mode) Standby (low-power mode) Go-to-sleep (low-power mode) Sleep (low-power mode) 6.1.1 Bus activity and idle detection The following mechanisms for activity and idle detection are valid in normal-power modes: • If the absolute differential voltage on the bus lines is higher than Vi(dif)det(act) for tdet(act)(bus), activity is detected on the bus lines and pin RXEN is switched LOW which results in pin RXD being released: – If, after bus activity detection, the differential voltage on the bus lines is higher than VIH(dif), pin RXD will go HIGH – If, after bus activity detection, the differential voltage on the bus lines is lower than VIL(dif), pin RXD will go LOW • If the absolute differential voltage on the bus lines is lower than Vi(dif)det(act) for tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH. This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH) 6.2 Mode control pins: STBN and EN Control inputs STBN and EN are used to select the operating mode. See Table 3 for a detailed description of pin signalling and Figure 3 for the timing diagram. All mode transitions are controlled via the STBN and EN pins, unless an undervoltage condition is detected. If VIO and (VCC or VBAT) are within their operating ranges, pin ERRN indicates the status of the error flag. Operating ranges are: VBAT = 6.5 V to 60 V, VCC = 4.75 V to 5.25 V and VIO = 2.2 V to 5.25 V. Table 3. Pin signalling Mode STBN EN ERRN[1] LOW Normal RXEN RXD HIGH LOW HIGH LOW bus idle Receive-only HIGH HIGH error flag HIGH LOW set error flag reset bus activity Go-to-sleep LOW Standby LOW HIGH error flag [2] LOW set error flag reset Sleep LOW X wake flag wake set[2] flag reset [1] Pin ERRN provides a serial interface for retrieving diagnostic information. [2] Valid if VIO and (VCC or VBAT) are present. TJA1081 Product data sheet Transmitter INH HIGH bus DATA_0 bus DATA_1 enabled or idle disabled wake flag set[2] All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 HIGH wake flag reset float © NXP B.V. 2012. All rights reserved. 5 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver TXD BGE TXEN BP BM RXEN RXD 001aae439 Fig 3. Timing diagram in Normal mode normal receive only standby receive only normal 0.7VIO STBN 0.3VIO tdet(EN) td(STBN-stb) tdet(EN) td(STBN-RXD) EN ERRN 0.7VIO 0.3VIO S2 015aaa068 Fig 4. Timing diagram of control pins EN and STBN The state diagram is shown in Figure 5. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 6 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 1 RECEIVE ONLY NORMAL STBN = HIGH EN = LOW STBN = HIGH EN = HIGH 4 3, 30 15, 25, 42, 43 8, 17, 39 5 6, 33 31, 32 10, 20 11, 21 2 14, 24, 40, 41 7, 16, 38 28, 29 12, 22 19 STANDBY(1) GO-TO-SLEEP STBN = LOW EN = LOW STBN = LOW EN = HIGH 23 9, 18 36, 37 13, 34, 35 26, 44 27, 45 SLEEP STBN = LOW EN = X 001aae438 (1) At the first battery connection the transceiver will enter the Standby mode. Fig 5. State diagram The state transitions are represented with numbers, which correspond with the numbers in column 3 of Table 4 to Table 7. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 7 of 37 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081 Product data sheet Table 4. State transitions forced by EN and STBN  indicates the action that initiates a transaction; 1 and 2  indicated the consequences of a transaction. Transition from mode Direction to mode Normal Rev. 5 — 28 November 2012 All information provided in this document is subject to legal disclaimers. Go-to-sleep Sleep Pin Flag Note STBN EN UVVIO UVVBAT UVVCC PWON Wake Receive-only 1 H L cleared cleared cleared cleared cleared Go-to-sleep 2 L H cleared cleared cleared cleared cleared Standby 3 L L cleared cleared cleared cleared cleared 4 H H cleared cleared cleared X X Go-to-sleep 5 L H cleared cleared cleared X X Standby 6 L L cleared cleared cleared X X Normal 7 H H cleared cleared 2  cleared X 1  cleared [2][3] Receive-only 8 H L cleared cleared 2  cleared X 1  set [2][3] Go-to-sleep 9 L H cleared cleared X X X Normal 10 H H cleared cleared cleared X 1  cleared [2][4] Receive-only 11 H L cleared cleared cleared X 1  set [2][4] Standby 12 L L cleared cleared X X X [4] Sleep 13 L H cleared cleared X X cleared [5] Normal 14 H H 2  cleared 2  cleared 2  cleared X 1  cleared [2][3] Receive-only 15 H L 2  cleared 2  cleared 2  cleared X 1  set [2][3] Receive-only Normal Standby Transition number [1] STBN must be set to LOW at least tdet(EN) after the falling edge on EN. [2] Positive edge on pin STBN sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. [3] Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags. [4] Hold time of go-to-sleep is less than th(gotosleep). [5] Hold time of go-to-sleep becomes greater than th(gotosleep). [1] TJA1081 FlexRay node transceiver 8 of 37 © NXP B.V. 2012. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081 Product data sheet Table 5. State transitions forced by a wake-up  indicates the action that initiates a transaction; 1 and 2  indicated the consequences of a transaction. Transition from mode Direction to mode Transition number Pin STBN EN UVVIO UVVBAT UVVCC PWON Wake Standby Normal 16 H H cleared cleared 1  cleared X  set [1] Receive-only 17 H L cleared cleared 1  cleared X  set [1] Go-to-sleep 18 L H cleared cleared 1  cleared X  set [1] Standby 19 L L cleared cleared 1  cleared X  set [1] Normal 20 H H cleared cleared 1  cleared X  set [1] Receive-only 21 H L cleared cleared 1  cleared X  set [1] Standby 22 L L cleared cleared 1  cleared X  set [1] Go-to-sleep 23 L H cleared cleared 1  cleared X  set [1] Go-to-sleep Rev. 5 — 28 November 2012 All information provided in this document is subject to legal disclaimers. Sleep Flag Note Normal 24 H H 1  cleared 1  cleared 1  cleared X  set [1][2] Receive-only 25 H L 1  cleared 1  cleared 1  cleared X  set [1][2] Standby 26 L L 1  cleared 1  cleared 1  cleared X  set [1] Go-to-sleep 27 L H 1  cleared 1  cleared 1  cleared X  set [1][2] [1] Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags. [2] Transition via Standby mode. TJA1081 FlexRay node transceiver 9 of 37 © NXP B.V. 2012. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081 Product data sheet Table 6. State transitions forced by an undervoltage condition  indicates the action that initiates a transaction; 1 and 2  indicated the consequences of a transaction. Transition from mode Direction to mode Transition number Flag UVVIO UVVBAT UVVCC PWON Wake Normal Sleep 28  set cleared cleared cleared cleared [1] Sleep 29 cleared  set cleared cleared cleared [1] Standby 30 cleared cleared  set cleared cleared [1] Sleep 31  set cleared cleared X 1  cleared [1] Sleep 32 cleared  set cleared X 1  cleared [1] Standby 33 cleared cleared  set X 1  cleared [1] Sleep 34  set cleared cleared X 1  cleared [1] Sleep 35 cleared  set cleared X 1  cleared [1] Sleep 36  set cleared X X 1  cleared [1][2] Sleep 37 cleared  set X X 1  cleared [1][3] Receive-only Go-to-sleep Rev. 5 — 28 November 2012 All information provided in this document is subject to legal disclaimers. Standby [1] UVVIO, UVVBAT or UVVCC detected clears the wake flag. [2] UVVIO overrules UVVCC. [3] UVVBAT overrules UVVCC. Note TJA1081 FlexRay node transceiver 10 of 37 © NXP B.V. 2012. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081 Product data sheet Table 7. State transitions forced by an undervoltage recovery  indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition from mode Direction to mode Transition number Pin STBN EN UVVIO UVVBAT UVVCC PWON Wake Standby Normal 38 H H cleared cleared  cleared X X [1] Receive-only 39 H L cleared cleared  cleared X X [1] Normal 40 H H cleared  cleared cleared X 1  cleared Normal 41 H H  cleared cleared cleared X X Sleep Flag Note [2][3] [4] Rev. 5 — 28 November 2012 All information provided in this document is subject to legal disclaimers. Receive-only 42 H L cleared  cleared cleared X 1  set Receive-only 43 H L  cleared cleared cleared X X Standby 44 L L cleared  cleared cleared X 1  set Sleep 45 L X  cleared cleared cleared X cleared [4] [2][3] [4] [2][3] Go-to-sleep 46 L H cleared  cleared cleared X 1  set [2][3] Sleep 47 L X  cleared cleared cleared X cleared [4] [1] Recovery of UVVCC flag. [2] Recovery of UVVBAT flag. [3] Clearing the UVVBAT flag sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. [4] Recovery of UVVIO flag. TJA1081 FlexRay node transceiver 11 of 37 © NXP B.V. 2012. All rights reserved. TJA1081 NXP Semiconductors FlexRay node transceiver 6.2.1 Normal mode In Normal mode the transceiver is able to transmit and receive data via the bus lines BP and BM. The output of the normal receiver is directly connected to pin RXD. Transmitter behavior in Normal mode, with no time-out present on pins TXEN and BGE and the temperature flag not set (TEMP HIGH = 0; see Table 9), is detailed in Table 8. In this mode, pin INH is set HIGH. Table 8. Transmitter function table BGE TXEN TXD Transmitter L X X transmitter is disabled X H X transmitter is disabled H L H transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW H L L transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH 6.2.2 Receive-only mode In Receive-only mode the transceiver can only receive data. The transmitter is disabled, regardless of the voltage levels on pins BGE and TXEN. In this mode, pin INH is set HIGH. 6.2.3 Standby mode Standby mode is a low-power mode featuring very low current consumption. In this mode, the transceiver cannot transmit or receive data. The low-power receiver is activated to monitor the bus for wake-up patterns. A transition to Standby mode can be triggered by applying the appropriate levels on pins EN and STBN (see Figure 5 and Table 4) or if an undervoltage is detected on pin VCC (see Figure 5 and Section 6.2.5). In this mode, pin INH is set HIGH. If the wake flag is set, pins RXEN and RXD are driven LOW; otherwise pins RXEN and RXD are set HIGH (see Section 6.3). 6.2.4 Go-to-sleep mode In this mode, the transceiver behaves as in Standby mode. If this mode is selected for a time longer than the go-to-sleep hold time (th(gotosleep)) and the wake flag has been previously cleared, the transceiver will enter Sleep mode, regardless of the voltage on pin EN. 6.2.5 Sleep mode Sleep mode is a low-power mode. The only difference between Sleep mode and Standby mode is that pin INH is set floating in Sleep mode. A transition to Sleep mode will be triggered from all other modes if the UVVIO flag or the UVVBAT flag is set (see Table 6). If an undervoltage is detected on pin VCC or VBAT while VIO is present, the wake flag is set by a positive edge on pin STBN, provided that VIO and (VCC or VBAT) are present. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 12 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver The undervoltage flags will be reset when the wake flag is set, and the transceiver will enter the mode indicated by the levels on pins EN and STBN if VIO is present. 6.3 Wake-up mechanism From Sleep mode (pin INH is switched off), the transceiver will enter Standby or Go-to-sleep mode (depending on the level at pin EN) if the wake flag is set. Consequently, pin INH is switched on. If an undervoltage is not detected on pins VIO, VCC and VBAT, the transceiver will switch immediately to the mode indicated by the levels on pins EN and STBN. In Standby, Go-to-sleep and Sleep modes, pins RXD and RXEN are driven LOW if the wake flag is set. 6.3.1 Remote wake-up 6.3.1.1 Bus wake-up via wake-up pattern Bus wake-up is detected if two consecutive DATA_0 of at least tdet(wake)DATA_0 separated by an idle or DATA_1 of at least tdet(wake)idle, followed by an idle or DATA_1 of at least tdet(wake)idle are present on the bus lines within tdet(wake)tot. tdet(wake)tot 0V Vdif −425 mV tdet(wake)Data_0 tdet(wake)idle tdet(wake)Data_0 tdet(wake)idle 001aae442 Fig 6. 6.3.1.2 Bus wake-up timing Bus wake-up via dedicated FlexRay data frame The reception of a dedicated data frame, emulating a valid wake-up pattern, as shown in Figure 7, sets the wake-up flag of the TJA1081. Due to the Byte Start Sequence (BSS), preceding each byte, the DATA_0 and DATA_1 phases for the wake-up symbol are interrupted every 1 s. For 10 Mbit/s the maximum interruption time is 130 ns. Such interruptions do not prevent the transceiver from recognizing the wake-up pattern in the payload of a data frame. The wake-up flag will not be set if an invalid wake-up pattern is received. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 13 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver Vdif 130 ns wake-up 870 ns 870 ns +1500 0V −1500 770 870 870 ns ns ns 130 130 ns ns 5 μs 5 μs 5 μs 5 μs 015aaa043 Each interruption is 130 ns. The transition time from DATA_0 to DATA_1 and from DATA_1 to DATA_0 is about 20 ns. The TJA1081 wake-up flag will be set with the following pattern: FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, FFh Fig 7. Minimum bus pattern for bus wake-up 6.3.2 Local wake-up via pin WAKE If the voltage on pin WAKE is lower than Vth(det)(WAKE) for longer than twake(WAKE) (falling edge on pin WAKE) a local wake-up event on pin WAKE is detected. At the same time, the biasing of this pin is switched to pull-down. If the voltage on pin WAKE is higher than Vth(det)(WAKE) for longer than twake(WAKE), the biasing of this pin is switched to pull-up, and no local wake-up will be detected. pull-up tfltr(WAKE) pull-down pull-up tfltr(WAKE) VBAT WAKE 0V RXD, RXEN and ERRN VBAT INH 0V 015aaa069 Sleep mode: VIO and (VBAT or VCC) still provided. Fig 8. TJA1081 Product data sheet Local wake-up timing via pin WAKE All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 14 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 6.4 Fail-silent behavior In order to be fail silent, undervoltage detection and a reset mechanism for the digital state machine are implemented. If an undervoltage is detected on pins VCC, VIO and/or VBAT, the transceiver will enter a low-power mode. This ensures the passive and defined behavior of the transmitter and receiver when an undervoltage is detected. In the range between the minimum operating voltage and the undervoltage detection threshold, the principle functions of the transmitter and receiver are maintained. However, in this range parameters (e.g. thresholds and delays of the transmitter and receiver) may deviate from the levels specified for the operating range. The digital state machine is supplied by VCC, VIO or VBAT, depending on which voltage is available. Therefore, the digital state machine will be properly supplied as long as the voltage on pin VCC or pin VIO remains above 4.75 V or the voltage on pin VBAT remains above 6.5 V. If the voltage on all pins (i.e. VCC, VIO and VBAT) breaks down, a reset signal will be given to the digital state machine as soon as the internal supply voltage for the digital state machine becomes too low for the proper operation of the state machine. This ensures the passive and defined behavior of the digital state machine in the event of an overall supply voltage breakdown. 6.4.1 VBAT undervoltage If the UVVBAT flag is set, the transceiver will enter Sleep mode (pin INH is switched off) regardless of the voltages present on pins EN and STBN. If the undervoltage recovers, the wake flag will be set and the transceiver will enter the mode determined by the voltages on pins EN and STBN. 6.4.2 VCC undervoltage If the UVVCC flag is set, the transceiver will enter Standby mode regardless of the voltages present on pins EN and STBN. If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is possible. 6.4.3 VIO undervoltage If the voltage on pin VIO is lower than Vuvd(VIO) (even if the UVVIO flag is reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If the UVVIO flag is set, the transceiver will enter Sleep mode (pin INH is switched off). If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is possible. 6.5 Flags 6.5.1 Local wake-up source flag The local wake-up source flag can only be set in a low-power mode. When a wake-up event is detected on pin WAKE (see Section 6.3.2), the local wake-up source flag is set. The local wake-up source flag is reset by entering a low-power mode. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 15 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 6.5.2 Remote wake-up source flag The remote wake-up source flag can only be set in a low-power mode if pin VBAT is within its operating range. When a remote wake-up event is detected on the bus lines (see Section 6.3.1), the remote wake-up source flag is set. The remote wake-up source flag is reset by entering a low-power mode. 6.5.3 Wake flag The wake flag is set if one of the following events occurs: • The local or remote wake-up source flag is set (edge sensitive) • A positive edge is detected on pin STBN when VIO is present • Recovery of the UVVBAT flag The wake flag is reset by entering Normal mode, a low-power mode or by setting one of the undervoltage flags. 6.5.4 Power-on flag The PWON power-on flag is set if the internal supply voltage for the digital part becomes higher than the lowest value it needs to operate. Entering Normal mode resets the PWON flag. 6.5.5 Temperature medium flag The temperature medium flag is set if the junction temperature exceeds Tj(warn)(medium) in a normal-power mode while pin VBAT is within its operating range. The temperature medium flag is reset when the junction temperature drops below Tj(warn)(medium) in a normal-power mode with pin VBAT within its operating range or after a read of the status register in a low-power mode while pin VBAT is within its operating range. No action will be taken if this flag is set. 6.5.6 Temperature high flag The temperature high flag is set if the junction temperature exceeds Tj(dis)(high) in a normal-power mode while pin VBAT is within its operating range. The temperature high flag is reset if a negative edge is applied to pin TXEN while the junction temperature is lower than Tj(dis)(high) in a normal-power mode with pin VBAT within its operating range. If the temperature high flag is set, the transmitter will be disabled. 6.5.7 TXEN_BGE clamped flag The TXEN_BGE clamped flag is set if pin TXEN is LOW and pin BGE is HIGH for longer than tdetCL(TXEN_BGE). The TXEN_BGE clamped flag is reset if pin TXEN is HIGH or pin BGE is LOW. If the TXEN_BGE flag is set, the transmitter is disabled. 6.5.8 Bus error flag The bus error flag is set if pin TXEN is LOW and pin BGE is HIGH and the data received from the bus lines (pins BP and BM) are different to that received on pin TXD. The transmission of any valid communication element, including a wake-up pattern, does not lead to bus error indication. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 16 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver The error flag is reset if the data on the bus lines (pins BP and BM) are the same as on pin TXD or if the transmitter is disabled. No action will be taken if the bus error flag is set. 6.5.9 UVVBAT flag The UVVBAT flag is set if the voltage on pin VBAT is lower than Vuvd(VBAT). The UVVBAT flag is reset if the voltage is higher than Vuvd(VBAT) or by setting the wake flag; see Section 6.4.1. 6.5.10 UVVCC flag The UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than tdet(uv)(VCC). The flag is reset if the voltage on pin VCC is higher than Vuvd(VCC) for longer than trec(uv)(VCC) or the wake flag is set; see Section 6.4.2. 6.5.11 UVVIO flag The UVVIO flag is set if the voltage on pin VIO is lower than Vuvd(VIO) for longer than tdet(uv)(VIO). The flag is reset if the voltage on pin VIO is higher than Vuvd(VIO) or the wake flag is set; see Section 6.4.3. 6.5.12 Error flag The error flag is set if one of the status bits S4 to S10 is set. The error flag is reset if none of the S4 to S10 status bits are set; see Table 9. 6.6 Status register The status register can be read out on pin ERRN by using pin EN as clock; the status bits are given in Table 9. The timing diagram is shown in Figure 9. The status register is accessible if: • UVVIO flag is not set and the voltage on pin VIO is between 4.75 V and 5.25 V • UVVCC flag is not set and the voltage on pin VIO is between 2.2 V and 4.75 V After reading the status register, if no edge is detected on pin EN for longer than tdet(EN), the status bits (S4 to S12) will be cleared if the corresponding flag has been reset. Pin ERRN is LOW if the corresponding status bit is set. Table 9. Status bits Bit number Status bit Description S0 LOCAL WAKEUP local wake-up source flag is redirected to this bit S1 REMOTE WAKEUP remote wake-up source flag is redirected to this bit S2 - not used; always set S3 PWON status bit set means PWON flag has been set previously S4 BUS ERROR status bit set means bus error flag has been set previously S5 TEMP HIGH status bit set means temperature high flag has been set previously S6 TEMP MEDIUM status bit set means temperature medium flag has been set previously S7 TXEN_BGE CLAMPED status bit set means TXEN_BGE clamped flag has been set previously S8 UVVBAT status bit set means UVVBAT flag has been set previously S9 UVVCC status bit set means UVVCC flag has been set previously TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 17 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver Table 9. Status bits …continued Bit number Status bit Description S10 UVVIO status bit set means UVVIO flag has been set previously S11 - not used; always reset S12 - not used; always reset receive only normal 0.7VIO STBN tdet(EN) 0.7VIO EN TEN td(EN-ERRN) 0.7VIO ERRN 0.3VIO S0 S1 S2 001aag896 Fig 9. Timing diagram for status bits TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 18 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 7. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit VBAT battery supply voltage no time limit 0.3 +60 V VCC supply voltage no time limit 0.3 +5.5 V VIO supply voltage on pin VIO no time limit 0.3 +5.5 V VINH voltage on pin INH 0.3 VBAT + 0.3 V IO(INH) output current on pin INH 1 - mA VWAKE voltage on pin WAKE 0.3 VBAT + 0.3 V Io(WAKE) output current on pin WAKE pin GND not connected 15 - mA VBGE voltage on pin BGE no time limit 0.3 +5.5 V VTXEN voltage on pin TXEN no time limit 0.3 +5.5 V VTXD voltage on pin TXD no time limit 0.3 +5.5 V VERRN voltage on pin ERRN no time limit 0.3 VIO + 0.3 V VRXD voltage on pin RXD no time limit 0.3 VIO + 0.3 V VRXEN voltage on pin RXEN no time limit 0.3 VIO + 0.3 V no time limit VEN voltage on pin EN no time limit 0.3 +5.5 V VSTBN voltage on pin STBN no time limit 0.3 +5.5 V VBP voltage on pin BP no time limit 60 +60 V VBM voltage on pin BM no time limit V transient voltage Vtrt on pins BM and BP 60 +60 [1] 100 - V [2] - 75 V [3] 150 - V [4] - 100 V Tstg storage temperature 55 +150 C Tvj virtual junction temperature [5] 40 +150 C electrostatic discharge voltage HBM on pins BP and BM to ground [6] 8.0 +8.0 kV HBM at any other pin [6] 4.0 +4.0 kV MM on all pins [7] 200 +200 V CDM on all pins [8] 1000 +1000 V VESD [1] According to ISO7637, test pulse 1, class C; verified by an external test house. [2] According to ISO7637, test pulse 2a, class C; verified by an external test house. [3] According to ISO7637, test pulse 3a, class C; verified by an external test house. [4] According to ISO7637, test pulse 3b, class C; verified by an external test house. [5] In accordance with IEC 60747-1. An alternative definition of Tvj is: Tvj = Tamb + P  Rth(j-a), where Rth(j-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). [6] HBM: C = 100 pF; R = 1.5 k. [7] MM: C = 200 pF; L = 0.75 H; R = 10 . [8] CDM: R = 1 . TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 19 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 8. Thermal characteristics Table 11. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 118 K/W 9. Static characteristics Table 12. Static characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = 40 C to +150 C; Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit IBAT battery supply current low-power modes; no load on pin INH - - 55 A - - 1 mA Vuvd(VBAT) undervoltage detection voltage on pin VBAT 2.75 - 4.5 V Pin VBAT normal-power modes Pin VCC ICC Vuvd(VCC) low-power modes 1 0 +10 A Normal mode; VBGE = 0 V; VTXEN = VIO; Receive-only mode - - 15 mA Normal mode; VBGE = VIO; VTXEN = 0 V - - 37 mA Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus =   - - 15 mA undervoltage detection voltage on pin VCC (VBAT  5.5 V AND VIO  4.75 V) OR VBAT  6.5 V 2.75 3.7 4.5 V supply current on pin VIO low-power modes 1 +1 +10 A Normal and Receive-only modes; VTXD = VIO - - 1000 A supply current Pin VIO IIO Vuvd(VIO) undervoltage detection voltage on pin VIO 1 1.5 2 V Vuvr(VIO) undervoltage recovery voltage on pin VIO 1 1.6 2.2 V Vuvhys(VIO) undervoltage hysteresis voltage on pin VIO 25 - 200 mV VBAT > 5.5 V Pin EN VIH(EN) HIGH-level input voltage on pin EN 0.7VIO - 5.5 V VIL(EN) LOW-level input voltage on pin EN 0.3 - 0.3VIO V IIH(EN) HIGH-level input current on pin EN VEN = 0.7VIO 3 - 11 A IIL(EN) LOW-level input current on pin EN VEN = 0 V 1 0 +1 A 0.7VIO - 5.5 V Pin STBN VIH(STBN) HIGH-level input voltage on pin STBN TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 20 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver Table 12. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = 40 C to +150 C; Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions VIL(STBN) LOW-level input voltage on pin STBN IIH(STBN) HIGH-level input current on pin STBN IIL(STBN) LOW-level input current on pin STBN Min Typ Max Unit 0.3 - 0.3VIO V VSTBN = 0.7VIO 3 - 11 A VSTBN = 0 V 1 0 +1 A 0.7VIO - 5.5 V Pin TXEN VIH(TXEN) HIGH-level input voltage on pin TXEN VIL(TXEN) LOW-level input voltage on pin TXEN 0.3 - 0.3VIO V IIH(TXEN) HIGH-level input current on pin TXEN VTXEN = VIO 1 0 +1 A IIL(TXEN) LOW-level input current on pin TXEN VTXEN = 0.3VIO 15 - 3 A IL(TXEN) leakage current on pin TXEN VTXEN = 5.25 V; VIO = 0 V 1 0 +1 A Pin BGE VIH(BGE) HIGH-level input voltage on pin BGE 0.7VIO - 5.5 V VIL(BGE) LOW-level input voltage on pin BGE 0.3 - 0.3VIO V IIH(BGE) HIGH-level input current on pin BGE VBGE = 0.7VIO 3 - 11 A IIL(BGE) LOW-level input current on pin BGE VBGE = 0 V 1 0 +1 A VIH(TXD) HIGH-level input voltage on pin TXD normal-power modes 0.7VIO - VIO + 0.3 V VIL(TXD) LOW-level input voltage on pin TXD normal-power modes 0.3 - 0.3VIO V IIH(TXD) HIGH-level input current on pin TXD VTXD = VIO 70 230 650 A IIL(TXD) LOW-level input current on pin TXD normal-power modes; VTXD = 0 V 5 0 +5 A low-power modes 1 0 +1 A ILI(TXD) input leakage current on pin TXD VTXD = 5.25 V; VIO = 0 V 1 0 +1 A - 5 10 pF Pin TXD [1] input capacitance on pin TXD not tested; with respect to all other pins at ground; VTXD = 100 mV; f = 5 MHz IOH(RXD) HIGH-level output current on pin RXD VRXD = VIO  0.4 V; VIO = VCC 20 - 2 mA IOL(RXD) LOW-level output current on pin RXD VRXD = 0.4 V 2 - 20 mA IOH(ERRN) HIGH-level output current on pin ERRN VERRN = VIO  0.4 V; VIO = VCC 1500 600 100 A IOL(ERRN) LOW-level output current on pin ERRN VERRN = 0.4 V 300 700 1500 A IOH(RXEN) HIGH-level output current on pin RXEN VRXEN = VIO  0.4 V; VIO = VCC 4 1.7 0.5 mA IOL(RXEN) LOW-level output current on pin RXEN VRXEN = 0.4 V 1 3.2 8 mA Ci(TXD) Pin RXD Pin ERRN Pin RXEN TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 21 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver Table 12. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = 40 C to +150 C; Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Normal or Receive-only mode; VTXEN = VIO 0.4VCC 0.5VCC 0.6VCC V Standby, Go-to-sleep or Sleep mode 0.1 Normal or Receive-only mode; VTXEN = VIO 0.4VCC 0.5VCC 0.6VCC V Standby, Go-to-sleep or Sleep mode 0.1 0 +0.1 V Pins BP and BM Vo(idle)(BP) Vo(idle)(BM) idle output voltage on pin BP idle output voltage on pin BM 0 +0.1 V Io(idle)BP idle output current on pin BP 60 V  VBP  +60 V; with respect to GND and VBAT 7.5 - +7.5 mA Io(idle)BM idle output current on pin BM 60 V  VBM  +60 V; with respect to GND and VBAT 7.5 - +7.5 mA Vo(idle)(dif) differential idle output voltage 25 0 +25 mV VOH(dif) differential HIGH-level output voltage 40   Rbus  55 ; VCC = 5 V; Cbus = 100 pF 600 850 1500 mV VOL(dif) differential LOW-level output voltage 40   Rbus  55 ; VCC = 5 V; Cbus = 100 pF 1500 850 600 mV VIH(dif) differential HIGH-level input voltage normal-power modes; 10 V  VBP  +15 V; 10 V  VBM  +15 V 150 210 300 mV VIL(dif) differential LOW-level input voltage normal-power modes; 10 V  VBP  +15 V; 10 V  VBM  +15 V 300 210 150 mV low-power modes; 10 V  VBP  +15 V; 10 V  VBM  +15 V 400 210 100 mV normal-power modes; (VBP + VBM) / 2 = 2.5 V - - 10 % Vi(dif)(H-L) differential input volt. diff. betw. HIGHand LOW-levels (abs. value) Vi(dif)det(act) activity detection differential input voltage normal-power modes (absolute value) 150 210 300 mV IO(sc) short-circuit output current (absolute value) on pin BP; 0 V  VBP  60 V - - 35 mA on pin BM; 0 V  VBM  60 V - - 35 mA on pins BP and BM; VBP = VBM: 0 V  VBP  60 V; 0 V  VBM  60 V - - 35 mA Ri(BP) input resistance on pin BP idle level; Rbus =   10 18.5 40 k Ri(BM) input resistance on pin BM idle level; Rbus =   10 18.5 40 k Ri(dif)(BP-BM) differential input resistance between pin BP and pin BM idle level; Rbus =   20 37 80 k ILI(BP) input leakage current on pin BP VBP = 5 V; VBAT = VCC = VIO = 0 V 10 0 +10 A TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 22 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver Table 12. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = 40 C to +150 C; Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit ILI(BM) input leakage current on pin BM VBM = 5 V; VBAT = VCC = VIO = 0 V 10 0 +10 A Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage Rbus = 45  0.4VCC 0.5VCC 0.6VCC V Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage Rbus = 45  0.4VCC 0.5VCC 0.6VCC V Vcm(bus) bus common-mode voltage difference Rbus = 45  25 0 +25 mV - 8 15 pF Ci(BP) input capacitance on pin BP not tested; with respect to all other pins at ground; VBP = 100 mV; f = 5 MHz [1] Ci(BM) input capacitance on pin BM not tested; with respect to all other pins at ground; VBM = 100 mV; f = 5 MHz [1] - 8 15 pF Ci(dif)(BP-BM) differential input capacitance between pin not tested; with respect to BP and pin BM all other pins at ground; V(BM-BP) = 100 mV; f = 5 MHz [1] - 2 5 pF Pin INH VOH(INH) HIGH-level output voltage on pin INH IINH = 0.2 mA VBAT  VBAT  VBAT  V 0.8 0.3 0.1 IL(INH) leakage current on pin INH Sleep mode 5 0 +5 A IOL(INH) LOW-level output current on pin INH VINH = 0 V 15 5 1 mA Pin WAKE Vth(det)(WAKE) detection threshold voltage on pin WAKE low-power mode 2.5 - 4.5 V IIL(WAKE) LOW-level input current on pin WAKE VWAKE = 2.4 V for t > twake(WAKE) 3 - 11 A IIH(WAKE) HIGH-level input current on pin WAKE VWAKE = 4.6 V for t > twake(WAKE) 11 - 3 A Temperature protection Tj(warn)(medium) medium warning junction temperature VBAT > 5.5 V 155 165 175 C Tj(dis)(high) high disable junction temperature VBAT > 5.5 V 180 190 200 C Power-on reset Vth(det)POR power-on reset detection threshold voltage 3.0 - 3.4 V Vth(rec)POR power-on reset recovery threshold voltage 3.1 - 3.5 V Vhys(POR) power-on reset hysteresis voltage 100 - 200 mV [1] These values are based on measurements taken on several samples (less than 10 pieces). These measurements have taken place in the laboratory and have been done at Tamb = 25 C and Tamb = 125 C. No characterization has been done for these parameters. No industrial test will be performed on production products. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 23 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 10. Dynamic characteristics Table 13. Dynamic characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = 40 C to +150 C; Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit delay time from TXD to bus Normal mode - - 50 ns - - 50 ns - - 4 ns DATA_0 - - 50 ns DATA_1 - - 50 ns Pins BP and BM td(TXD-bus) [1] DATA_0 DATA_1 td(TXD-bus) delay time difference from TXD to bus Normal mode; between DATA_0 and DATA_1 td(bus-RXD) delay time from bus to RXD Normal mode; CRXD = 15 pF; see Figure 11 [1] td(bus-RXD) delay time difference from bus to RXD Normal mode CRXD = 15 pF; between DATA_0 and DATA_1; see Figure 11 - - 5 ns td(TXEN-busidle) delay time from TXEN to bus idle Normal mode - 46 80 ns td(TXEN-busact) delay time from TXEN to bus active Normal mode - 39 75 ns td(BGE-busidle) delay time from BGE to bus idle Normal mode - 47 100 ns td(BGE-busact) delay time from BGE to bus active Normal mode - 40 75 ns td(bus)(idle-act) bus delay time from idle to active Normal mode - 7 30 ns td(bus)(act-idle) bus delay time from active to idle Normal mode - 7 30 ns tr(dif)(bus) bus differential rise time 10 % to 90 %; Rbus = 45 ; Cbus = 100 pF 5 17 25 ns tf(dif)(bus) bus differential fall time 90 % to 10 %; Rbus = 45 ; Cbus = 100 pF 5 17 25 ns WAKE symbol detection tdet(wake)DATA_0 DATA_0 wake-up detection time tdet(wake)idle idle wake-up detection time tdet(wake)tot total wake-up detection time Standby or Sleep mode; 10 V  VBP  +15 V; 10 V  VBM  +15 V 1 - 4 s 1 - 4 s 50 - 115 s Undervoltage tdet(uv)(VCC) undervoltage detection time on pin VCC 100 - 670 ms trec(uv)(VCC) undervoltage recovery time on pin VCC 1 - 5.2 ms tdet(uv)(VIO) undervoltage detection time on pin VIO 100 - 670 ms tdet(uv)(VBAT) undervoltage detection time on pin VBAT - - 1 ms Activity detection tdet(act)(bus) activity detection time on bus pins Vdif: 0 mV  400 mV 100 - 250 ns tdet(idle)(bus) idle detection time on bus pins Vdif: 400 mV  0 mV 100 - 245 ns STBN HIGH to RXD HIGH; wake flag set - - 2 s Mode control pins td(STBN-RXD) TJA1081 Product data sheet STBN to RXD delay time All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 24 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver Table 13. Dynamic characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = 40 C to +150 C; Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter td(STBN-stb) th(gotosleep) Conditions Min Typ Max Unit delay time from STBN to standby mode STBN LOW to Standby mode; Receive-only mode[2] - - 10 s go-to-sleep hold time 20 35 50 s 20 - 80 s Status register tdet(EN) detection time on pin EN for mode control TEN time period on pin EN for reading status bits 4 - 20 s td(EN-ERRN) delay time from EN to ERRN for reading status bits - - 2 s wake-up time on pin WAKE low-power modes; falling edge on pin WAKE; 6.5 V  VBAT  27 V 5 28 100 s low-power modes; falling edge on pin WAKE; 27 V < VBAT  60 V 25 75 175 s 2600 - 10400 s WAKE twake(WAKE) Miscellaneous tdetCL(TXEN_BGE) TXEN_BGE clamp detection time [1] Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 ns 1 ns. [2] Same parameter is guaranteed by design for the transition from Normal to Go-to-sleep mode. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 25 of 37 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx td(TXEN-busact) NXP Semiconductors TJA1081 Product data sheet td(TXD-bus) td(TXD-bus) td(BGE-busact) td(TXEN-busidle) td(BGE-busidle) 0.7VIO TXD 0.3VIO 0.7VIO TXEN 0.3VIO 0.7VIO BGE 0.3VIO Rev. 5 — 28 November 2012 All information provided in this document is subject to legal disclaimers. BP and BM 90 % +300 mV 0V −300 mV −150 mV −300 mV −150 mV −300 mV 10 % 0.7VIO RXEN 0.3VIO 0.7VIO RXD 0.3VIO td(bus-RXD) td(bus-RXD) td(bus-RXD) + td(bus-RXD) + tdet(idle)(bus) tdet(act)(bus) td(bus-RXD) + td(bus-RXD) + tdet(idle)(bus) tdet(act)(bus) tr(dif)(bus) tf(dif)(bus) 015aaa143 Fig 10. Detailed timing diagram TJA1081 FlexRay node transceiver 26 of 37 © NXP B.V. 2012. All rights reserved. TJA1081 NXP Semiconductors FlexRay node transceiver Vdif (mV) 22.5 ns 22.5 ns 400 300 37.5 ns −300 −400 60 ns td(bus-RXD) RXD Vdif (mV) td(bus-RXD) 22.5 ns 22.5 ns 400 300 37.5 ns −300 −400 60 ns td(bus-RXD) RXD td(bus-RXD) 015aaa044 Vdif is the receiver test signal. Fig 11. Receiver test signal TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 27 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 11. Test information +12 V +5 V 100 nF 10 μF 3 VIO 16 11 VCC VBAT BP 15 Rbus TJA1081 BM RXD Cbus 14 6 15 pF 015aaa070 Fig 12. Test circuit for dynamic characteristics ISO 7637 G 12 V or 42 V +5 V 100 nF 10 μF 3 VIO 16 VCC 11 VBAT BP 1 nF 15 ISO 7637 Rbus TJA1081 BM Cbus G 14 1 nF 015aaa071 The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2, 3a and 3b. Test conditions: Normal mode: bus idle Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz Standby mode Fig 13. Test circuit for automotive transients TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 28 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 12. Package outline SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT338-1 (SSOP16) TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 29 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 30 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 15. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 31 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 15. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 32 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 14. Appendix 14.1 EPL 3.0.1 requirements implemented in the TJA1081 Table 16. EPL 3.0.1 requirements implemented EPL 3.0.1 parameter Description - wake-up via dedicated data frames RDCLoad transmitter output voltage defined for DC bus load of 40  to 55 /100 pF dBDTx10, dBDTx01 transmitter delay:  75 ns uData0_LP receiver thresholds for detecting DATA_0 in low-power modes: 400 mV (min)/ 100 mV (max) dBDRxai idle reaction time: 50 ns to 275 ns dBDActivityDetection activity detection time 100 ns to 250 ns dBDRxia activity reaction time: 100 ns to 325 ns uData1  uData0 receiver threshold mismatch:  30 mV dBDRx10, dBDRx01 receiver delay:  75 ns dBusRx0BD, dBusRx1BD minimum bit time: 70 ns C_StarTxD, C_BDTxD maximum input capacitance on pin TXD: 10 pF dBDTxRxai idle loop delay:  325 ns - BD_Off mode defined Short circuit currents: iBPBMShortMax,iBMBPShortMax BP shorted to BM: < 60 mA; no time limit iBPGNDShortMax,iBMGNDShortMax BP/BM shorted to ground: < 60 mA; no time limit iBP-5ShortMax,iBM-5ShortMax BP/BM shorted to 5 V: < 60 mA; no time limit iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 27 V: < 60 mA; no time limit iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 48 V: < 72 mA; no time limit iBPBAT60ShortMax,iBMBAT60ShortMax BP/BM shorted to 60 V: < 90 mA; for 400 ms (max) dBDRVCC VCC undervoltage recovery time: 10 ms (max) uINH1Not_Sleep voltage drop from VBAT to INH:  1 V @ 200 A and VBAT  5.5 V iINH1Leak leakage current, when INH is floating: A - Qualification according to AEC-Q100 temperature classes uESDExt 6 kV ESD (min) on pins BP and BM according to HBM (100 pF/1500 ) uESDInt 2 kV ESD (min) on all other pins according to HBM (100 pF/1500 ) TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 33 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 15. Abbreviations Table 17. Abbreviations Abbreviation Description BSS Byte Start Sequence CDM Charged Device Model ECU Electronic Control Unit EMC ElectroMagnetic Compatibility EME ElectroMagnetic Emission EMI ElectroMagnetic Immunity ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TSS Transmission Start Sequence 16. References [1] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 2.1 Rev. A, FlexRay Consortium, Dec. 2005 [2] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 3.0.1, FlexRay Consortium [3] TJA1080A — FlexRay transceiver data sheet, www.nxp.com 17. Revision history Table 18. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1081 v.5 20121128 Product data sheet - TJA1081 v.4 Modifications: • • • Section 6.2 : VBAT, VCC and VIO operating ranges added Table 10: parameter values revised: VBAT, VCC and VIO Table 12: parameter values revised: VIL(dif) TJA1081 v.4 20110224 Product data sheet - TJA1081 v.3 TJA1081 v.3 20090904 Product data sheet - TJA1081 v.2 TJA1081 v.2 20090728 Product data sheet - TJA1081 v.1 TJA1081 v.1 20090415 Preliminary data sheet - - TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 34 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. TJA1081 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 35 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Licenses Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. This NXP product contains functionality that is compliant with the FlexRay specifications. NXP ICs with FlexRay functionality These specifications and the material contained in them, as released by the FlexRay Consortium, are for the purpose of information only. The FlexRay Consortium and the companies that have contributed to the specifications shall not be liable for any use of the specifications. The material contained in these specifications is protected by copyright and other types of Intellectual Property Rights. The commercial exploitation of the material contained in the specifications requires a license to such Intellectual Property Rights. These specifications may be utilized or reproduced without any modification, in any form or by any means, for informational purposes only. For any other purpose, no part of the specifications may be utilized or reproduced, in any form or by any means, without permission in writing from the publisher. The FlexRay specifications have been developed for automotive applications only. They have neither been developed nor tested for non-automotive applications. The word FlexRay and the FlexRay logo are registered trademarks. 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TJA1081 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 36 of 37 TJA1081 NXP Semiconductors FlexRay node transceiver 20. Contents 1 2 2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Optimized for time triggered communication systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Low power management . . . . . . . . . . . . . . . . . 1 2.3 Diagnosis (detection and signalling) . . . . . . . . . 2 2.4 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1 Bus activity and idle detection . . . . . . . . . . . . . 5 6.2 Mode control pins: STBN and EN. . . . . . . . . . . 5 6.2.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.2 Receive-only mode . . . . . . . . . . . . . . . . . . . . . 12 6.2.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.4 Go-to-sleep mode . . . . . . . . . . . . . . . . . . . . . . 12 6.2.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 Wake-up mechanism . . . . . . . . . . . . . . . . . . . 13 6.3.1 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 13 6.3.1.1 Bus wake-up via wake-up pattern. . . . . . . . . . 13 6.3.1.2 Bus wake-up via dedicated FlexRay data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3.2 Local wake-up via pin WAKE . . . . . . . . . . . . . 14 6.4 Fail-silent behavior . . . . . . . . . . . . . . . . . . . . . 15 6.4.1 VBAT undervoltage . . . . . . . . . . . . . . . . . . . . . 15 6.4.2 VCC undervoltage . . . . . . . . . . . . . . . . . . . . . . 15 6.4.3 VIO undervoltage. . . . . . . . . . . . . . . . . . . . . . . 15 6.5 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5.1 Local wake-up source flag . . . . . . . . . . . . . . . 15 6.5.2 Remote wake-up source flag . . . . . . . . . . . . . 16 6.5.3 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5.4 Power-on flag . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5.5 Temperature medium flag . . . . . . . . . . . . . . . . 16 6.5.6 Temperature high flag . . . . . . . . . . . . . . . . . . . 16 6.5.7 TXEN_BGE clamped flag . . . . . . . . . . . . . . . . 16 6.5.8 Bus error flag . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5.9 UVVBAT flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5.10 UVVCC flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5.11 UVVIO flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5.12 Error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 14.1 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 Status register . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPL 3.0.1 requirements implemented in the TJA1081. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 19 20 20 24 28 29 30 30 30 30 31 33 33 34 34 34 35 35 35 35 36 36 36 37 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 November 2012 Document identifier: TJA1081