TJA1101BHN/0Z

TJA1101B 100BASE-T1 PHY for automotive Ethernet Rev. 1 — 1 March 2021 1 Product data sheet General description The TJA1101B is a 100BASE-T1-compliant Ethernet PHY optimized for automotive use cases such as gateways, IP camera links, radar modules, driver assistance systems and back-bone networks. The device provides 100 Mbit/s transmit and receive capability over a single unshielded twisted-pair cable, supporting a cable length of up to at least 15 m. The TJA1101B has been designed for automotive robustness and ISO 26262, ASIL-A compliance, while minimizing power consumption and system costs. Being ASIL-A compliant, adequate safety features have been implemented to ensure that ASIL requirements are met at system level. Additional documentation, including a safety manual, is available on request. The TJA1101B supports OPEN Alliance TC-10-compliant sleep and wake-up request forwarding, with an always-on power domain connected directly to the battery supply without the need for a dedicated voltage regulator. 2 Features and benefits 2.1 General • • • • 100BASE-T1 PHY MII- and RMII-compliant interfaces Compact 36-pin HVQFN package (6 × 6 mm) for PCB space-constrained applications ISO 26262, ASIL-A compliant 2.2 Optimized for automotive use cases • • • • • • • • • • • • Transmitter optimized for capacitive coupling to unshielded twisted-pair cable Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m Enhanced integrated PAM-3 pulse shaping for low RF emissions EMC-optimized output driver strength for MII and RMII MDI pins meet class IV conducted emission limit as per OPEN Alliance EMC Specification 2.0 MDI pins protected against ESD to ±6 kV HBM and ±8 kV IEC61000-4-2 MDI pins protected against transients in automotive environment MDI pins do not need external filtering or ESD protection Automotive-grade temperature range from -40 °C to +125 °C Automotive product qualification in accordance with AEC-Q100 Host-configurable MDI polarity Automated polarity detection and correction TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 2.3 Low-power mode • OPEN Alliance TC-10-compliant sleep and wake-up forwarding – Robust remote wake-up detection via bus lines – Wake-up forwarding at PHY level (supporting global system wake-up) • Inhibit output for voltage regulator control • Dedicated PHY enable/disable input pin to minimize power consumption • Local wake-up pin • Wake-up via SMI-access 2.4 Diagnosis • Signal Quality Indicator for real-time monitoring of link stability and transmitted data quality • Diagnosis of cable errors (shorts and opens) • Gap-free supply undervoltage detection with fail-silent behavior • Internal, external and remote loopback modes 2.5 Miscellaneous • • • • • 3 Reverse MII mode for back-to-back connection of two PHYs On-chip regulators to provide 3.3 V single-supply operation Supports optional 1.8 V external supply for digital core On-chip termination resistors for the differential cable pair Jumbo frame support up to 16 kB Ordering information Table 1. Ordering information Type number TJA1101BHN TJA1101B Product data sheet Package Name Description Version HVQFN36 plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; body 6 × 6 × 0.85 mm SOT1092-2 All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 2 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 4 Block diagram A block diagram of the TJA1101B is shown in Figure 1. The 100BASE-T1 section contains the functional blocks specified in the 100BASE-T1 standard that make up the Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) layer for both the transmit and receive signal paths. The MII/RMII interface (including the Serial Management Interface (SMI)) conforms to IEEE 802.3 clause 22. Additional blocks are defined for mode control, register configuration, interrupt control, system configuration, reset control, local wake-up, remote wake-up, undervoltage detection and configuration control. A number of power-supply-related functional blocks are defined: an internal 1.8 V regulator for the digital core, a Very Low Power (VLP) supply for Sleep mode, the reset circuit, supply monitoring and inhibit control. The clock signals needed for the operation of the PHY are generated in the PLL block, derived from an external crystal or an oscillator input signal. Pin strapping allows a number of default PHY settings (e.g. Master or Slave configuration) to be hardware-configured at power-up. TXER PCS-TX TXEN PMA TRANSMITTER TXD[3:0] TXC RXD[3:0] RMII/MII LOGIC PHY 100BASE-T1 FRONT-END/ HYBRID PHY CONTROL RXDV/CRSDV RXER VDDD(1V8) VDDD(3V3) LDO 1V8 DIG AND 1.8 V/3V3 UV DETECTION SEL_1V8 1V8 SELECT INT_N PHYAD[1:0] RST_N PHY MODE CONTROL TRX_M ACTIVITY DETECT TOP MODE CONTROL AND REGISTERS SMI CONFIG CONTROL BASIC CONTROL BASIC STATUS MODE CONTROL CONFIGURATION INTERRUPT SOURCE INTERRUPT MASK EXTENDED STATUS UV 3V3 DETECTION 1V2 reset RESET CONTROL VDD(IO) VDD(IO) UV 3V3 DETECTION VDDA(3V3) VLP/RESET/ UV VBAT VBAT INH EN CLK_IN_OUT XI XO TRX_P PLL INT_N CONTROL MDC MDIO CONFIG[3:0] PMA RECEIVER PCS-RX RXC/REF_CLK VDDA(TX) VDDA(TX) INH WAKE_IN_OUT XO-OSC/ CLOCK GND aaa-028109 Figure 1. Block diagram TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 3 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 5 Pinning information 5.1 Pinning 28 TXC 29 TXEN 30 TXD3 31 TXD2 32 TXD1 33 TXD0 34 TXER terminal 1 index area 35 EN 36 MDIO The pin configuration of the TJA1101B is shown in Figure 2. Since 100BASE-T1 allows for full-duplex bidirectional communication, the standard MII signals COL and CRS are not needed. MDC 1 27 VDD(IO) INT_N 2 26 GND RST_N 3 25 RXC/REF_CLK SEL_1V8 4 XO 5 XI 6 22 RXD2/CONFIG0 VDDA(3V3) 7 21 RXD3/CONFIG1 WAKE_IN_OUT 8 20 CLK_IN_OUT VBAT 9 19 VDD(IO) 24 RXD0/PHYAD1 RXDV/CONFIG2/CRSDV 18 23 RXD1/PHYAD2 RXER/CONFIG3/TXCLK 17 VDDD(1V8) 16 VDDA(TX) 14 VDDD(3V3) 15 TRX_M 13 TRX_P 12 INH 10 VDDA(TX) 11 TJA1101B Transparent top view aaa-038948 Figure 2. Pin configuration diagram Table 2. Pin description [1] Symbol Pin Type MDC 1 I SMI clock input (weak pull-down) INT_N 2 O interrupt output (active-LOW, open-drain output, level-based) RST_N 3 I reset input (active-LOW, weak pull-up) SEL_1V8 4 I 1.8 V LDO mode selection (external or internal; weak pull-down) XO 5 AO crystal feedback - used in all MII/RMII and Reverse MII modes when a 25 MHz crystal is used XI 6 AI crystal input - used in all MII/RMII and Reverse MII modes when a 25 MHz crystal is used VDDA(3V3) 7 P 3.3 V analog supply voltage WAKE_IN_OUT 8 AIO local/forwarding wake-up input/output (configurable) VBAT 9 P battery supply voltage INH 10 AO inhibit output for voltage regulator control (VBAT-related, active-HIGH) TJA1101B Product data sheet Description All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 4 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 2. Pin description...continued [1] Symbol Pin Type [2] VDDA(TX) 11 P 3.3 V analog supply voltage for the transmitter TRX_P 12 AIO + terminal for transmit/receive signal TRX_M 13 AIO - terminal for transmit/receive signal [2] VDDA(TX) 14 P 3.3 V analog supply voltage for the transmitter VDDD(3V3) 15 P 3.3 V digital supply voltage VDDD(1V8) 16 P 1.8 V digital supply voltage (internally or externally generated; needs to be filtered if generated internally) RXER 17 O MII/RMII receive error output CONFIG3 17 I pin strapping configuration input 3 TXCLK 17 O transmit clock output in test mode and during slave jitter test RXDV 18 O MII receive data valid output CONFIG2 18 I pin strapping configuration input 2 CRSDV 18 O RMII mode: carrier sense/receive data valid output [3] VDD(IO) 19 P 3.3 V I/O supply voltage CLK_IN_OUT 20 IO 25 MHz reference clock input/output (configurable) RXD3 21 O MII mode: receive data output, bit 3 of RXD[3:0] nibble CONFIG1 21 I pin strapping configuration input 1 RXD2 22 O MII mode: receive data output, bit 2 of RXD[3:0] nibble CONFIG0 22 I pin strapping configuration input 0 RXD1 23 O MII mode: receive data output, bit 1 of RXD[3:0] nibble RMII mode: receive data output, bit 1 of RXD[1:0] nibble PHYAD2 23 I pin strapping configuration input for bit 2 of the PHY address used for the SMI address/Cipher scrambler RXD0 24 O MII mode: receive data output, bit 0 of RXD[3:0] nibble RMII mode: receive data output, bit 0 of RXD[1:0] nibble PHYAD1 24 I pin strapping configuration input for bit 1 of the PHY address used for the SMI address/Cipher scrambler RXC 25 O MII mode: external 25 MHz receive clock output I MII reverse mode: 25 MHz receive clock input I RMII mode: interface reference clock input (50 MHz external oscillator) O RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock at input of pin CLK_IN_OUT) REF_CLK GND [4] 25 Description 26 G ground reference [3] VDD(IO) 27 P 3.3 V I/O supply voltage TXC 28 O MII mode: 25 MHz transmit clock output I MII reverse mode: external 25 MHz transmit clock input TXEN 29 I MII/RMII mode: transmit enable input (active-HIGH; weak pull-down) TXD3 30 I MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down) TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 5 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 2. Pin description...continued [1] Symbol Pin Type TXD2 31 I MII mode: transmit data input, bit 2 of TXD[3:0] nibble (weak pull-down) TXD1 32 I MII mode: transmit data input, bit 1 of TXD[3:0] nibble (weak pull-down) RMII mode: transmit data input, bit 1 of TXD[1:0] nibble (weak pull-down) TXD0 33 I MII mode: transmit data input, bit 0 of TXD[3:0] nibble (weak pull-down) RMII mode: transmit data input, bit 0 of TXD[1:0] nibble (weak pull-down) TXER 34 I MII/RMII: transmit error input (weak pull-down) EN 35 I PHY enable input (active-HIGH; weak pull-down) MDIO 36 IO SMI data I/O (weak pull-up) [1] [2] [3] [4] Description AIO: analog input/output; AO: analog output; AI: analog input; I: digital input (VDD(IO) related); O: digital output (VDD(IO) related); IO: digital input/output (VDD(IO) related); P: power supply; G: ground. VDDA(TX) pins are connected internally and should be connected together on the PCB (pins 11 and 14). VDD(IO) pins are connected internally and should be connected together on the PCB (pins 19 and 27). HVQFN36 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is also recommended to connect the exposed center pad to board ground.. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 6 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6 Functional description 6.1 System configuration The TJA1101B contains a 100BASE-T1 compliant Ethernet PHY, with 100 Mbit/s transmit and receive capability over a single unshielded twisted-pair cable. The TJA1101B supports a cable length of up to at least 15 m, with a bit error rate of 1E-10 or less. It is optimized for capacitive signal coupling to the twisted-pair lines. A common-mode choke is typically inserted into the signal path to comply with automotive EMC requirements. The TJA1101B is designed to provide a cost-optimized system solution for automotive Ethernet links. It communicates with the Media Access Control (MAC) unit via the MII or RMII interface. The TJA1101B can operate with a crystal or an external clock. The clock can be forwarded to other PHYs (see Figure 3). The clocking and power supply schemes are independent of each other. The TJA1101B can be powered via a single 3.3 V supply. An internal LDO generates the required 1.8 V supply, requiring only the addition of a decoupling capacitor. When the TJA1101B is used in a switch application with several PHY ports, it may be more efficient to use an external SMPS to provide the 1.8 V supply. In this configuration, the internal LDO is switched off to allow an external supply to be used. The state of SEL_1V8 is captured and copied to bit LDO_MODE (see Table 11) when the device is powered up. A bit value of 0 enables the internal 1.8 V LDO. If LDO_MODE = 1, the internal LDO is disabled and VDDD(1V8) must be supplied externally. The value of LDO_MODE can be changed after power-up via register access. Control and status information is exchanged with the host controller via the SMI interface. The INH output can be used to switch off the external regulator when all ports are in Sleep mode. VBAT 3V3 1V8 INH WAKE_IN_OUT VBAT VREG (R)MII 3V3 EN RST_N TJA1101B TRX_P INT_N CON HOST CONTROLLER MDC TRX_M MDIO XI XO CLK_IN_OUT aaa-038962 Figure 3. Typical TJA1101B switch application circuit TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 7 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.2 MII and RMII The TJA1101B supports a number of MII modes that can be selected via pin strapping or the SMI. The following modes are supported: • MII • RMII (25 MHz XTAL or external 50 MHz via REF_CLK) • Reverse MII (connected externally) Refer to the SMI register description (Section 6.11) for further configuration options. The strength of the (R)MII output driver signals can be limited in all modes (via bit MII_DRIVER; see Table 21) to optimize EMC behavior. 6.2.1 MII The connections between the PHY and the MAC are shown in more detail in Figure 4. Data is exchanged via 4-bit wide data nibbles on TXD[3:0] and RXD[3:0]. Transmit and receive data is synchronized with the transmit (TXC) and receive (RXC) clocks. Both clock signals are provided by the PHY and are typically derived from an external clock or crystal running at a nominal frequency of 25 MHz (±100 ppm). Normal data transmission is initiated with a HIGH level on TXEN, while a HIGH level on RXDV indicates normal data reception. MII encoding is described in Table 3 and Table 4. RXC RXER RXDV PHY RXC RXER RXDV RXD[3:0] RXD[3:0] TXEN TXD[3:0] TXER TXC TXEN TXD[3:0] TXER TXC RXC RXER RXDV MAC/ SWITCH PHY CLK_IN_OUT XO XI 25 MHz RXC RXER RXDV RXD[3:0] RXD[3:0] TXEN TXD[3:0] TXER TXC TXEN TXD[3:0] TXER TXC MAC/ SWITCH CLK_IN_OUT 25 MHz clock to other PHY or switch (optional) XO XI aaa-022105 a. Using external XTAL showing optional 25 MHz clock output 25 MHz clock from other PHY or switch aaa-022106 b. Using external reference clock Figure 4. MII signaling Table 3. MII encoding of TXD[3:0], TXEN and TXER TJA1101B Product data sheet TXEN TXER TXD[3:0] Indication 0 0 0000 through 1111 normal interframe 0 1 0000 through 1111 reserved 1 0 0000 through 1111 normal data transmission 1 1 0000 through 1111 transmit error propagation All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 8 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 4. MII encoding of RXD[3:0], RXDV and RXER RXDV RXER RXD[3:0] Indication 0 0 0000 through 1111 normal interframe 0 1 0000 normal interframe 0 1 0001 through 1101 reserved 0 1 1110 false carrier indication 0 1 1111 reserved 1 0 0000 through 1111 normal data transmission 1 1 0000 through 1111 data reception with errors 6.2.2 RMII 6.2.2.1 Signaling and encoding RMII data is exchanged via 2-bit wide data nibbles on TXD[1:0] and RXD[1:0], as illustrated in Figure 5. To achieve the same data rate as MII, the interface is clocked at a nominal frequency of 50 MHz. A single clock signal, REF_CLK, is provided for both transmitted and received data. This clock signal is provided by the PHY and is typically derived from an external 25 MHz (±100 ppm) crystal (see Figure 5 (a)). Alternatively, a 50 MHz clock signal (±50 ppm) generated by an external oscillator can be connected to pin REF_CLK (see Figure 5 (b)). A third option is to connect a 25 MHz (±100 ppm) clock signal generated by another PHY or switch to pin CLK_IN_OUT (see Figure 5 (c)). RMII encoding is described in Table 5 and Table 6. Table 5. RMII encoding of TXD[1:0], TXEN TXEN TXD[1:0] Indication 0 00 through 11 normal interframe 1 00 through 11 normal data transmission Table 6. RMII encoding of RXD[1:0], CRSDV and RXER TJA1101B Product data sheet CRSDV RXER RXD[1:0] Indication 0 0 00 through 11 normal interframe 0 1 00 normal interframe 0 1 01 through 11 reserved 1 0 00 through 11 normal data transmission 1 1 00 through 11 data reception with errors All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 9 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet PHY CRSDV CRSDV RXD[1:0] RXER RXD[1:0] RXER TXEN TXD[1:0] TXEN TXD[1:0] REF_CLK MAC/ SWITCH PHY REF_CLK CRSDV CRSDV RXD[1:0] RXER RXD[1:0] RXER TXEN TXD[1:0] TXEN TXD[1:0] MAC/ SWITCH CLK_IN_OUT XO REF_CLK XI 25 MHz 25 MHz clock to other PHYs or switch (optional) XO XI 50 MHz oscillator aaa-022189 a. Using external XTAL showing optional 25 MHz clock output PHY CRSDV CRSDV RXD[1:0] RXER RXER TXEN TXEN REF_CLK aaa-022190 b. Using external reference clock RXD[1:0] TXD[1:0] REF_CLK TXD[1:0] MAC/ SWITCH REF_CLK CLK_IN_OUT XO XI 25 MHz clock from other PHY or switch aaa-022191 c. Using externally generated 25 MHz reference clock Figure 5. RMII signaling 6.2.3 Reverse MII In Reverse MII mode, two PHYs are connected back-to-back via the MII interface to realize a repeater function on the physical layer (see Figure 6). The MII signals are crossconnected: RX output signals from one PHY are connected to the TX inputs on the other PHY. The TXC and RXC clock signals become inputs on the PHY connected in Reverse MII mode. Reverse MII mode is selected by setting bits MII_MODE = 11 Since the MII interface is a standard solution, two PHYs could be used to implement two different physical layers to realize, for example, a conversion from Fast Ethernet to 100BASE-T1 and vice versa. Another use case for such a repeater could be to double the link length to 30 m. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 10 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet TXC TXER TXEN TXD[3:0] MDI Fast Ethernet PHY 100Base-TX RXDV RXD[3:0] RXER RXC XO XI 25 MHz XTAL RXC RXER RXDV RXD[3:0] TJA1101B TXEN TXD[3:0] TXER TXC (Reverse MII) XI MDI 100Base-T1 XO 25 MHz XTAL aaa-038995 Figure 6. Fast Ethernet to 100BASE-T1 media converter with TJA1101B in Reverse MII 6.3 System controller 6.3.1 Operating modes 6.3.1.1 Power-off mode The TJA1101B remains in Power-off mode as long as the voltage on pin VBAT is below the power-on reset threshold. The analog blocks are disabled and the digital blocks are in a passive reset state in this mode. 6.3.1.2 Standby mode At power-on, when the voltage on pin VBAT rises above the under-voltage recovery threshold (Vuvr(VBAT)), the TJA1101B enters Standby mode and switches on the INH control output (pin INH HIGH). This control signal may be used to activate the supply to the microcontroller in the ECU. Once the 3.3 V supply voltage is available, the internal 1.8 V regulator is activated (if selected) and the PHY is configured according to the pin strapping implemented on the CONFIGn and PHYADn pins. No SMI access takes place during the power-on settling time (ts(pon)). From an operating point of view, Standby mode corresponds to the IEEE 802.3 Powerdown mode, where the transmit and receive functions (in the PHY) are disabled. Standby mode also acts as a fail-silent mode. The TJA1101B switches to Standby mode when an undervoltage condition is detected on VDDA(3V3), VDDD(3V3), VDDD(1V8) or VDD(IO). 6.3.1.3 Normal mode To establish a communication link, the TJA1101B must be switched to Normal mode, either autonomously (AUTO_OP = 1; see Table 30) or via an SMI command from the host (AUTO_OP = 0). When the TJA1101B is configured for autonomous operation, the PHY enters Normal mode automatically and activates the link on power-on. When the TJA1101B is hostcontrolled, the PHY must be enabled via the SMI. When the PHY is enabled and enters Normal mode, the internal PLL starts running and the transmit and receive functions (both PCS and PMA) are enabled. After a period of stabilization, tinit(PHY), the PHY is ready to set up a link. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 11 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet If link control is enabled (LINK_CONTROL = 1; see Table 20), a PHY configured as Master initiates the training sequence by transmitting an idle pattern. The receiver of a PHY configured as Slave will attempt to synchronize with the idle pattern. Once the descrambler is synchronized (SCR_LOCKED = 1), the slave PHY itself starts sending an idle pattern using the recovered clock signal. The link is established (LINK_STATUS = 1) when the TJA1101B PHY and the remote PHY indicate that their local receiver status is OK. 6.3.1.4 Disable mode When the Ethernet interface is not in use or must be disabled for fail-safe reasons, the PHY can be switched off by pulling pin EN LOW. The PHY is switched off completely in Disable mode, minimizing power consumption. The configuration register settings are maintained. EN must be forced HIGH to exit Disable mode and activate the PHY. 6.3.1.5 Sleep mode If the network manager decides to withdraw a node from the network because it is no longer needed, the PHY can be switched to Sleep mode (powering down the entire ECU). In Sleep mode, the transmit and receive functions are switched off and no signal is driven onto the twisted-pair lines. Transmit requests from the MII interface are ignored and the MII output pins are in a high-ohmic state. The only valid SMI operations in Sleep mode are reading the POWER_MODE status bits in the Extended control register and issuing a Standby mode command (POWER_MODE = 1100; see Table 20). Releasing the INH output (INH LOW) allows the ECU to switch off its main power supply unit. Typically, the entire ECU is powered-down. The TJA1101B is kept partly alive by the permanent battery supply and can still react to activity on the Ethernet lines. Once valid Ethernet idle pulses longer than tdet(PHY) are detected on the lines (with REMWUPHY = 1), the TJA1101B wakes up in Standby mode and switches on the main power unit via the INH control signal. The TJA1101B PHY enters Normal mode via autonomous operation once the supply voltages are stable within their operating ranges, or can be switched to Normal mode via an SMI command if host-controlled. The communication link to the partner can then be re-established. Sleep mode can be entered from Normal mode via the intermediate Sleep Request mode as well as from Standby mode, as shown in Figure 7. Note that the configuration register settings are maintained in Sleep mode. If CLK_IN_OUT is used to provide the clock for other devices (e.g. other PHYs), the clock signal can be configured to remain active (CLK_HOLD = 1) along with INH even when the PHY is in Sleep mode or disabled. When CLK_HOLD = 1, the device enters Sleep mode automatically but remains active until a FORCE_SLEEP SMI command is received. Note that this command forces the PHY to Sleep mode immediately (if it was not already in Sleep mode). 6.3.1.6 Sleep Request mode Sleep Request mode is an intermediate state used to initiate a transition to Sleep mode. In Sleep Request mode, the PHY transmits scrambler code with an encoded LPS command to inform the link partner about the request to enter Sleep mode. The PHY sleep request timer (tto(req)sleep; see Table 37) starts when the TJA1101B enters Sleep Request mode. This timer determines the maximum length of time the PHY TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 12 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet remains in Sleep Request mode. The PHY switches to Sleep mode (via an intermediate step through Silent mode) on receiving LPS confirmation of the sleep request from the Link partner. If the timer expires before confirmation is received from the link partner, the PHY returns to Normal mode. This process is valid when LPS_ACTIVE = 1 and SLEEP_CONFIRM = 1. If bit SLEEP_ACK is not set when the PHY enters Sleep Request mode, it switches back to Normal mode if data is detected on MII or MDI (see Table 21). The DATA_DET_WU flag in the General status register is set and a WAKEUP interrupt is generated (if REMWUPHY = 1). If SLEEP_ACK is set when the PHY enters Sleep Request mode, the PHY sleep acknowledge timer (tto(ack)sleep; see Table 37) is started. While the timer is running, the PHY switches back to Normal mode in response to a host command or wake-up request. When the timer expires, LPS transmission begins to initiate a transition to Sleep mode. Data detected at MII or MDI is ignored. INH is released when the PHY is in Sleep mode. 6.3.1.7 Silent mode Silent mode is an intermediate state between Sleep Request mode and Sleep mode. It is provided to allow time to switch off the transmitter after a sleep request has been accepted before entering Sleep mode. The TJA1101B switches to Sleep mode once the channel goes silent. If the channel remains active for longer than tto(req)sleep, the PHY returns to Normal mode and a SLEEP_ABORT interrupt is generated. 6.3.1.8 Reset mode The TJA1101B switches to Reset mode from any mode except Power-off when pin RST_N is held LOW for at least tdet(rst)(max), provided the voltage on VDD(IO) is above the undervoltage threshold. When RST_N goes HIGH again, or an undervoltage is detected on VDD(IO), the TJA1101B switches to Standby mode. All register bits are reset to their default values in Reset mode and the state of the pin strapping pins is captured. 6.3.2 Status of functional blocks in TJA1101B operating modes Table 7 presents an overview of the status of TJA1101B functional blocks in each operating mode. Table 7. Status of functional blocks in TJA1101B operating modes Functional block [1] Sleep Request Sleep Disable on high-ohmic on high-ohmic high-ohmic PMA/PCS-TX on off on off off PMA/PCS-RX on off on off SMI on Activity detection off LDO_1V8 Product data sheet Standby MII Crystal oscillator TJA1101B Normal on/off [3] on/off [5] on on on off off on/off [5] Rev. 1 — 1 March 2021 on on on/off [3] off on/off [5] off All information provided in this document is subject to legal disclaimers. off [2] [4] off off off off © NXP B.V. 2021. All rights reserved. 13 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 7. Status of functional blocks in TJA1101B operating modes...continued Functional block Normal Standby Sleep Request Sleep Disable RST_N input on on on on EN input on Product data sheet on/off on [6] INT_N output on on on high-ohmic high-ohmic INH output on on on off on/off Temp detection on on on off off [6] [7] on/off off [6] on/off [2] [3] [4] [5] on/off on [6] WAKE_IN_OUT [1] TJA1101B on [6] off off [7] Outputs RXD[3:0], RXER and RXDV are LOW in Standby mode; the other MII pins are configured as inputs via internal 100 kΩ pull-down resistors. Limited access to SMI registers in Sleep mode to allow mode control/wake-up via SMI. VDD(IO) must be available. Configurable; depends on bits CLK_MODE in the Common configuration register. The crystal will be off in Sleep mode unless bit CLK_HOLD = 1 and bits CLK_MODE = 00 or 01. Configurable; VDDD(1V8) can be supplied internally (bit LDO_MODE in the Common configuration register LOW) or externally (bit LDO_MODE HIGH). Configurable. The behavior of the INH output in Disable mode is configurable and depends on bit CONFIG_INH in the Common configuration register. All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 14 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.4 Mode transitions A mode transition diagram for the TJA1101B is shown in Figure 7. Abbreviations used in the mode transition diagram are defined in Table 8. The following events, listed in order of priority, trigger mode transitions: • • • • • • Power on/off Undervoltage on VDD(IO) RST_N input EN input Overtemperature or Undervoltage on VDDA(3V3), VDDD(3V3), VDDD(1V8) SMI command and wake-up (local, remote or forwarding) Table 8. State diagram legend Transition Abbreviation Description Silent to Normal sleep request timer expired t > tto(req)sleep Normal to Sleep Request Sleep Request command POWER_MODE = 1011 autonomous power-down no frame transmission or reception for longer than tto(pd)autn AND AUTO_PWD = 1 LPS code group received LPS_WUR_DIS = 0 (LPS/WUR enabled) AND LPS_RECEIVED = 1 AND t > tto(req)sleep AND LPS_ACTIVE = 1 no data detected on MDI or MII pcs_rx_dv = FALSE AND TXEN = LOW sleep acknowledge timer enabled SLEEP_ACK = 1 Normal mode command POWER_MODE = 0011 wake-up request (FWDPHYREM = 1 and WAKEUP = 1) OR WUR symbols received at the bus pins sleep acknowledge timer disabled SLEEP_ACK = 0 sleep acknowledge time-out time not expired t < tto(ack)sleep data detected on MDI or MII pcs_rx_dv = TRUE OR TXEN = HIGH LPS enabled LPS_WUR_DIS = 0 sleep request timer expired t > tto(req)sleep data detected on MDI or MII pcs_rx_dv = TRUE OR TXEN = HIGH sleep acknowledge timer disabled SLEEP_ACK = 0 LPS disabled LPS_WUR_DIS = 1 sleep request timer expired t > tto(req)sleep Sleep Request to Silent LPS enabled LPS_WUR_DIS = 0 Standby to Normal autonomous operation see Section 6.6 Sleep Request to Normal Normal to Normal Sleep Request to Sleep TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 15 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet sleep request timer expired (t > t to(req)sleep) [Sleep Request command OR autonomous power-down OR (LPS code group received AND (no data detected on MDI or MII OR sleep acknowledge timer enabled))] AND no WUR transmitted or received Sleep Request command AND data detected at MDI or MII AND sleep acknowledge timer disabled SLEEP REQUEST NORMAL INH = on PHY enabled INH = on PHY enabled [(Normal mode command OR wake-up request) AND (sleep acknowledge timer disabled OR sleep acknowledge timer not expired)] OR (data detected at MDI or MII AND sleep acknowledge timer disabled) OR (LPS enabled AND sleep request timer expired) Normal mode command OR autonomous operation OR (FWDPHYREM = 1 AND local wake-up) LPS enabled AND [LPS sent AND (SLEEP_CONFIRM = 0 OR (SLEEP_CONFIRM = 1 AND LPS received)) OR LOC_RCVR_STATUS = 0] SILENT Standby command OR UV(1) OR Overtemperature INH = on PHY enabled (SEND_Z) Standby command OR UV(1) OR Overtemperature LPS disabled AND sleep request timer expired (3) DISABLE INH = on/off(2)) PHY disabled EN pin HIGH OR uv_VDD(IO) STANDBY Sleep Request command OR t > t to(uvd)(4) INH = on PHY disabled Power-on (no uv_VBAT) from any state Power-off (uv_VBAT) POWER-OFF (INH = off) SLEEP INH = off PHY disabled local wake-up OR activity detected OR Standby mode command EN pin LOW AND RST_N HIGH AND no uv_VDD(IO)) AND (Normal OR Standby OR Sleep_Request) no bus activity FORCE_SLEEP = 1 AND no UV RST_N HIGH OR uv_VDD(IO) RST_N LOW AND (no uv_VDD(IO)) from any state other than Power-off or Sleep RESET (INH = no change) aaa-041097 1. UV means undervoltage on one of the power supply pins VDD(IO), VDDA(3V3), VDDD(1V8), VDDD(3V3). 2. INH can be configured to be on or off. 3. The PHY will not be in Sleep mode, and cannot be woken up, until the timeout associated with the transition has expired (after tto(req)sleep). 4. At power-on, after a transition from Power-off to Standby mode, undervoltage detection timeout is enabled once all supply voltages are available. When an undervoltage is detected, the TJA1101B switches to Sleep mode after tto(uvd). Figure 7. Mode transition diagram TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 16 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.5 Sleep and wake-up forwarding concept The sleep and wake-up forwarding concept of the TJA1101B is compliant with the OPEN Alliance Sleep/Wake-up specification. The TJA1101B features a wake-up request forwarding function that enables fast wake-up forwarding without the need for a switch, MAC or μC action. The wake-up forwarding principle is illustrated in Figure 8. The wakeup request can be forwarded via non-active (gray PHYs in the figure) or active links (white PHY). In the case of a non-active link, a wake-up pulse (WUP; duration tw(wake)) is transmitted, to be detected as activity at the link partner. For an active link, wake up request (WUR) scrambler code groups are sent. The wake-up behavior of the PHY can be configured. This arrangement allows WAKE_IN_OUT to be used as a local wake-up or to have a mixed system with only some ports forwarding wake-up requests. The following configuration options are available and are selected via the SMI Configuration register 1 (Table 21): REMWUPHY determines whether the PHY reacts to a remote wake-up request. FWDPHYREM determines whether the PHY forwards a wake-up request (via WAKE_IN_OUT) to its MDI. A WUP or WUR is sent, depending on the link status. LOCWUPHY determines whether the PHY should be woken up in response to a local wake-up event (forwarded via WAKE_IN_OUT) FWDPHYLOC determines whether a wake-up event should be forwarded to other ports (i.e. should the WAKE_IN_OUT signal be activated). The WAKE_IN_OUT signal features a programmable timeout to enable it to support a number of wake-up concepts (e.g. wake-up line). It reacts on a rising edge. The wake-up detection time, tdet(wake) (see Table 37) on pin WAKE_IN_OUT is determined by register bit settings LOC_WU_TIM (see Table 30). The wake-up pulse duration (tp; see Table 37) is also determined by LOC_WU_TIM. VBAT 1.2 V INH WUP pulses PHY µCONTROLLER WUR codes PHY MACs + SWITCH WUP pulses WAKE_IN_OUT 3.3 V PHY aaa-022042 Figure 8. Wake-up request forwarding TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 17 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.6 Autonomous operation When the TJA1101B is configured for autonomous operation (either via pin strapping, see Section 6.10, or via bit AUTO_OP in the Common configuration register, Table 30), it can operate and establish a link without further interaction with a host controller. On power-on or wake-up from Sleep mode, the TJA1101B goes directly to Normal mode once all supply voltages are available and the link-up process starts automatically. Host configuration (e.g. for link or mode control) will not be possible until the device is switched from autonomous to managed operation by resetting bit AUTO_OP. 6.7 Autonomous power-down If autonomous power-down is enabled for the PHY (AUTO_PWD = 1), it goes to Sleep Request mode automatically if no Ethernet frames have been received at the MDI and (R)MII within the timeout time, tto(pd)autn. 6.8 Test modes Five test modes are supported. Only test modes 1, 2, 4 and 5 are included in the 100BASE-T1 specification [1]. The test modes can be selected individually via an SMI command in Normal mode while link control is disabled. Pin RXER is used as a reference clock output for test modes 1 to 4 (the nominal RXER function is disabled when test modes are active). No load should be connected when the reference clock is being measured. 6.8.1 Test mode 1 Test mode 1 is used to test transmitter droop. In Test mode 1, the PHY transmits ‘+1’ symbols for 600 ns followed by ‘-1’ symbols for a further 600 ns. This sequence is repeated continuously. 6.8.2 Test mode 2 Test mode 2 is used to test transmitter timing jitter in Master mode. In Test mode 2, the PHY transmits the data symbol sequence {+1, -1} repeatedly. The transmission of the symbols is synchronized with the local external oscillator. 6.8.3 Test mode 3 Test mode 3 is used to test transmitter timing jitter in Slave mode. In Test mode 3, the PHY transmits the data symbol sequence {+1, -1} repeatedly. The transmission of the symbols is synchronized with the local external oscillator. 6.8.4 Test mode 4 Test mode 4 is used to test transmitter distortion. In Test mode 4, the PHY transmits the sequence of symbols generated by the scrambler polynomial gs1 = 1 + x9 + x11. The bit sequence x0n, x1n is derived from the scrambler according to the following equations: TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 18 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet This stream of 3-bit nibbles is mapped to a stream of ternary symbols according to Table 9. Table 9. Symbol mapping in test mode 4 x1n x0n PAM-3 transmit symbol 0 0 0 0 1 +1 1 0 0 1 1 -1 6.8.5 Test mode 5 Test mode 5 is used to test the transmit PSD mask. In Test mode 5, the PHY transmits a random sequence of PAM-3 symbols. 6.8.6 Slave jitter test To enable the Slave jitter test in Normal mode, bit SLAVE_JITTER_TEST must be set to 1 before link control is enabled (LINK_CONTROL = 1; see Table 20). During this test, the transmitter reference clock is fed to pin TXCLK. 6.9 Error diagnosis 6.9.1 Undervoltage detection The TJA1101B continuously monitors the status of the supply voltages. Once a supply voltage drops below the specified minimum operating threshold, the TJA1101B enters the fail-silent Standby mode and communication is halted. If an undervoltage is detected on VBAT, the TJA1101B switches to Power-off mode. At power-on, after a transition from Power-off to Standby mode, undervoltage detection timeout is enabled once all supply voltages are available. The timeout timer is started when an undervoltage is detected. If the undervoltage is still active when the timer expires (after tto(uvd)), the TJA1101B switches from Standby mode to Sleep mode. The microcontroller can determine the source of the interruption by reading the contents of the External status register (Table 28). The under-voltage detection/recovery range is positioned immediately next to the operating range, without a gap. Since parameters are specified down to the minimum value of the under-voltage detection threshold, it is guaranteed that the behavior of the TJA1101B is fully specified and defined for all possible voltage condition on the supply pins. 6.9.2 Cabling errors The TJA1101B can detect open and short circuits between the twisted-pair bus lines when neither of the link partners is transmitting (link control disabled). It may make sense to run the diagnostic before establishing the Ethernet link. When bit CABLE_TEST in the Extended Control register (Table 20) is set to 1, test pulses are transmitted onto the transmission medium with a repetition rate of 666.6 kHz. The TJA1101B evaluates the reflected signals and uses impedance mismatch data along the channel to determine the quality of the link. The results of the cable test are available in the External status register TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 19 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet (Table 28) within tto(cbl_tst). The tests performed and associated results are summarized in Table 10. Table 10. Cable tests and results The cable bus lines are designated BI_DA+ and BI_DA-, in alignment with 100BASE-T1 [1]. BI_DA+ BI_DA- Result open open open detected + shorted to - - shorted to + short detected shorted to VDD open open detected open shorted to VDD open detected shorted to VDD shorted to VDD short detected shorted to GND open open detected open shorted to GND open detected shorted to GND shorted to GND short detected connected to active link partner connected to active link partner short and open detected (master) (master) 6.9.3 Link stability The Signal Quality Indicator (SQI) is the parameter used to estimate link stability. The PMA receive function monitors the SQI. Once the value falls below a configurable threshold (SQI_FAILLIMIT), the link status is set to FAIL and communication is interrupted. The TJA1101B allows for adjusting the sensitivity of the PMA receive function by configuring this threshold. The microcontroller can always check the current value of the SQI via the SMI, allowing it to track a possible degradation in link stability. 6.9.4 Link-fail counter High losses and/or a noisy channel may cause the link to shut down when reception is no longer reliable. In such cases, the PHY generates a LINK_STATUS_FAIL interrupt. Retraining of the link begins automatically provided link control is enabled (LINK_CONTROL = 1). Bits LOC_RCVR_COUNTER and REM_RCVR_COUNTER in the Link-fail counter register (Table 29) are incremented after every link fail event. Both counters are reset when this register is read. 6.9.5 Jabber detection The Jabber detection function prevents the PHY being locked in the DATA state of the PCS Receive state diagram when the End-of-Stream Delimiters, ESD1 and ESD2, are not detected. The maximum time the PHY can reside in the DATA state is limited to tto(PCS-RX) (rcv_max_timer in the IEEE specification [1]). After this time, the PCS-RX state machine is reset, triggering a transition to PHY Idle state. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 20 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.9.6 Polarity detection A polarity error occurs when the two signal wires in the twisted pair cable are swapped. According to the IEEE specification [1], the polarity is always observed to be correct by the Master PHY; only the Slave is allowed to correct the polarity. When the TJA1101B is in Slave configuration, it can detect if the ternary symbols sent from the Master PHY are received with the wrong polarity and will correct this error internally and set the POLARITY_DETECT bit in the External status register (Table 28). Irrespective of the Master or Slave mode, the host can overwrite and swap the default MDI polarity by setting MDI_POL in Configuration Register 3 (Table 31). 6.9.7 Interleave detection A 100BASE-T1 PHY can send two different interleave sequences of ternary symbols (TAn, TBn) or (TBn, TAn). The receivers in the TJA1101B are able to de-interleave both sequences. The order of the ternary symbols detected by the receiver is indicated by the INTERLEAVE_DETECT bit in the External status register (Table 28). 6.9.8 Loopback modes The TJA1101B supports three loopback modes: • Internal loopback (PCS loopback in accordance with IEEE 802.3bw) • External loopback • Remote loopback To run the PHY in loopback mode, the LOOPBACK control bit in the Basic control register should be set before enabling link control. 6.9.8.1 Internal loopback PMA RECEIVE MDI MUX In Internal loopback mode, the PCS receive function gets the ternary symbols An and Bn directly from the PCS transmit function as shown in Figure 9. This action allows the MAC to compare packets sent through the MII transmit function with packets received from the MII receive function and, therefore, to validate the functionality of the 100BASE-T1 PCS function. PCS RECEIVE MII Receive An, Bn PCS TRANSMIT MII Transmit HYBRID PMA TRANSMIT aaa-019866 Figure 9. Internal loopback 6.9.8.2 External loopback In External loopback mode, the PMA receive function receives signals directly from the PMA transmit function as shown in Figure 10. This external loopback test allows the MAC to compare packets sent through the MII transmit function with packets received from the MII receive function and, therefore, to validate the functionality of the 100BASE-T1 PCS and PMA functions. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 21 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet open PMA RECEIVE PCS RECEIVE MII Receive PMA TRANSMIT PCS TRANSMIT MII Transmit HYBRID aaa-019868 Figure 10. External loopback 6.9.8.3 Remote loopback MAC MII PHY MDI MDI In Remote loopback mode, the packet received by the link partner at the MDI is passed through the PMA receive and PCS receive functions and forwarded to the PCS transmit function, which in turn sends it back to the link partner from where it came. The PCS receive data is made available at the MII. Remote loopback allows the MAC to compare the packets sent to the MDI with the packets received back from the MDI and, therefore, to validate the functionality of the physical channel, including both 100BASE-T1 PHYs. PMA RECEIVE PCS RECEIVE MII Receive PMA TRANSMIT PCS TRANSMIT MII Transmit HYBRID PHY in Remote loopback mode aaa-019869 Figure 11. Remote loopback TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 22 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.10 Hardware configuration A number of pins are provided to allow default values for a number of features to be hardware-configured, without microcontroller interaction. The pull-up/down behavior of these pins is sensed at power-up and after a reset. A pull-up behavior is coded as logic 1, while a pull-down behavior is coded as logic 0. The results are stored in the corresponding SMI registers. All pre-configuration settings (except for the PHY addresses) can be overwritten via SMI commands. Pin strapping at pins 23 (PHYAD2) and 24 (PHYAD1) determines bits 2 and 1, respectively, of the PHY address used for the SMI address/Cipher scrambler. The PHY address cannot be changed once the PHY has been configured. Besides the address configured via pin strapping, the TJA1101B can always be accessed via address 0. Table 11 gives an overview of the functions to be configured via hardware pins. Table 11. Pin strapping configuration Symbol Pin Value Description MASTER_SLAVE 22 (CONFIG0) 0 PHY configured as Slave 1 PHY configured as Master 0 managed operation 1 autonomous operation 00 Normal MII mode 01 RMII mode (50 MHz input on REF_CLK) 10 RMII mode (50 MHz output on REF_CLK) 11 Reverse MII mode 23 (PHYAD2) - bit 2 of PHY address used for the SMI 24 (PHYAD1) - bit 1 of PHY address used for the SMI 4 (SEL_1V8) 0 internal 1.8 V LDO enabled 1 external 1.8 V supply AUTO_OP MII_MODE PHYAD[2:1] LDO_MODE TJA1101B Product data sheet 21 (CONFIG1) 17 (CONFIG3) 18 (CONFIG2) All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 23 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.11 SMI registers 6.11.1 Register mapping overview Table 12. SMI register mapping Register index (dec) Register name Group 0 Basic control register Basic 1 Basic status register Basic 2 PHY identification register 1 Extended 3 PHY identification register 2 Extended 15 Extended status register Extended 16 PHY identification register 3 NXP specific 17 Extended control register NXP specific 18 Configuration register 1 NXP specific 19 Configuration register 2 NXP specific 20 Symbol error counter register NXP specific 21 Interrupt source register NXP specific 22 Interrupt enable register NXP specific 23 Communication status register NXP specific 24 General status register NXP specific 25 External status register NXP specific 26 Link-fail counter register NXP specific 27 Common configuration register NXP specific 28 Configuration register 3 NXP specific Table 13. Register notation TJA1101B Product data sheet Notation Description R/W Read/write R Read only LH Latched HIGH; must be read out to reset LL Latched LOW; must be read out to reset SC Self-clearing PS Pin strapping All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 24 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 6.11.2 TJA1101B registers Table 14. Basic control register (register 0) Bit Symbol Access 15 RESET R/W SC Value software reset control: 0 [1] 1 14 LOOPBACK [2] loopback control: [1] 1 SPEED_SELECT (LSB) R/W AUTONEG_EN R/W SC 11 POWER_DOWN R/W speed select (LSB): 10 Mbit/s if SPEED_SELECT (MSB) = 0 1000 Mbit/s if SPEED_SELECT (MSB) = 1 1 [1] 0 [1] 0 [1] ISOLATE 100 Mbit/s if SPEED_SELECT (MSB) = 0 reserved if SPEED_SELECT (MSB) = 1 Auto negotiation not supported; always 0; a write access is ignored. Standby power down enable: 1 10 normal operation loopback mode [3] 0 12 normal operation PHY reset R/W 0 13 Description normal operation (clearing this bit automatically triggers a transition to Normal mode, provided control bits POWER_MODE are set to 0011 Normal mode, see Table 20) power down and switch to Standby mode (provided ISOLATE = 0; ignored if ISOLATE = 1 and CONTROL_ERR interrupt generated) PHY isolation: R/W 0 [1] 1 normal operation isolate PHY from MII/RMII (provided POWER_DOWN = 0; ignored if POWER_DOWN = 1 and CONTROL_ERR interrupt generated) 9 RE_AUTONEG R/W SC 0 [1] Auto negotiation not supported; always 0; a write access is ignored. 8 DUPLEX_MODE R/W 1 [1] only full duplex supported; always 1; a write access is ignored. 7 COLLISION_TEST R/W 0 [1] COL signal test not supported; always 0; a write access is ignored. 6 SPEED_SELECT (MSB) R/W [3] 0 1 5 UNIDIRECT_EN TJA1101B Product data sheet R/W speed select (MSB): [1] 10 Mbit/s if SPEED_SELECT (LSB) = 0 100 Mbit/s if SPEED_SELECT (LSB) = 1 1000 Mbit/s if SPEED_SELECT (LSB) = 0 reserved if SPEED_SELECT (LSB) = 1 unidirectional enable when bit 12 (AUTONEG_EN) = 0 and bit 8 (DUPLEX_MODE) = 1: All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 25 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 14. Basic control register (register 0)...continued Bit Symbol Access Value 0 Description [1] enable transmit from MII only when the PHY has determined that a valid link has been established 1 4:0 [1] [2] [3] reserved R/W enable transmit from MII regardless of whether the PHY has determined that a valid link has been established 00000 [1] always write 00000; ignore on read Default value. The loopback mode is selected via bits LOOPBACK_MODE in the Extended control register (Table 20). Speed Select: 00: 10 Mbit/s; 01: 100 Mbit/s; 10: 1000 Mbit/s; 11: reserved; a write access value other than 01 is ignored. Table 15. Basic status register (register 1) Bit 15 Symbol 100BASE-T4 Access R Value 0 [1] 1 14 100BASE-X_FD R 0 100BASE-X_HD R 0 10Mbps_FD R 0 10Mbps_HD R 0 100BASE-T2_FD R 0 100BASE-T2_HD R 0 EXTENDED_STATUS R 7 UNIDIRECT_ ABILITY R 6 MF_PREAMBLE_SUPPRESSION R 4 AUTONEG_COMPLETE REMOTE_FAULT TJA1101B Product data sheet R R LH extended status information in register 15h PHY able to transmit from MII only when the PHY has determined that a valid link has been established [1] 0 1 5 no extended status information in register 15h [1] 0 1 PHY not able to perform 100BASE-T2 half-duplex PHY able to perform 100BASE-T2 half-duplex 0 1 PHY not able to perform 100BASE-T2 full-duplex PHY able to perform 100BASE-T2 full-duplex [1] 1 8 PHY not able to perform 10 Mbit/s half-duplex PHY able to perform 10 Mbit/s half-duplex [1] 1 9 PHY not able to perform 10 Mbit/s full-duplex PHY able to perform 10 Mbit/s full-duplex [1] 1 10 PHY not able to perform 100BASE-X half-duplex PHY able to perform 100BASE-X half-duplex [1] 1 11 PHY not able to perform 100BASE-X full-duplex PHY able to perform 100BASE-X full-duplex [1] 1 12 PHY not able to perform 100BASE-T4 PHY able to perform 100BASE-T4 [1] 1 13 Description PHY able to transmit from MII regardless of whether the PHY has determined that a valid link has been established PHY will not accept management frames with preamble suppressed [1] 0 PHY will accept management frames with preamble suppressed Autonegotiation process not completed 1 [1] Autonegotiation process completed 0 [1][2] no remote fault condition detected 1 remote fault condition detected All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 26 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 15. Basic status register (register 1)...continued Bit Symbol 3 Access AUTONEG_ABILITY Value 0 R Description [1] PHY not able to perform Autonegotiation 1 2 LINK_STATUS 1 JABBER_DETECT 0 0 R LL EXTENDED_CAPABILITY 1 R LH 0 R 0 link is down link is up [1][2] 1 1 [1] [2] [3] PHY able to perform Autonegotiation [1][2][3] no jabber condition detected jabber condition detected basic register set capabilities only [1] extended register capabilities Default value. Reset to default value when link control is disabled (LINK_CONTROL = 0). According to IEEE 802.3; LINK_STATUS = 1 when LOC_RCVR_STATUS = 1. Table 16. PHY identification register 1 (register 2) Bit Symbol 15:0 [1] [2] PHY_ID Access R Value 0180h Description [1] [2] bits 3 to 18 of the Organizationally Unique Identifier (OUI) Default value. OUI = 00.60.37h. Table 17. PHY identification register 2 (register 3) Bit Symbol Access Value Description [1] [2] 15:10 PHY_ID R 110111 bits 19 to 24 of the OUI 9:4 TYPE_NO R 010000 six-bit manufacturer’s type number 3:0 [1] [2] REVISION_NO R 0010 [1] four-bit manufacturer’s revision number Default value. OUI = 00.60.37h. Table 18. PHY identification register 3 (Register 16) Bit Symbol Access Value 15:8 reserved R - 7:0 VERSION_NO R xxh [1] [1] Description 8-bit manufacturer's firmware revision number Default value. Table 19. Extended status register (register 15) Bit 15 Symbol 1000BASE-X_FD Access Value R 0 1 TJA1101B Product data sheet [1] Description PHY not able to perform 1000BASE-X full-duplex PHY able to perform 1000BASE-X full-duplex All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 27 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 19. Extended status register (register 15)...continued Bit Symbol 14 Access Value 1000BASE-X_HD 0 R Description [1] PHY not able to perform 1000BASE-X half-duplex 1 13 1000BASE-T_FD 0 R PHY able to perform 1000BASE-X half-duplex [1] PHY not able to perform 1000BASE-T full-duplex 1 12 1000BASE-T_HD 0 R PHY able to perform 1000BASE-T full-duplex [1] PHY not able to perform 1000BASE-T half-duplex 1 PHY able to perform 1000BASE-T half-duplex 11:8 reserved R 0000 7 R 0 100BASE-T1 6 1000BASE-RTPGE 5:0 [1] R reserved R [1] always 0000; ignore on read PHY not able to 1-pair 100BASE-T1 100 Mbit/s 1 [1] PHY able to 1-pair 100BASE-T1 100 Mbit/s 0 [1] PHY not able to support RTPGE 1 PHY supports RTPGE - ignore on read Default value. Table 20. Extended control register (register 17) Bit 15 14:11 Symbol LINK_CONTROL POWER_MODE Access Value Description R/W [1] link control enable: R/W 0 link control disabled 1 link control enabled [2] operating mode select: 0000 10 [4] SLAVE_JITTER_TEST [3] 0011 Normal mode (command) 1001 Silent mode (read only) 1010 Sleep mode (read only) 1011 Sleep Request mode (command) 1100 Standby mode (command) enable/disable Slave jitter test R/W 0 [3] disable Slave jitter test 1 9 TRAINING_RESTART R/W SC enable Slave jitter test Autonegotiation process restart: 0 [3] halts the training phase 1 8:6 [4] TEST_MODE forces a restart of the training phase test mode selection: R/W [3] TJA1101B Product data sheet no change 000 no test mode 001 100BASE-T1 test mode 1 010 100BASE-T1 test mode 2 All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 28 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 20. Extended control register (register 17)...continued Bit Symbol 5 Access CABLE_TEST Value 011 test mode 3 100 100BASE-T1 test mode 4 101 100BASE-T1 test mode 5 110 scrambler and descrambler bypassed 111 reserved; ignore on read TDR-based cable test: R/W SC 0 [3] 1 [4][5] 4:3 LOOPBACK_MODE CONFIG_EN loopback mode select: R/W [3] external loopback 10 external loopback 11 remote loopback 0 [3] 1 reserved R/W 0 WAKE_REQUEST SC configuration register access: configuration register access disabled configuration register access enabled - ignore on read wake-up request configuration: 0 [3] 1 [1] [2] [3] [4] [5] internal loopback 01 [3] R/W 1 stops TDR-based cable test forces TDR-based cable test 00 2 Description no wake-up signal to be transmitted LINK_CONTROL = 0: transmit idle symbols as bus wake-up request LINK_CONTROL = 1: transmit WUR symbols Default value is 0 when AUTO_OP = 0; default value is 1 when AUTO_OP = 1. Any other value generates a CONTROL_ERR interrupt. Default value. Link control must be disabled (LINK_CONTROL = 0) before entering this mode. The selected loopback mode is enabled when bit LOOPBACK in the Basic control register (Table 14) is set to 1. Table 21. Configuration register 1 (register 18) Bit 15 14 Symbol MASTER_SLAVE FWDPHYLOC Access Value Description R/W [1] PHY Master/Slave configuration: 0 PHY configured as Slave 1 PHY configured as Master R/W [2] 0 1 13:12 11 reserved REMWUPHY TJA1101B Product data sheet local wake-up forwarding: wake-up event not forwarded locally [3] wake-up event forwarded locally R/W - ignore on read R/W [2] remote wake-up: All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 29 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 21. Configuration register 1 (register 18)...continued Bit Symbol Access Value 0 1 10 LOCWUPHY R/W PHY does not react to a remote wake-up [3] [2] [4] 0 1 9:8 7 MII_MODE MII_DRIVER R/W RMII mode enabled (50 MHz input on REF_CLK) 10 RMII mode enabled (50 MHz output on REF_CLK) 11 Reverse MII mode MII output driver strength: R/W [3] sleep confirmation setting: [3] LPS/WUR setting: R/W [3] sleep acknowledge: [3] 1 2 reserved FWDPHYREM AUTO_PWD R/W - ignore on read R/W [2] remote wake-up forwarding: LPS_ACTIVE 1 0 [3] Product data sheet remote wake-up event forwarded autonomous power down: R/W autonomous power-down disabled autonomous power-down enabled LPS code group reception: R/W 0 TJA1101B remote wake-up event not forwarded [3] 1 0 sleep acknowledge timer disabled; auto-transition back from Sleep Request mode to Normal mode enabled during data transmission on MII or MDI sleep acknowledge timer enabled; auto-transition back from Sleep Request mode to Normal mode disabled during data transmission on MII or MDI 0 1 LPS/WUR enabled LPS/WUR disabled R/W 0 3 no confirmation needed from another PHY before going to sleep confirmation needed from another PHY before going to sleep 1 SLEEP_ACK standard reduced R/W 0 4 MII mode: 01 1 LPS_WUR_DIS PHY reacts to a local wake-up MII mode enabled 0 5 local wake-up: 00 1 SLEEP_CONFIRM PHY reacts to a remote wake-up PHY does not react to a local wake-up [3] [1] 0 6 Description automatic transition from Normal to Sleep Request when LPS code group received disabled All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 30 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 21. Configuration register 1 (register 18)...continued Bit Symbol Access Value 1 [1] [2] [3] [4] Description [3] automatic transition from Normal to Sleep Request when LPS code group received enabled Default value determined by pin strapping (see Section 6.10). Clear bits FWDPHYLOC, REMWUPHY, LOCWUPHY and FWDPHYREM if the corresponding wake-up/forwarding feature is not being used. Default value. Setting LOCWUPHY has an activation time of tdet(wake). If a wake-up occurs within the activation time, it may not be detected. Table 22. Configuration register 2 (register 19) Bit Symbol Access Value Description PHY address used for the SMI address and for initializing the Cipher scrambler key: PHYAD[4:3] is set to 00 PHYAD[2:1] is predetermined by the hardware configuration straps on pins 23 and 24 respectively PHYAD[0] set to 0 Signal Quality Indicator (SQI) averaging: 15:11 PHYAD[4:0] R [1] 10:9 SQI_AVERAGING R/W [2] 00 01 8:6 SQI_WLIMIT SQI averaged 32 symbols [3] 10 SQI averaged 128 symbols 11 SQI averaged 256 symbols SQI warning limit: R/W 000 [3] 5:3 SQI_FAILLIMIT JUMBO_ENABLE class A SQI warning limit 010 class B SQI warning limit 011 class C SQI warning limit 100 class D SQI warning limit 101 class E SQI warning limit 110 class F SQI warning limit 111 class G SQI warning limit SQI fail limit: R/W TJA1101B Product data sheet R/W no warning limit 001 [3] 2 SQI averaged 64 symbols 000 no fail limit 001 class A SQI fail limit 010 class B SQI fail limit 011 class C SQI fail limit 100 class D SQI fail limit 101 class E SQI fail limit 110 class F SQI fail limit 111 class G SQI fail limit Jumbo packet support: All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 31 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 22. Configuration register 2 (register 19)...continued Bit Symbol Access Value Description 0 1 1:0 SLEEP_REQUEST_TO packets up to 4 kB supported [3] [4] R/W packets up to 16 kB supported sleep request/acknowledge timeout: 00 01 [1] [2] [3] [4] 0.4 ms/0.2 ms [3] 1 ms/0.5 ms 10 4 ms/2 ms 11 16 ms/8 ms Default value determined by pin strapping (see Section 6.10. The SQI is derived from the actual internal slicer margin and includes filtering. Averaging the SQI value itself does not, therefore, have any added value. Default value. The specified values are nominal settings; see parameters tto(req)sleep and tto(ack)sleep, respectively, for the limits. Table 23. Symbol error counter register (register 20) Bit Symbol 15:0 [1] Access SYM_ERR_CNT R Value 0000h Description [1] The symbol error counter is incremented when an invalid code symbol is received (including idle symbols). The counter is incremented only once per packet, even when the received packet contains more than one symbol error. This counter increments up to 16 2 . When the counter overflows, the value FFFFh is retained. The counter is reset when the register is read. Default value. Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0). Table 24. Interrupt source register (register 21) Bit 15 14 13 12 11 10 9 Symbol PWON WAKEUP WUR_RECEIVED LPS_RECEIVED PHY_INIT_FAIL LINK_STATUS_FAIL LINK_STATUS_UP TJA1101B Product data sheet Access R LH R LH R LH R LH R LH R LH R LH Value 0 [1] 1 0 1 no PHY initialization error detected PHY initialization error detected [1][3] 1 0 no LPS code groups received LPS code groups received [1] 1 0 no dedicated wake-up request detected dedicated wake-up request detected [1] 1 0 no local or remote wake-up detected local or remote wake-up detected [1] 1 0 power-on not detected power-on detected [1][2] 1 0 Description link status not changed link status bit LINK_UP changed from ‘link OK’ to ‘link fail’ [1][3] link status not changed link status bit LINK_UP changed from ‘link fail’ to ‘link OK’ All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 32 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 24. Interrupt source register (register 21)...continued Bit Symbol 8 SYM_ERR 7 TRAINING_FAILED 6 SQI_WARNING 5 CONTROL_ERR 4 reserved 3 UV_ERR 2 UV_RECOVERY 1 TEMP_ERR 0 SLEEP_ABORT Access Value 0 R LH [1][3] no symbol error detected 1 0 R LH symbol error detected [1] no training phase failure detected 1 0 R LH training phase failure detected [1][3] SQI value above warning limit 1 R LH 0 R - SQI value below warning limit and bit LINK_UP set [1] no SMI control error detected 1 R LH 0 R LH 0 SMI control error detected ignore on read [1] no undervoltage detected 1 undervoltage detected on VDD(IO), VDDD(3V3), VDDD(1V8) or VDDA(3V3) [1] no undervoltage recovery detected 1 0 R LH undervoltage recovery detected [1] no overtemperature error detected 1 0 R LH overtemperature error detected [1] no transition from Sleep Request back to Normal as a result of the Sleep Request timer expiring 1 [1] [2] [3] Description transition from Sleep Request back to Normal as a result of the Sleep Request timer expiring Default value. Bit WAKEUP may be set when an undervoltage is detected on VDD(IO) in Sleep_Request mode. Ignore this bit when bit UV_VDDIO is set. Bit WAKEUP is reset by a read operation; however wake-up detection will not be enabled again until a state transition has been completed. Interrupts LINK_STATUS_FAIL, LINK_STATUS_UP, SYM_ERR and SQI_WARNING are cleared on entering Sleep Request mode, on entering Standby mode due to an undervoltage and when an undervoltage is detected in Standby mode. Table 25. Interrupt enable register (register 22) Disabling an interrupt source disables signaling at pin INT_N for that interrupt. However, the corresponding bit in the Interrupt source register (Table 24) remains active. Bit Symbol Access Value Description 15 PWON_EN R/W 0 PWON interrupt disabled 14 WAKEUP_EN R/W 1 [1] PWON interrupt enabled 0 [1] WAKEUP interrupt disabled 1 13 WUR_RECEIVED_EN R/W 0 WAKEUP interrupt enabled [1] 1 12 LPS_RECEIVED_EN R/W 0 WUR_RECEIVED interrupt enabled [1] 1 11 PHY_INIT_FAIL_EN TJA1101B Product data sheet R/W 0 WUR_RECEIVED interrupt disabled LPS_RECEIVED interrupt disabled LPS_RECEIVED interrupt enabled [1] PHY_INIT_FAIL interrupt disabled All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 33 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 25. Interrupt enable register (register 22)...continued Disabling an interrupt source disables signaling at pin INT_N for that interrupt. However, the corresponding bit in the Interrupt source register (Table 24) remains active. Bit Symbol 10 Access LINK_STATUS_FAIL_EN Value Description 1 PHY_INIT_FAIL interrupt enabled 0 R/W [1] 1 9 LINK_STATUS_UP_EN 0 R/W LINK_STATUS_FAIL interrupt enabled [1] 1 8 SYM_ERR_EN 0 R/W TRAINING_FAILED_EN 0 R/W SQI_WARNING_EN 0 R/W CONTROL_ERR_EN 0 R/W reserved 3 R/W UV_ERR_EN R/W UV_RECOVERY_EN CONTROL_ERR interrupt enabled 0 always write 0; ignore on read 0 [1] UV_ERR interrupt disabled 0 R/W UV_ERR interrupt enabled [1] 1 1 TEMP_ERR_EN 0 R/W SLEEP_ABORT_EN 0 R/W TEMP_ERR interrupt disabled TEMP_ERR interrupt enabled [1] 1 [1] UV_RECOVERY interrupt disabled UV_RECOVERY interrupt enabled [1] 1 0 CONTROL_ERR interrupt disabled [1] 1 2 SQI_WARNING interrupt disabled SQI_WARNING interrupt enabled [1] 1 4 TRAINING_FAILED interrupt disabled TRAINING_FAILED interrupt enabled [1] 1 5 SYM_ERR interrupt disabled SYM_ERR interrupt enabled [1] 1 6 LINK_STATUS_UP interrupt disabled LINK_STATUS_UP interrupt enabled [1] 1 7 LINK_STATUS_FAIL interrupt disabled SLEEP_ABORT interrupt disabled SLEEP_ABORT interrupt enabled Default value. Table 26. Communication status register (register 23) Bit 15 Symbol LINK_UP Access R Value 0 [1][2] 1 14:13 12 TX_MODE LOC_RCVR_STATUS TJA1101B Product data sheet R R LL Description link failure link OK 00 [1][2] transmitter disabled 01 transmitter in SEND_N mode 10 transmitter in SEND_I mode 11 transmitter in SEND_Z mode 0 1 [1][2] local receiver not OK local receiver OK All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 34 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 26. Communication status register (register 23)...continued Bit Symbol 11 Access REM_RCVR_STATUS 10 SCR_LOCKED Value 0 R LL [1][2] 1 0 R SSD_ERR 8 ESD_ERR 7:5 TRANSMIT_ERR 2:0 [1] [2] PHY_STATE 000 worse than class A SQI (unstable link) 001 class A SQI (unstable link) 010 class B SQI (unstable link) 011 class C SQI (good link) 100 class D SQI (good link; bit error rate < 1e-10) 101 class E SQI (good link) 110 class F SQI (very good link) 111 class G SQI (very good link) 0 [1][2] 1 0 R LH no receive error detected receive error detected since register last read [1][2] 1 no transmit error detected transmit error detected since register last read [1] R no ESD error detected ESD error detected [1][2] R LH no SSD error detected SSD error detected [1][2] 1 R RECEIVE_ERR 3 0 descrambler unlocked descrambler locked [1][2] 1 R LH SQI 4 0 R LH remote receiver not OK remote receiver OK [1][2] 1 9 Description 000 PHY Idle 001 PHY Initializing 010 PHY Configured 011 PHY Offline 100 PHY Active 101 PHY Isolate 110 PHY Cable test 111 PHY Test mode Default value. Reset to default value when link control is disabled (LINK_CONTROL = 0). Table 27. General status register (register 24) Bit 15 Symbol INT_STATUS Access R Value 0 1 TJA1101B Product data sheet [1] Description all interrupts cleared unmasked interrupt pending All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 35 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 27. General status register (register 24)...continued Bit Symbol 14 PLL_LOCKED 13 LOCAL_WU 12 REMOTE_WU 11 DATA_DET_WU Access Value 0 R LL Description [1] PLL unstable and not locked 1 0 R LH PLL stable and locked [1][2] no local wake-up detected 1 0 R LH local wake-up detected [1][2] no remote wake-up detected 1 0 R LH remote wake-up detected [1][3] no 100BASE-T1 data detected at MDI or MII in Sleep Request mode 1 10 EN_STATUS 9 RESET_STATUS 8 reserved 0 R LH 100BASE-T1 data detected at MDI (pcs_rx_dv = TRUE; see [1]) or MII (TXEN = 1) in Sleep Request mode [1] EN HIGH 1 R LH 0 R - EN switched LOW since register last read [1] no hardware reset detected 1 hardware reset detected since register last read ignore on read 7:3 LINKFAIL_CNT R 00000 2:0 reserved R - [1] [2] [3] [4] [1][4] number of link fails since register last read ignore on read Default value. Status bit is cleared by a read operation; however wake-up detection will not be enabled again until a state transition has been completed. Bit DATA_DET_WU may be set when an undervoltage is detected on VDD(IO) in Sleep_Request mode. Ignore this bit when bit UV_VDDIO is set. Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0). Table 28. External status register (register 25) Bit 15 14 13 12 11 10 9 Symbol UV_VDDD_3V3 UV_VDDA_3V3 UV_VDDD_1V8 reserved UV_VDDIO TEMP_HIGH TEMP_WARN TJA1101B Product data sheet Access R LH Value 0 1 R LH 0 R LH 0 R - R LH 0 [1] no undervoltage detected on pin VDDD(1V8) ignore on read [1] no undervoltage detected on pin VDD(IO) undervoltage detected on pin VDD(IO) [1] 1 1 no undervoltage detected on pin VDDA(3V3) undervoltage detected on pin VDDD(1V8) 1 0 no undervoltage detected on pin VDDD(3V3) undervoltage detected on pin VDDA(3V3) 1 0 Description undervoltage detected on pin VDDD(3V3) [1] 1 R LH R LH [1] temperature below high level temperature above high level [1] temperature below warning level temperature above warning level All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 36 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 28. External status register (register 25)...continued Bit Symbol 8 Access SHORT_DETECT 7 0 R LH OPEN_DETECT 6 Value no short circuit detected 1 0 R LH POLARITY_DETECT Description [2] short circuit detected since register last read [2] no open circuit detected 1 0 R open circuit detected since register last read [2] no polarity inversion detected at MDI 1 5 4:0 [1] [2] 0 INTERLEAVE_DETECT R reserved R polarity inversion detected at MDI [2] interleave order of detected ternary symbols: TAn, TBn 1 interleave order of detected ternary symbols: TBn, TAn - ignore on read Default value. Default value; bit NOT reset to default value when link control is disabled (LINK_CONTROL = 0). Table 29. Link fail counter register (register 26) Bit Symbol Access Value The counter is incremented when local receiver is NOT_OK; when the counter overflows, the value FFh is retained. The counter is reset when the register is read. [1][2] The counter is incremented when remote receiver is NOT_OK; when the counter overflows, the value FFh is retained. The counter is reset when the register is read. 15:8 LOC_RCVR_CNT R 00h 7:0 REM_RCVR_CNT R 00h [1] [2] Description [1][2] Default value. Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0). Table 30. Common configuration register (register 27) Bit 15 Symbol AUTO_OP Access Value Description R/W [1] managed/autonomous operation: 14 reserved R/W 13:12 CLK_MODE R/W 0 managed operation 1 autonomous operation - clock mode: 00 11 LDO_MODE TJA1101B Product data sheet R/W ignore on read [2] 25 MHz XTAL; no clock at CLK_IN_OUT 01 25 MHz XTAL; 25 MHz output at CLK_IN_OUT 10 25 MHz external clock at CLK_IN_OUT 11 50 MHz input at REF_CLK; RMII mode only; no XTAL; no clock at CLK_IN_OUT [1] LDO mode: 0 internal 1.8 V LDO enabled 1 external 1.8 V supply All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 37 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 30. Common configuration register (register 27)...continued Bit Symbol Access 10 CLK_DRIVER R/W Value Description output driver strength on CLK_IN_OUT: 0 [2] standard output driver strength at output of CLK_IN_OUT 1 9 CLK_HOLD reduced output driver strength at output of CLK_IN_OUT local wake-up: R/W 0 [2] XTAL and CLK_IN_OUT output switched off in Sleep mode 1 8:7 LOC_WU_TIM XTAL and CLK_IN_OUT output remain active until device switched to Sleep mode via SMI local wake-up timer: R/W 00 6 CONFIG_WAKE [2] longest (10 ms to 20 ms) 01 long (250 μs to 500 μs) 10 short (100 μs to 200 μs) 11 shortest (10 μs to 40 μs) local wake configuration: R/W 0 1 5 CONFIG_INH absolute input threshold [2] ratiometric input threshold (VDD(IO)) INH configuration: R/W 0 1 4:0 [1] [2] reserved R/W INH switched off in Disable mode [2] INH switched on in Disable mode - ignore on read Default value determined by pin strapping (see Section 6.10). Default value. Table 31. Configuration register 3 (register 28) Bit Symbol Access Value Description 15:3 reserved R/W - ignore on read 2 MDI_POL R/W MDI polarity: 0 [1] 1 1 FORCE_SLEEP R/W SC swapped polarity: pin 12 = TRX_M; pin 13 = TRX_P forced sleep operation: 0 [1] 1 0 [1] reserved R/W regular polarity: pin 12 = TRX_P; pin 13 = TRX_M 1 forced sleep inactive force PHY to Sleep mode [1] always write 1; ignore on read Default value. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 38 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 7 Limiting values Table 32. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter Vx IO(INH) Vtrt [1] voltage on pin x Conditions Min Max Unit on pin VBAT -0.3 +40 V on pin INH -0.3 VBAT + 0.3 V on pin WAKE_IN_OUT -36 +42 V on pins VDDA(3V3), VDDA(TX), VDDD(3V3), VDD(IO), TRX_P, TRX_M -0.3 +4.6 V on pins VDDD(1V8), XI, XO -0.3 +2.5 V on input pins MDC, MDIO, RST_N, INT_N, EN, CLK_IN_OUT, SEL_1V8 and MII digital input pins -0.3 min(VDD(IO) + 0.3, +4.6) V on digital output pins -0.3 VDD(IO) + 0.3 V -2 - mA pulse 1 -100 - V pulse 2a - 75 V pulse 3a -150 - V - 100 V output current on pin INH transient voltage on pins WAKE_IN_OUT, VBAT, TRX_P, TRX_M [2] pulse 3b VESD electrostatic discharge voltage IEC 61000-4-2; 150 pF, 330 Ω [3] on pins TRX_P, TRX_M [4] -8.0 +8.0 kV on pin WAKE_IN_OUT [5] -8.0 +8.0 kV on pin VBAT to GND [6] -8.0 +8.0 kV [7] -2.0 +2.0 kV Human Body Model (HBM) on any pin on pins TRX_P, TRX_M -6.0 +6.0 kV on pin WAKE_IN_OUT [8] -6.0 +6.0 kV on pin VBAT [9] -6.0 +6.0 kV [10] -500 +500 V Charged Device Model (CDM) on any pin Tamb ambient temperature -40 +125 °C Tstg storage temperature -55 +150 °C [1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these values. [2] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637. [3] Verified by an external test house according to IEC TS 62228, Section 4.3. [4] Tested with a common mode choke and 100 nF coupling capacitors. [5] Tested with 10 nF capacitor to GND and 10 kΩ in series between the capacitor and the WAKE_IN_OUT pin. [6] Tested with 100 nF capacitor from VBAT to GND. [7] According to AEC-Q100-002. [8] With 10 nF capacitor to GND and 10 kΩ in series between the capacitor and the WAKE_IN_OUT pin. [9] With 100 nF from VBAT to GND. [10] According to AEC-Q100-011. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 39 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 8 Thermal characteristics Table 33. Thermal characteristics Symbol Rth(j-a) Rth(j-c) Ψj-top [1] [2] Parameter Conditions thermal resistance from junction to ambient thermal resistance from junction to case thermal characterization parameter from junction to top of package [1] [2] [1] Typ Unit LDO disabled (LDO_MODE = 1) 30 K/W LDO enabled (LDO_MODE = 0) 34 K/W LDO disabled (LDO_MODE = 1) 5 K/W LDO enabled (LDO_MODE = 0) 10 K/W LDO disabled (LDO_MODE = 1) 2 K/W LDO enabled (LDO_MODE = 0) 7 K/W HVQFN36 package; in free air HVQFN36 package; in free air HVQFN36 package; in free air According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers ( thickness: 35 μm) and thermal via array under the exposed pad connected to the first inner copper layer. Determined using an isothermal cold plate. 9 Static characteristics Table 34. Supply characteristics Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit operating range 3.1 - 36 V Battery supply: pin VBAT VBAT battery supply voltage Vuvd undervoltage detection voltage 2.8 - - V Vuvr undervoltage recovery voltage - - 3.1 V Vuvhys undervoltage hysteresis voltage 15 100 - mV IBAT battery supply current all modes except Sleep; VBAT < 36 V; IINH = 0 μA - - 2.0 mA Sleep mode; Tvj ≤ 85 °C; VBAT < 7.4 V - 130 300 μA Sleep mode; Tvj ≤ 85 °C; 7.4 V < VBAT < 30 V - 45 100 μA VBAT < 40 V; IINH = 0 μA - - 6 mA operating range 3.1 3.3 3.5 V 3.3 V analog supply: pin VDDA(3V3) VDDA(3V3) analog supply voltage (3.3 V) Vuvd undervoltage detection voltage 2.9 - - V Vuvr undervoltage recovery voltage - - 3.1 V Vuvhys undervoltage hysteresis voltage 50 80 - mV IDDA(3V3) analog supply current (3.3 V) - 21 27 mA TJA1101B Product data sheet Normal/Sleep Request modes All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 40 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 34. Supply characteristics...continued Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Standby mode - 75 150 μA Disable/Reset modes - 4 50 μA operating range 3.1 3.3 3.5 V 3.3 V digital supply: pin VDDD(3V3) VDDD(3V3) digital supply voltage (3.3 V) Vuvd undervoltage detection voltage 2.9 - - V Vuvr undervoltage recovery voltage - - 3.1 V Vuvhys undervoltage hysteresis voltage 50 80 - mV IDDD(3V3) digital supply current (3.3 V) Normal/Sleep Request modes; LDO_MODE = 0 - 50 60 mA Normal/Sleep Request modes; LDO_MODE = 1 - 2.5 4 mA Standby mode; LDO_MODE = 0 - 0.2 5 mA Disable/Reset modes - 1 50 μA 1.8 V digital supply: pin VDDD(1V8) VDDD(1V8) digital supply voltage (1.8 V) operating range; LDO_MODE = 1 1.745 1.84 1.95 V Vuvd undervoltage detection voltage LDO_MODE = 1 1.65 - - V Vuvr undervoltage recovery voltage LDO_MODE = 1 - - 1.745 V Vuvhys undervoltage hysteresis voltage LDO_MODE = 1 20 35 - mV - 46 55 mA IDDD(1V8) digital supply current (1.8 V) Normal/Sleep Request modes; LDO_MODE = 1 [1] Transmitter analog supply: pins VDDA(TX) VDDA(TX) transmitter analog supply voltage operating range 3.1 3.3 3.5 V IDDA(TX) transmitter analog supply current Normal/Sleep Request modes - 27 33 mA Standby/Disable/Reset modes - 0 50 μA operating range 3.1 3.3 3.5 V Input/output supply: pin VDD(IO) VDD(IO) input/output supply voltage Vuvd undervoltage detection voltage 2.9 - - V Vuvr undervoltage recovery voltage - - 3.1 V Vuvhys undervoltage hysteresis voltage 50 80 - mV - 5 7.5 mA Standby/Disable modes; no currents in pull-up resistors on digital inputs - 3 25 μA Reset mode; no currents in pullup resistors on digital inputs - 35 80 μA IDD(IO) input/output supply current TJA1101B Product data sheet Normal/Sleep Request modes; Cload on MII pins = 15 pF All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 [1] © NXP B.V. 2021. All rights reserved. 41 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 34. Supply characteristics...continued Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Normal/Sleep Request modes; LDO_MODE = 0 - 360 480 mW Normal/Sleep Request modes; LDO_MODE = 1 - 290 400 mW Power consumption P [1] power dissipation Not measured in production; guaranteed by design. Table 35. xMI interfaces characteristics Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit 2 - - V SMI interface: pins MDC and MDIO VIH HIGH-level input voltage VIL LOW-level input voltage Ci input capacitance - - 0.8 V pin MDC [1] - - 8 pF pin MDIO [1] - - 10 pF VOH HIGH-level output voltage pin MDIO; IOH = -4 mA VDD(IO) - 0.4 - - V VOL LOW-level output voltage pin MDIO; IOL = 4 mA - - 0.4 V IIH HIGH-level input current VIH = VDD(IO) - - 20 μA IIL LOW-level input current pin MDC; VIL = 0 V -20 - - μA pin MDIO; Vi = 0 V -100 - -20 μA Rpd pull-down resistance on pin MDC 262.5 500 - kΩ Rpu pull-up resistance on pin MDIO 70 100 130 kΩ 2 - - V - - 0.8 V - - 8 pF (R)MII interface: pins TXER, TXEN, TXDx, TXC, RXDx, RXDV, RXER, RXC VIH HIGH-level input voltage VIL LOW-level input voltage [1] Ci input capacitance VOH HIGH-level output voltage IOH = -4 mA VDD(IO) - 0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IIH HIGH-level input current VIH = VDD(IO) - - 200 μA IIL LOW-level input current VIL = 0 V -20 - - μA Rpd pull-down resistance on pins TXER, TXEN, TXDx, TXDx 70 100 130 kΩ on pin TXC; Reverse MII mode 70 100 130 kΩ [1] Not measured in production; guaranteed by design. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 42 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 36. General electrical characteristics Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit pins RST_N, EN VIH HIGH-level input voltage 2 - - V VIL LOW-level input voltage - - 0.8 V Vhys(i) input hysteresis voltage 0.36 0.5 - V - - 8 pF [1] Ci input capacitance IIH HIGH-level input current at pin RST_N; VIH = VDD(IO) - - 20 μA IIL LOW-level input current at pin EN; VIL = 0 V -20 - - μA Rpd pull-down resistance on pin EN 70 100 130 kΩ Rpu pull-up resistance on pin RST_N 70 100 130 kΩ LOW-level output voltage IOL = 2 mA - - 0.4 V V pin INT_N VOL pin SEL_1V8 VIH HIGH-level input voltage 0.7 × VDD(IO) - - VIL LOW-level input voltage - - 0.3 × V VDD(IO) Vhys(i) input hysteresis voltage 0.1 × VDD(IO) - - V IIL LOW-level input current VIL = 0 V -5 - +5 μA Rpd pull-down resistance on pin SEL_1V8 70 100 130 kΩ V pin CLK_IN_OUT VIH HIGH-level input voltage 0.7 × VDD(IO) - - VIL LOW-level input voltage - - 0.3 × V VDD(IO) Vhys(i) input hysteresis voltage 0.1 × VDD(IO) - - V VOH HIGH-level output voltage CLK_MODE = 01; IOH = -4 mA VDD(IO) - 0.4 - - V VOL LOW-level output voltage CLK_MODE = 01; IOL = 4 mA - - 0.4 V IIL LOW-level input current CLK_MODE = 00 or 11; VIL = 0 V -5 - +5 μA Rpd pull-down resistance CLK_MODE = 00 or 11 70 100 130 kΩ pins RXD[3:0], RXER, RXDV, during pin strapping VIH HIGH-level input voltage 2 - - V VIL LOW-level input voltage - - 0.8 V TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 43 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 36. General electrical characteristics...continued Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit CONFIG_WAKE = 0 (see Table 30) 2.8 - 4.1 V CONFIG_WAKE = 1 0.44 × VDD(IO) - 0.64 × V VDD(IO) CONFIG_WAKE = 0 2.4 - 3.75 CONFIG_WAKE = 1 0.38 × VDD(IO) - 0.55 × V VDD(IO) CONFIG_WAKE = 0 0.25 - 0.8 CONFIG_WAKE = 1 0.025 × VDD(IO) 0.2 × V VDD(IO) -5 - +5 μA pin WAKE_IN_OUT VIH VIL Vhys(i) HIGH-level input voltage LOW-level input voltage input hysteresis voltage V V Ii input current VOH HIGH-level output voltage all modes except Sleep and Power-off; IWAKE_IN_OUT = 0 mA VBAT 0.8 - VBAT V IOL LOW-level output current all modes except Sleep, Poweroff; VWAKE_IN_OUT = 0 V -30 - - mA VOH HIGH-level output voltage all modes except Sleep, Poweroff; IINH = -1 mA VBAT - 1 - VBAT V IOL LOW-level output current all modes except Sleep, Poweroff; VINH = 0 V -15 -7 -2 mA IL leakage current Sleep, Power-off modes -5 - +5 μA input capacitance pin XI - 3.5 - pF - 2 - pF 13.3 25 47 mA/V pin INH pins XI, XO Ci pin XO gm(DC) DC transconductance [1] Normal, Sleep Request modes; MII_MODE = 00, 01 or 11 Transmitter test results: pins TRX_M, TRX_P [2] Vdroop/VM droop voltage to peak voltage ratio 100BASE-T1 test mode 1; with respect to initial peak value [1] -45 - +45 % Vdist(M) peak distortion voltage 100BASE-T1 test mode 4 [1] - - 15 mV 100BASE-T1 test mode 5 [1] f = 1 MHz -70.9 - -63.3 dBm/ Hz f = 20 MHz -75.8 - -64.8 dBm/ Hz f = 40 MHz -89.2 - -68.5 dBm/ Hz PSDM power spectral density mask TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 44 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 36. General electrical characteristics...continued Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions f = 57 MHz to 200 MHz Transmitter output amplitude: pins TRX_M, RX_P VoM(TX) Rterm Typ Max Unit - - -76.5 dBm/ Hz - 1 - V 47.5 50 52.5 Ω [2] transmitter peak output voltage termination resistance Min [3] on each pin; Normal, Sleep Request modes; LINK_ CONTROL = 1 Temperature protection Tj(sd) shutdown junction temperature 180 - 200 °C Tj(sd)rel release shutdown junction temperature 147 - 167 °C Tj(warn) warning junction temperature 155 - 175 °C Tj(warn)rel release warning junction temperature 147 - 167 °C Tj(warn)hys warning junction temperature hysteresis 2 8 - °C [1] [2] [3] Not measured in production; guaranteed by design. Test carried out with external common mode choke and coupling capacitors connected. Including the resistance of an external common mode choke (average 3.5 Ω) with a 1 kΩ parallel resistor. 10 Dynamic characteristics Table 37. Dynamic characteristics Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit [1] MII transmit timing (see Figure 12); MII_DRIVER = 0 (standard output driver strength) Tclk clock period pin TXC - 40 - ns δ duty cycle pin TXC 35 - 65 % tWH pulse width HIGH pin TXC 14 20 - ns tWL pulse width LOW pin TXC 14 20 - ns tsu set-up time TXC to TXD[3:0], TXER, TXEN MII 10 - - ns Reverse MII 10 - - ns 0 - - ns 10 - - ns - 40 - ns th hold time TXC to TXD[3:0], TXEN, TXER MII Reverse MII MII receive timing (see Figure 13); MII_DRIVER = 0 (standard output driver strength) Tclk clock period TJA1101B Product data sheet pin RXC All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 [1] © NXP B.V. 2021. All rights reserved. 45 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 37. Dynamic characteristics...continued Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit δ duty cycle pin RXC 35 - 65 % tWH pulse width HIGH pin RXC 14 20 - ns tWL pulse width LOW pin RXC 14 20 - ns td delay time RXC to RXD[3:0], RXDV, RXER MII 15 - 25 ns Reverse MII 0 - 25 RMII transmit and receive timing (see Figure 14 and Figure 15); MII_DRIVER = 0 (standard output driver strength) ns [1] Tclk clock period pin REF_CLK - 20 - ns δ duty cycle pin REF_CLK 35 - 65 % tWH pulse width HIGH pin REF_CLK 7 10 - ns tWL pulse width LOW pin REF_CLK 7 10 - ns tsu set-up time REF_CLK to TXD[1:0], TXEN, TXER 4 - - ns th hold time REF_CLK to TXD[1:0], TXEN, TXER 2 - - ns td delay time REF_CLK to RXD[1:0], RXER, CRSDV 4 - 13 ns MII_DRIVER = 0; CL = 15 pF 1.3 - 5 ns MII_DRIVER = 1; CL = 7.5 pF 2 - 7.7 ns 1.3 - 5 ns MII_DRIVER = 0; CL = 15 pF 0.7 - 2.5 ns MII_DRIVER = 1; CL = 7.5 pF 0.9 - 3.4 ns 0.7 - 2.5 ns MII_DRIVER = 0; CL = 15 pF 1.3 - 5 ns MII_DRIVER = 1; CL = 7.5 pF 2 - 7.7 ns 1.3 - 5 ns MII_DRIVER = 0; CL = 15 pF 0.7 - 2.5 ns MII_DRIVER = 1; CL = 7.5 pF 0.9 - 3.4 ns 0.7 - 2.5 ns (R)MII interface timing tf fall time [1] [2] MII: RXD[3:0], RXDV, RXER MII: TXC, RXC; CL = 15 pF RMII: RXD[1:0], CRSDV, RXER RMII: REF_CLK; CL = 15 pF tr rise time [3] MII: RXD[3:0], RXDV, RXER MII: TXC, RXC; CL = 15 pF RMII: RXD[1:0], CRSDV, RXER RMII: REF_CLK; CL = 15 pF SMI timing (see Figure 16) [1] Tclk(MDC) MDC clock period 400 - - ns tWH(MDC) MDC pulse width HIGH 160 - - ns tWL(MDC) MDC pulse width LOW 160 - - ns TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 46 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 37. Dynamic characteristics...continued Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit tsu(MDIO) MDIO set-up time to rising edge on MDC 10 - - ns th(MDIO) MDIO hold time from rising edge on MDC 10 - - ns td(MDC-MDIO) delay time from MDC to MDIO from rising edge on MDC; read from PHY 0 - 300 ns LOC_WU_TIM = 00 10 - 20 ms LOC_WU_TIM = 01 250 - 500 μs LOC_WU_TIM = 10 100 - 200 μs LOC_WU_TIM = 11 20 - 40 μs LOC_WU_TIM = 00 20 - 40 ms LOC_WU_TIM = 01 500 - 1000 μs LOC_WU_TIM = 10 200 - 400 μs LOC_WU_TIM = 11 40 - 80 μs [1] WAKE timing; pin WAKE_IN_OUT tdet(wake) wake-up detection time tp pulse duration ton turn-on time RL = 100 kΩ; CL = 50 pF; VWAKE_IN_OUT = 2 V 0 2 50 μs toff turn-off time RL = 100 kΩ; CL = 50 pF; VWAKE_IN_OUT = 2 V 5 50 65 μs RL = 100 kΩ; CL = 50 pF; Vth(INH) = 2 V 0 2 50 μs RL = 100 kΩ; CL = 50 pF; Vth(INH) = 2 V 5 50 65 μs [1] INH timing; pin INH ton turn-on time toff turn-off time [1] interrupt timing; pin INT_N ton turn-on time Rpu = 10 kΩ; CL = 15 pF 8 - 20 μs toff turn-off time Rpu = 10 kΩ; CL = 15 pF 8 - 20 μs JUMBO_ENABLE = 0 - 1.1 - ms JUMBO_ENABLE = 1 - 2.2 - ms Normal mode; CABLE_TEST = 1 - 100 - μs PCS-RX timeout timing [4] tto(PCS-RX) PCS-RX time-out time Normal and Sleep Request modes Cable test timing tto(cbl_tst) cable test time-out time [1] pins RST_N, EN tdet(rst) reset detection time on pin RSTN; Vuvd(VDDIO) < VDD(IO) ≤ 3.5 V 5 - 20 μs tdet(EN) detection time on pin EN Vuvd(VDDIO) < VDD(IO) ≤ 3.5 V 5 - 20 μs Master mode - - 50 ps Transmitter test results tjit(RMS) RMS jitter time TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 47 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Table 37. Dynamic characteristics...continued Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit - - 150 ps on pin VBAT; VBAT = 2.7 V 0 - 30 μs on pin VDDA(3V3); VDDA(3V3) = 2.8 V 2 - 30 μs on pin VDDD(3V3); VDDD(3V3) = 2.8 V 2 - 30 μs on pin VDDD(1V8) 2 - 30 μs VDD(IO) = 2.8 V 2 - 30 μs on pin VDDA(3V3); VDDA(3V3) = 3.2 V 2 - 30 μs on pin VDDD(3V3); VDDD(3V3) = 3.2 V 2 - 30 μs on pin VDDD(1V8) 2 - 30 μs on pin VDD(IO); VDD(IO) = 3.2 V 2 - 30 μs for transition from Standby to Sleep mode (see Section 6.9.1) 300 - 670 ms Slave mode (with link); SLAVE_ JITTER_TEST = 1 Undervoltage detection tdet(uv) trec(uv) tto(uvd) [1] [5] [1] undervoltage detection time undervoltage recovery time undervoltage detection time-out time [1] General timing parameters ts(pon) power-on settling time from power-on to Standby mode - - 2 ms tinit(PHY) PHY initialization time from Standby mode to Normal mode - - 2 ms tto(req)sleep sleep request time-out time SLEEP_REQUEST_TO = 00 360 - 500 μs SLEEP_REQUEST_TO = 01 900 - 1150 μs SLEEP_REQUEST_TO = 10 3.6 - 4.4 ms SLEEP_REQUEST_TO = 11 14.4 - 17.6 ms SLEEP_REQUEST_TO = 00 180 - 250 μs SLEEP_REQUEST_TO = 01 450 - 575 μs SLEEP_REQUEST_TO = 10 1.8 - 2.2 ms SLEEP_REQUEST_TO = 11 7.2 - 8.8 ms tto(ack)sleep sleep acknowledge time-out time tdet(PHY) PHY detection time on bus pins TRX_P, TRX_M - - 0.7 ms tto(pd)autn autonomous power-down time-out time Normal mode; AUTO_PWD = 1 1 - 2 s tPD propagation delay from MII to MDI; Normal mode 140 - 300 ns from MDI to MII; Normal mode 760 - 920 ns from RMII to MDI; Normal mode 190 - 540 ns from MDI to RMII; Normal mode 700 - 1070 ns Normal mode; no active link; wake-up forwarding 0.7 1.0 1.3 ms tw(wake) [1] [2] [3] wake-up pulse width Not measured in production; guaranteed by design. From 2 V to 0.8 V. From 0.8 V to 2 V. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 48 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet [4] [5] rcv_max_timer in the IEEE specification [1]. Measured at the RXER pin, representing the transmit clock (TX_CLK). Tclk(TXC) tWH(TXC) tWL(TXC) TXC tsu(MII) tsu(MII) th(MII) th(MII) TXEN TXD[3:0] TXER aaa-038936 Figure 12. MII transmit timing diagram Tclk(RXC) tWH(RXC) tWL(RXC) RXC td(MIIrx) td(MIIrx) RXDV td(MIIrx) td(MIIrx) RXD[3:0] RXER aaa-038937 Figure 13. MII receive timing diagram TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 49 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet tWH(REF_CLK) tWL(REF_CLK) Tclk(REF_CLK) REF_CLK tsu(RMII) th(RMII) tsu(RMII) th(RMII) TXEN TXD[1:0] aaa-038938 Figure 14. RMII transmit timing diagram Tclk(REF_CLK) REF_CLK td(RMIIrx) td(RMIIrx) CRSDV RXER RXD[1:0] aaa-038939 Figure 15. RMII receive timing diagram TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 50 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet tWH(MDC) Tclk(MDC) tWL(MDC) MDC td(MDC-MDIO) td(MDC-MDIO) MDIO (Data-out) tsu(MDIO) th(MDIO) MDIO (Data-in) aaa-038940 Figure 16. SMI timing diagram 11 Application information The MDI circuit for the TJA1101B is shown in Figure 17. The common mode termination depends on OEM requirements and might vary, depending on the application. The common mode choke is expected to be compliant with the OPEN Alliance CMC specification. The 100 nF coupling capacitors should have a voltage range ≥ 50 V with 10 % (max) tolerance. The TJA1101B provides an ESD robustness of ±6 kV according to IEC 61000-4-2 and HBM at the IC pins. With CMC and coupling capacitors, it is able to withstand ≥ ±8 kV for IEC 61000-4-2 on the connector pins. common mode choke TRX_P PHY 100 nF BI_DA+ TRX_M BI_DA- 200 µH 100 nF according to OPEN Alliance CMC Spec 1 kΩ 100 kΩ 1 kΩ 4.7 nF optional according to OPEN Alliance System Implementation Spec aaa-022043 Figure 17. MDI circuit diagram Further information can be found in the TJA1101B application hints [2]. 12 Package information The TJA1101B comes in a 36-pin HVQFN package as shown in Figure 18. Measuring 2 just 36 mm with a pitch of 0.5 mm, the HVQFN36 package is particularly suited to PCB space-constrained applications, such as an integrated IP camera module. The package features wettable sides/flanks to allow for optical inspection of the soldering process. The exposed die pad must be connected to ground. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 51 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 13 Package outline HVQFN36: plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; body 6 x 6 x 0.85 mm D B SOT1092-2 A terminal 1 index area E A A1 c detail X e1 e v w b 10 18 C C A B C y1 C y L 19 9 e e2 Eh 1 27 terminal 1 index area 36 28 X Dh 0 2.5 Dimensions Unit mm 5 mm scale A(1) A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 e2 L v 0.2 6.1 6.0 5.9 4.05 3.90 3.75 6.1 6.0 5.9 4.05 3.90 3.75 0.5 4 4 0.65 0.55 0.45 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT1092-2 References IEC JEDEC JEITA --- --- sot1092-2_po European projection Issue date 09-02-23 09-02-24 Figure 18. Package outline SOT1092-2 (HVQFN36) TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 52 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 14 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 53 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 38 and Table 39 Table 38. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 39. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 54 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15 References [1] IEEE 802.3bw-2015 — IEEE Standard for Ethernet Amendment 1: Physical Layer Specifications and Management Parameters for 100 Mb/s Operation over a Single Balanced Twisted Pair Cable (100BASET1) [2] AN13147 — Application note for TJA1101B 100BASE-T1 PHY for automotive Ethernet, NXP Semiconductors 16 Revision history Table 40. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1101B v.1 20210301 Product data sheet - - TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 55 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet 17 Legal information 17.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 17.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without TJA1101B Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 56 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL-classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. TJA1101B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 March 2021 © NXP B.V. 2021. All rights reserved. 57 / 58 TJA1101B NXP Semiconductors 100BASE-T1 PHY for automotive Ethernet Contents 1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 5.1 6 6.1 6.2 6.2.1 6.2.2 6.2.2.1 6.2.3 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.1.3 6.3.1.4 6.3.1.5 6.3.1.6 6.3.1.7 6.3.1.8 6.3.2 General description ............................................ 1 Features and benefits .........................................1 General .............................................................. 1 Optimized for automotive use cases ..................1 Low-power mode ............................................... 2 Diagnosis ........................................................... 2 Miscellaneous .................................................... 2 Ordering information .......................................... 2 Block diagram ..................................................... 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Functional description ........................................7 System configuration ......................................... 7 MII and RMII ......................................................8 MII ...................................................................... 8 RMII ................................................................... 9 Signaling and encoding ..................................... 9 Reverse MII ..................................................... 10 System controller ............................................. 11 Operating modes ............................................. 11 Power-off mode ............................................... 11 Standby mode ................................................. 11 Normal mode ................................................... 11 Disable mode ...................................................12 Sleep mode ..................................................... 12 Sleep Request mode ....................................... 12 Silent mode ......................................................13 Reset mode ..................................................... 13 Status of functional blocks in TJA1101B operating modes .............................................. 13 6.4 Mode transitions .............................................. 15 6.5 Sleep and wake-up forwarding concept ...........17 6.6 Autonomous operation .....................................18 6.7 Autonomous power-down ................................ 18 6.8 Test modes ...................................................... 18 6.8.1 Test mode 1 .....................................................18 6.8.2 Test mode 2 .....................................................18 6.8.3 Test mode 3 .....................................................18 6.8.4 Test mode 4 .....................................................18 6.8.5 Test mode 5 .....................................................19 6.8.6 Slave jitter test .................................................19 6.9 Error diagnosis ................................................ 19 6.9.1 Undervoltage detection ....................................19 6.9.2 Cabling errors .................................................. 19 6.9.3 Link stability ..................................................... 20 6.9.4 Link-fail counter ............................................... 20 6.9.5 Jabber detection .............................................. 20 6.9.6 Polarity detection ............................................. 21 6.9.7 Interleave detection ......................................... 21 6.9.8 Loopback modes ............................................. 21 6.9.8.1 Internal loopback ............................................. 21 6.9.8.2 External loopback ............................................ 21 6.9.8.3 Remote loopback .............................................22 6.10 6.11 6.11.1 6.11.2 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 Hardware configuration ....................................23 SMI registers ................................................... 24 Register mapping overview ............................. 24 TJA1101B registers ......................................... 25 Limiting values .................................................. 39 Thermal characteristics ....................................40 Static characteristics ........................................ 40 Dynamic characteristics ...................................45 Application information .................................... 51 Package information .........................................51 Package outline .................................................52 Soldering of SMD packages .............................53 Introduction to soldering ............................. Wave and reflow soldering ......................... Wave soldering ........................................... Reflow soldering ......................................... References ......................................................... 55 Revision history ................................................ 55 Legal information .............................................. 56 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 March 2021 Document identifier: TJA1101B