NPN − 2N6515, 2N6517;
PNP − 2N6520
High Voltage Transistors
NPN and PNP
Features
http://onsemi.com
• Voltage and Current are Negative for PNP Transistors
• These are Pb−Free Devices*
COLLECTOR
3
2
BASE
MAXIMUM RATINGS
Rating
Symbol
Collector − Emitter Voltage
Vdc
250
350
VCBO
2N6515
2N6517, 2N6520
Emitter − Base Voltage
1
EMITTER
2
BASE
Vdc
PNP
250
350
VEBO
2N6515, 2N6517
2N6520
1
EMITTER
Vdc
6.0
5.0
Base Current
IB
250
mAdc
Collector Current − Continuous
IC
500
mAdc
Total Device Dissipation @ TA = 25°C
Derate above 25°C
PD
625
5.0
mW
mW/°C
Total Device Dissipation @ TC = 25°C
Derate above 25°C
PD
1.5
12
W
mW/°C
TJ, Tstg
−55 to +150
°C
Operating and Storage Junction
Temperature Range
COLLECTOR
3
NPN
Unit
VCEO
2N6515
2N6517, 2N6520
Collector − Base Voltage
Value
TO−92
CASE 29
STYLE 1
1
12
3
STRAIGHT LEAD
BULK PACK
2
3
BENT LEAD
TAPE & REEL
AMMO PACK
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
200
°C/W
Thermal Resistance, Junction−to−Case
RqJC
83.3
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
MARKING DIAGRAM
2N
65xx
AYWW G
G
xx
= 15, 17, or 20
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 5
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
2N6515/D
NPN − 2N6515, 2N6517; PNP − 2N6520
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
250
350
−
−
250
350
−
−
6.0
5.0
−
−
−
−
50
50
−
−
50
50
2N6515
2N6517, 2N6520
35
20
−
−
(IC = 10 mAdc, VCE = 10 Vdc)
2N6515
2N6517, 2N6520
50
30
−
−
(IC = 30 mAdc, VCE = 10 Vdc)
2N6515
2N6517, 2N6520
50
30
300
200
(IC = 50 mAdc, VCE = 10 Vdc)
2N6515
2N6517, 2N6520
45
20
220
200
(IC = 100 mAdc, VCE = 10 Vdc)
2N6515
2N6517, 2N6520
25
15
−
−
−
−
−
−
0.30
0.35
0.50
1.0
−
−
−
0.75
0.85
0.90
Unit
OFF CHARACTERISTICS
Collector−Emitter Breakdown Voltage (Note 1)
(IC = 1.0 mAdc, IB = 0)
V(BR)CEO
2N6515
2N6517, 2N6520
Collector−Base Breakdown Voltage
(IC = 100 mAdc, IE = 0 )
Vdc
V(BR)CBO
2N6515
2N6517, 2N6520
Emitter−Base Breakdown Voltage
(IE = 10 mAdc, IC = 0)
Vdc
V(BR)EBO
2N6515, 2N6517
2N6520
Collector Cutoff Current
(VCB = 150 Vdc, IE = 0)
(VCB = 250 Vdc, IE = 0)
2N6515
2N6517, 2N6520
Emitter Cutoff Current
(VEB = 5.0 Vdc, IC = 0)
(VEB = 4.0 Vdc, IC = 0)
2N6515, 2N6517
2N6520
Vdc
ICBO
nAdc
IEBO
nAdc
ON CHARACTERISTICS (Note 1)
DC Current Gain
(IC = 1.0 mAdc, VCE = 10 Vdc)
hFE
−
Collector−Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
(IC = 20 mAdc, IB = 2.0 mAdc)
(IC = 30 mAdc, IB = 3.0 mAdc)
(IC = 50 mAdc, IB = 5.0 mAdc)
VCE(sat)
Vdc
Base−Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
(IC = 20 mAdc, IB = 2.0 mAdc)
(IC = 30 mAdc, IB = 3.0 mAdc)
VBE(sat)
Base−Emitter On Voltage
(IC = 100 mAdc, VCE = 10 Vdc)
VBE(on)
−
2.0
Vdc
fT
40
200
MHz
Ccb
−
6.0
pF
−
−
80
100
Vdc
SMALL−SIGNAL CHARACTERISTICS
Current−Gain − Bandwidth Product (Note 1)
(IC = 10 mAdc, VCE = 20 Vdc, f = 20 MHz)
Collector−Base Capacitance
(VCB = 20 Vdc, IE = 0, f = 1.0 MHz)
Emitter−Base Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz)
Ceb
2N6515, 2N6517
2N6520
pF
SWITCHING CHARACTERISTICS
Turn−On Time
(VCC = 100 Vdc, VBE(off) = 2.0 Vdc, IC = 50 mAdc, IB1 = 10 mAdc)
ton
−
200
ms
Turn−Off Time
(VCC = 100 Vdc, IC = 50 mAdc, IB1 = IB2 = 10 mAdc)
toff
−
3.5
ms
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%.
http://onsemi.com
2
NPN − 2N6515, 2N6517; PNP − 2N6520
hFE , DC CURRENT GAIN
200
VCE = 10 V
TJ = 125°C
100
25°C
70
−55°C
50
30
20
1.0
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50
70 100
Figure 1. DC Current Gain
NPN 2N6515
200
200
TJ = 125°C
VCE = −10 V
100
hFE , DC CURRENT GAIN
hFE , DC CURRENT GAIN
VCE = 10 V
25°C
70
50
−55°C
30
20
10
1.0
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
100
25°C
70
−55°C
50
30
20
10
−1.0
50 70 100
100
70
50
TJ = 25°C
VCE = 20 V
f = 20 MHz
20
10
1.0
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
−2.0 −3.0 −5.0 −7.0 −10
−20 −30
IC, COLLECTOR CURRENT (mA)
−50 −70 −100
Figure 3. DC Current Gain
PNP 2N6520
f,
T CURRENT−GAIN BANDWIDTH PRODUCT (MHz)
f,
T CURRENT−GAIN BANDWIDTH PRODUCT (MHz)
Figure 2. DC Current Gain
NPN 2N6517
30
TJ = 125°C
50 70
100
Figure 4. Current−Gain − Bandwidth Product
NPN 2N6515, 2N6517
100
70
50
TJ = 25°C
VCE = −20 V
f = 20 MHz
30
20
10
−1.0
−2.0 −3.0 −5.0 −7.0 −10
−20 −30
IC, COLLECTOR CURRENT (mA)
−50 −70 −100
Figure 5. Current−Gain − Bandwidth Product
PNP 2N6520
http://onsemi.com
3
NPN − 2N6515, 2N6517; PNP − 2N6520
−1.4
1.4
TJ = 25°C
1.2
−1.2
0.8
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
1.0
VBE(sat) @ IC/IB = 10
0.6
VBE(on) @ VCE = 10 V
0.4
0.2
0
1.0
VCE(sat) @ IC/IB = 5.0
2.0
3.0
−1.0
−0.8
VBE(sat) @ IC/IB = 10
−0.6
VBE(on) @ VCE = −10 V
−0.4
−0.2
VCE(sat) @ IC/IB = 10
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50
0
−1.0
70 100
1.5
1.0
0.5
0
RθV, TEMPERATURE COEFFICIENTS (mV/°C)
RθV, TEMPERATURE COEFFICIENTS (mV/°C)
IC
+ 10
IB
2.0
25°C to 125°C
RqVC for VCE(sat)
−55°C to
25°C
−0.5
−1.0
−1.5
−2.0
−2.5
1.0
−55°C to 125°C
RqVB for VBE
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50
70
100
2.0
1.5
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
20
0.5
Ccb
−55°C to
25°C
−1.0
−1.5
RqVC for VCE(sat)
−55°C to 125°C
−2.0
−2.5
−1.0
−2.0 −3.0 −5.0 −7.0 −10
−20 −30
IC, COLLECTOR CURRENT (mA)
−50 −70 −100
TJ = 25°C
20
10
7.0
5.0
2.0
1.0
−0.2
50 100 200
Ceb
30
3.0
1.0 2.0
5.0
10
20
VR, REVERSE VOLTAGE (VOLTS)
RqVB for VBE
−0.5
2.0
0.5
25°C to 125°C
0
3.0
1.0
0.2
IC
+ 10
IB
1.0
100
70
50
Ceb
10
7.0
5.0
−50 −70 −100
Figure 9. Temperature Coefficients
PNP 2N6520
TJ = 25°C
30
VCE(sat) @ IC/IB = 5.0
−2.0 −3.0 −5.0 −7.0 −10
−20 −30
IC, COLLECTOR CURRENT (mA)
2.5
Figure 8. Temperature Coefficients
NPN 2N6515, 2N6517
100
70
50
VCE(sat) @ IC/IB = 10
Figure 7. “On” Voltages
PNP 2N6520
Figure 6. “On” Voltages
NPN 2N6515, 2N6517
2.5
TJ = 25°C
Figure 10. Capacitance
NPN 2N6515, 2N6517
Ccb
−0.5 −1.0 −2.0
−5.0 −10 −20
−50
VR, REVERSE VOLTAGE (VOLTS)
Figure 11. Capacitance
PNP 2N6520
http://onsemi.com
4
−10
0
−20
0
NPN − 2N6515, 2N6517; PNP − 2N6520
1.0k
700
500
td @ VBE(off) = 2.0 V
VCE(off) = 100 V
IC/IB = 5.0
TJ = 25°C
tr
100
70
50
100
70
50
30
30
20
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50
tr
200
20
10
1.0
10
−1.0
70 100
−2.0 −3.0 −5.0 −7.0 −10
−20 −30
IC, COLLECTOR CURRENT (mA)
Figure 12. Turn−On Time
NPN 2N6515, 2N6517
10k
7.0k
5.0k
t, TIME (ns)
−50 −70 −100
Figure 13. Turn−On Time
PNP 2N6520
2.0k
ts
ts
1.0k
700
3.0k
500
2.0k
1.0k
700
500
VCE(off) = −100 V
IC/IB = 5.0
TJ = 25°C
td @ VBE(off) = 2.0 V
300
200
t, TIME (ns)
t, TIME (ns)
300
1.0k
700
500
tf
tf
300
VCE(off) = 100 V
IC/IB = 5.0
IB1 = IB2
TJ = 25°C
VCE(off) = −100 V
IC/IB = 5.0
IB1 = IB2
TJ = 25°C
200
100
70
50
300
200
30
100
1.0
2.0 3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50
20
−1.0
70 100
−2.0 −3.0 −5.0 −7.0 −10
−20 −30
IC, COLLECTOR CURRENT (mA)
Figure 14. Turn−Off Time
NPN 2N6515, 2N6517
−50 −70 −100
Figure 15. Turn−Off Time
PNP 2N6520
+VCC
VCC ADJUSTED
FOR VCE(off) = 100 V
+10.8 V
2.2 k
20 k
50 W SAMPLING SCOPE
1.0 k
50
1/2MSD7000
−9.2 V
PULSE WIDTH ≈ 100 ms
tr, tf ≤ 5.0 ns
DUTY CYCLE ≤ 1.0%
FOR PNP TEST CIRCUIT,
REVERSE ALL VOLTAGE POLARITIES
APPROXIMATELY
−1.35 V
(ADJUST FOR V(BE)off = 2.0 V)
Figure 16. Switching Time Test Circuit
http://onsemi.com
5
RESISTANCE (NORMALIZED)
NPN − 2N6515, 2N6517; PNP − 2N6520
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
0.1
SINGLE PULSE
0.05
0.1
0.07
0.05
SINGLE PULSE
ZqJC(t) = r(t) • RqJC TJ(pk) − TC = P(pk) ZqJC(t)
ZqJA(t) = r(t) • RqJA TJ(pk) − TA = P(pk) ZqJA(t)
0.03
0.02
0.01
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
t, TIME (ms)
100
200
500
1.0k
2.0k
5.0k
10k
Figure 17. Thermal Response
IC, COLLECTOR CURRENT (mA)
500
TA = 25°C
200
100
tP
1.0 ms
TC = 25°C
50
FIGURE A
10 ms
100 ms
PP
100 ms
PP
20
CURRENT LIMIT
THERMAL LIMIT
(PULSE CURVES @ TC = 25°C)
SECOND BREAKDOWN LIMIT
10
5.0
2.0
CURVES APPLY
BELOW RATED VCEO
1.0
0.5
0.5
1.0
t1
2N6515
1/f
t
DUTYCYCLE + t1f + 1
tP
PEAK PULSE POWER = PP
2N6517, 2N6520
2.0
5.0
10
20
50 100 200
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
500
Figure 18. Active Region Safe Operating Area
Design Note: Use of Transient Thermal
Resistance Data
ORDERING INFORMATION
Package
Shipping†
2N6515RLRMG
TO−92
(Pb−Free)
2000 Ammo Pack
2N6517G
TO−92
(Pb−Free)
5000 Unit / Bulk
2N6517RLRPG
TO−92
(Pb−Free)
2000 Ammo Pack
2N6520RLRAG
TO−92
(Pb−Free)
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226)
CASE 29−11
ISSUE AM
SCALE 1:1
1
12
3
STRAIGHT LEAD
BULK PACK
DATE 09 MAR 2007
2
3
BENT LEAD
TAPE & REEL
AMMO PACK
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
STRAIGHT LEAD
BULK PACK
R
P
L
SEATING
PLANE
K
DIM
A
B
C
D
G
H
J
K
L
N
P
R
V
D
X X
G
J
H
V
C
SECTION X−X
N
1
INCHES
MIN
MAX
0.175
0.205
0.170
0.210
0.125
0.165
0.016
0.021
0.045
0.055
0.095
0.105
0.015
0.020
0.500
--0.250
--0.080
0.105
--0.100
0.115
--0.135
---
MILLIMETERS
MIN
MAX
4.45
5.20
4.32
5.33
3.18
4.19
0.407
0.533
1.15
1.39
2.42
2.66
0.39
0.50
12.70
--6.35
--2.04
2.66
--2.54
2.93
--3.43
---
N
A
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. CONTOUR OF PACKAGE BEYOND
DIMENSION R IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P
AND BEYOND DIMENSION K MINIMUM.
BENT LEAD
TAPE & REEL
AMMO PACK
B
P
T
SEATING
PLANE
G
K
DIM
A
B
C
D
G
J
K
N
P
R
V
D
X X
J
V
1
C
N
SECTION X−X
MILLIMETERS
MIN
MAX
4.45
5.20
4.32
5.33
3.18
4.19
0.40
0.54
2.40
2.80
0.39
0.50
12.70
--2.04
2.66
1.50
4.00
2.93
--3.43
---
STYLES ON PAGE 2
DOCUMENT NUMBER:
STATUS:
98ASB42022B
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
TO−92 (TO−226)
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
3
TO−92 (TO−226)
CASE 29−11
ISSUE AM
DATE 09 MAR 2007
STYLE 1:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 6:
PIN 1. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
STYLE 7:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 8:
PIN 1. DRAIN
2. GATE
3. SOURCE & SUBSTRATE
STYLE 9:
PIN 1. BASE 1
2. EMITTER
3. BASE 2
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 11:
PIN 1. ANODE
2. CATHODE & ANODE
3. CATHODE
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
STYLE 13:
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
STYLE 14:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
STYLE 15:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
STYLE 16:
PIN 1. ANODE
2. GATE
3. CATHODE
STYLE 17:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
STYLE 18:
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
STYLE 19:
PIN 1. GATE
2. ANODE
3. CATHODE
STYLE 20:
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
STYLE 21:
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 24:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 26:
PIN 1. VCC
2. GROUND 2
3. OUTPUT
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 28:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 29:
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
STYLE 31:
PIN 1. GATE
2. DRAIN
3. SOURCE
STYLE 32:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
STYLE 33:
PIN 1. RETURN
2. INPUT
3. OUTPUT
STYLE 34:
PIN 1. INPUT
2. GROUND
3. LOGIC
STYLE 35:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
DOCUMENT NUMBER:
STATUS:
98ASB42022B
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
TO−92 (TO−226)
http://onsemi.com
2
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 2 OFXXX
3
DOCUMENT NUMBER:
98ASB42022B
PAGE 3 OF 3
ISSUE
AM
REVISION
ADDED BENT−LEAD TAPE & REEL VERSION. REQ. BY J. SUPINA.
DATE
09 MAR 2007
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 11AM
Case Outline Number:
29
onsemi,
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