74ABT16501CMTD

Revised January 1999 74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs General Description The ABT16501 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are com- plementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OE inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Features ■ Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode ■ Flow-through architecture optimizes PCB layout ■ Guaranteed latch-up protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability Ordering Code: Order Number Package Number 74ABT16501CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ABT16501CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape or Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table (Note 1) Inputs Pin Assignment for SSOP Output OEAB LEAB CLKAB A B L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X B0 (Note 2) H L L X B0 (Note 3) Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. © 1999 Fairchild Semiconductor Corporation DS011690.prf www.fairchildsemi.com 74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs January 1995 74ABT16501 Logic Diagram www.fairchildsemi.com 2 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C Over Voltage Latchup (I/O) −0.5V to +7.0V Free Air Ambient Temperature Input Voltage (Note 5) −0.5V to +7.0V Supply Voltage Input Current (Note 5) −30 mA to +5.0 mA in the Disabled or −0.5V to 5.5V in the HIGH State −0.5V to VCC −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Voltage Applied to Any Output Power-off State 10V Recommended Operating Conditions VCC Pin Potential to Ground Pin −500 mA DC Latchup Source Current Data Input 50 mV/ns Enable Input 20 mV/ns Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current Min Typ VCC Max Units V Recognized HIGH Signal 0.8 V Recognized LOW Signal 2.0 −1.2 2.5 V Min IIN = −18 mA V Min IOH = −3 mA V Min IOH = −32 mA 0.55 V Min IOL = 64 mA 1 µA Max 2.0 IBVI Input HIGH Current Breakdown Test 7 µA Max IIL Input LOW Current −1 µA Max −1 Input Leakage Test 4.75 VIN = 2.7V (Note 6) VIN = VCC 1 VID Conditions VIN = 7.0V VIN = 0.5V (Note 6) VIN = 0.0V V 0.0 IID = 1.9 µA All Other Pins Grounded IIH + Output Leakage Current 10 µA 0 − 5.5V VOUT = 2.7V; OE, OE = 2.0V Output Leakage Current −10 µA 0 − 5.5V VOUT = 0.5V; OE, OE = 2.0V IOZH IIL + IOZL IOS Output Short-Circuit Current −275 mA Max VOUT = 0V ICEX Output HIGH Leakage Current −100 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 1.0 mA Max All Outputs HIGH ICCL Power Supply Current 68 mA Max An or Bn Outputs LOW ICCZ Power Supply Current 1.0 mA Max OEn = VCC, ICCT Additional ICC/Input 2.5 mA Max All Others at VCC or GND VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 6) 0.23 MHz Max Outputs Open Transparent Mode One Bit Toggling, 50% Duty Cycle Note 6: Guaranteed, but not tested. 3 www.fairchildsemi.com 74ABT16501 Absolute Maximum Ratings(Note 4) 74ABT16501 DC Electrical Characteristics Symbol Parameter Min Typ Max Units VCC 0.7 1.2 Conditions CL = 50 pF; RL = 500Ω TA = 25°C (Note 7) VOLP Quiet Output Maximum Dynamic VOL V 5.0 VOLV Quiet Output Minimum Dynamic VOL −1.5 −1.0 V 5.0 TA = 25°C (Note 7) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 8) VIHD Minimum HIGH Level Dynamic Input Voltage 2.2 VILD Maximum LOW Level Dynamic Input Voltage 1.8 1.2 0.8 V 5.0 TA = 25°C (Note 9) V 5.0 TA = 25°C (Note 9) Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 9: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ fmax Maximum Clock Frequency 150 200 Max Min tPLH Propagation Delay 1.0 2.7 4.6 1.0 4.6 tPHL A or B to B or A 1.0 3.2 4.6 1.0 4.6 tPLH Propagation Delay 1.0 3.1 5.0 1.0 5.0 tPHL LEAB or LEBA to B or A 1.0 3.6 5.5 1.0 5.5 tPLH Propagation Delay 1.0 3.4 5.3 1.0 5.3 tPHL CLKAB or CLKBA to B or A 1.0 3.7 5.3 1.0 5.3 tPZH Propagation Delay 1.5 2.7 5.6 1.5 5.6 tPZL OEAB or OEBA to B or A 1.5 3.0 5.6 1.5 5.6 tPHZ Propagation Delay 1.5 3.7 6.0 1.5 6.0 tPLZ OEAB or OEBA to B or A 1.5 3.2 6.0 1.5 6.0 Units Max 150 MHz ns ns ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Max Min tS(H) Setup Time, 4.0 4.0 tS(L) A to CLKAB, B to CLKBA 4.0 4.0 tH(H) Hold Time, 0 0 tH(L) A to CLKAB, B to CLKBA 0 0 tS(H) Setup Time, A to LEAB 4.0 4.0 tS(L) or B to LEBA, CLK HIGH 4.0 4.0 tH(H) Hold Time, A to LEAB 1.5 1.5 tH(L) or B to LEBA, CLK HIGH 1.5 1.5 tS(H) Setup Time, A to LEAB 1.5 1.5 ts(L) or B to LEBA, CLK LOW 1.5 1.5 tH(H) Hold Time, A to LEAB 1.5 1.5 tH(L) or B to LEBA, CLK LOW 1.5 1.5 tW(H) Pulse Width, 3.3 3.3 tW(L) LEAB or LEBA, HIGH 3.3 3.3 tW(H) Pulse Width, CLKAB 3.3 3.3 tW(L) or CLKBA, HIGH or LOW 3.3 3.3 www.fairchildsemi.com 4 Units Max ns ns ns ns ns ns ns ns Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 0.0V CI/O (Note 10) Output Capacitance 11.0 pF VCC = 5.0V Note 10: CI/O is measured at frequency f = 1 MHz per MIL-STD-883, Method 3012. AC Loading *Includes jig and probe capacitance. FIGURE 2. VM = 1.5V FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V Rep. Rate tW tr tf 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT16501 Capacitance 74ABT16501 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A www.fairchildsemi.com 6 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)