74ABT646CMSA

Revised November 1999 74ABT646 Octal Transceivers and Registers with 3-STATE Outputs General Description Features The ABT646 consists of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ A and B output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability Ordering Code: Order Number 74ABT646CSC Package Number M24B Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 4.4mm Wide 74ABT646CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT646CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names A0–A7 © 1999 Fairchild Semiconductor Corporation DS010978 Description Data Register A Inputs/3-STATE Outputs B0–B7 Data Register B Inputs/3-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OE Output Enable Input DIR Direction Control Input www.fairchildsemi.com 74ABT646 Octal Transceivers and Registers with 3-STATE Outputs April 1992 74ABT646 Truth Table Inputs Data I/O (Note 1) OE DIR CPAB CPBA SAB SBA H X H or L X X X  H or L H X X H X X  X X X L H X L X H X L X L H L H   X L L L X L L X L L X L L X   H or L Function A0–A7 B0–B7 Isolation Input Input Clock An Data into A Register Clock Bn Data into B Register An to Bn—Real Time (Transparent Mode) Input Output Clock An Data into A Register X H X A Register to Bn (Stored Mode) X H X Clock An Data into A Register and Output to Bn X X L X L X H B Register to An (Stored Mode) X H Clock Bn Data into B Register and Output to An H or L Bn to An—Real Time (Transparent Mode) Output Input Clock Bn Data into B Register H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition  Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Real Time Transfer A-Bus to B-Bus Storage from Bus to Register FIGURE 1. FIGURE 3. Real Time Transfer B-Bus to A-Bus Transfer from Register to Bus FIGURE 2. www.fairchildsemi.com FIGURE 4. 2 74ABT646 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ABT646 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Voltage Applied to Any Output Data Input 50 mV/ns Enable Input 20 mV/ns Clock Input 100 mV/ns in the Disable or −0.5V to +5.5V Power-Off State −0.5V to VCC in the HIGH State Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 3: Either voltage limit or current limit is sufficient to protect inputs. −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) 10V DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VOL Output LOW Voltage VID Input Leakage Test IIH Input HIGH Current 2.0 Units VIH VCC V Conditions Recognized HIGH Signal Recognized LOW Signal Min IIN = −18 mA (Non I/O Pins) 2.5 IOH = −3 mA, (An, Bn) 2.0 IOH = −32 mA, (An, Bn) IOL = 64 mA, (An, Bn) 0.55 4.75 V 0.0 IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded 1 IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Max 7 µA Max V IN = 7.0V (Non-I/O Pins) 100 µA Max V IN = 5.5V (An, Bn) µA Max −1 Input LOW Current −1 IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX IZZ V IN = 2.7V (Non-I/O Pins) (Note 4) µA 1 10 V IN = VCC (Non-I/O Pins) V IN = 0.5V (Non-I/O Pins) (Note 4) V IN = 0.0V (Non-I/O Pins) µA 0V–5.5V V OUT = 2.7V (An, Bn); OE = 2.0V 0V–5.5V V OUT = 0.5V (An, Bn); OE = 2.0V −10 µA −275 mA Max V OUT = 0V (An, Bn) Output HIGH Leakage Current 50 µA Max V OUT = VCC (An, Bn) Bus Drainage Test 100 µA 0.0V −100 V OUT = 5.5V (An, Bn); All Others GND ICCH Power Supply Current 250 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max Outputs 3-STATE; All Others GND ICCT Additional ICC/Input 2.5 mA Max V I = VCC − 2.1V ICCD Dynamic ICC All Other Outputs at VCC or GND No Load Outputs OPEN (Note 4) 0.18 mA/MHz Max OE and DIR = GND, Non-I/O = GND or VCC (Note 5) One Bit toggling, 50% duty cycle Note 4: Guaranteed but not tested. Note 5: For 8-bit toggling, ICCD < 1.4 mA/MHz. www.fairchildsemi.com 4 Symbol Parameter Min Typ Max 0.6 0.8 Units Conditions VCC CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL V 5.0 TA = 25°C (Note 6) VOLV Quiet Output Minimum Dynamic VOL −1.2 −0.9 V 5.0 TA = 25°C (Note 6) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25° (Note 7) VIHD Minimum HIGH Level Dynamic Input Voltage 2.2 1.8 V 5.0 TA = 25°C (Note 8) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 8) 0.8 0.5 Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 8: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP package) Symbol Parameter Min TA = +25°C TA = −55°C to +125°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF CL = 50 pF Typ Max Min Max 200 Min Units Max fMAX Maximum Clock Frequency 200 200 tPLH Propagation Delay 1.7 3.0 5.6 2.2 8.8 1.7 5.6 MHz tPHL Clock to Bus 1.7 3.4 5.6 1.7 8.8 1.7 5.6 tPLH Propagation Delay 1.5 2.6 4.8 1.5 7.9 1.5 4.8 tPHL Bus to Bus 1.5 3.0 4.8 1.5 7.9 1.5 4.8 tPLH Propagation Delay 1.5 3.0 5.9 1.5 8.1 1.5 5.9 tPHL SBA or SAB to An to Bn 1.5 3.4 5.9 1.5 8.9 1.5 5.9 tPZH Enable Time 1.5 3.2 6.3 1.0 7.3 1.5 6.3 tPZL OE to Anor Bn 1.5 3.5 6.3 1.9 8.8 1.5 6.3 tPHZ Disable Time 1.5 3.7 6.0 1.5 9.3 1.5 6.0 tPLZ OE to Anor Bn 1.5 3.2 6.0 1.5 9.3 1.5 6.0 tPZH Enable Time 1.5 3.4 6.3 1.0 7.7 1.5 6.3 tPZL DIR to An or B n 1.5 3.7 6.3 2.2 9.5 1.5 6.3 tPHZ Disable Time 1.5 3.8 6.0 1.5 8.7 1.5 6.0 tPLZ DIR to An or B n 1.5 3.2 6.0 1.5 9.2 1.5 6.0 ns ns ns ns ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF CL = 50 pF Min tS(H) Setup Time, HIGH tS(L) or LOW Bus to Clock tH(H) Hold Time, HIGH tH(L) or LOW Bus to Clock tW(H) Pulse Width, tW(L) HIGH or LOW Max Units Min Max Min 1.5 1.5 3.0 1.5 ns 1.0 1.0 1.0 1.0 ns 3.0 3.0 4.0 3.0 ns 5 Max www.fairchildsemi.com 74ABT646 DC Electrical Characteristics 74ABT646 Extended AC Electrical Characteristics (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching 1 Output Switching 8 Outputs Switching Parameter (Note 9) (Note 10) Units (Note 11) Min Max Min Max Min Max tPLH Propagation Delay 1.5 5.5 2.0 7.5 2.5 10.0 tPHL Clock to Bus 1.5 5.5 2.0 7.5 2.5 10.0 tPLH Propagation Delay 1.5 6.0 2.0 7.0 2.5 9.5 tPHL Bus to Bus 1.5 6.0 2.0 7.0 2.5 9.5 tPLH Propagation Delay 1.5 6.0 2.0 7.5 2.5 10.0 tPHL SBA or SAB to An or Bn 1.5 6.0 2.0 7.5 2.5 10.0 tPZH Output Enable Time 1.5 6.0 2.0 8.0 2.5 10.5 tPZL OEn or DIR to An or Bn 1.5 6.0 2.0 8.0 2.5 10.5 tPHZ Output Disable Time 1.5 6.0 tPLZ OEn or DIR to An or Bn 1.5 6.0 (Note 12) ns ns ns ns (Note 12) ns Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 12: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Skew (SOIC Package) Symbol Parameter TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 13) (Note 14) Max Max Units tOSHL (Note 15) Pin to Pin Skew, HL Transitions 1.3 2.5 ns tOSLH (Note 15) Pin to Pin Skew, LH Transitions 1.0 2.0 ns tPS (Note 16) Duty Cycle, LH–HL Skew 2.0 4.0 ns tOST (Note 15) Pin to Pin Skew, LH/HL Transitions 2.0 4.0 ns tPV (Note 17) Device to Device Skew, LH/HL Transitions 2.5 4.5 ns Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5 pF VCC = 0V (non I/O pins) CI/O (Note 18) Output Capacitance 11 pF VCC = 5.0V (An, Bn) Note 18: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 6 74ABT646 AC Loading *Includes jig and probe capacitance FIGURE 6. Test Input Signal Levels Input Pulse Requirements FIGURE 5. Standard AC Test Load Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 7. Test Input Signal Requirements AC Waveforms FIGURE 8. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 10. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 9. Propagation Delay, Pulse Width Waveforms FIGURE 11. Setup Time, Hold Time and Recovery Time Waveforms 7 www.fairchildsemi.com 74ABT646 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 www.fairchildsemi.com 8 74ABT646 Octal Transceivers and Registers with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com