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74ACT16240SSCX

74ACT16240SSCX

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SSOP48_300MIL

  • 描述:

    IC BUFFER INVERT 5.5V 48SSOP

  • 数据手册
  • 价格&库存
74ACT16240SSCX 数据手册
Revised October 1999 74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs General Description Features The ACT16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. ■ Separate control logic for each byte ■ 16-bit version of the ACT240 ■ Outputs source/sink 24 mA ■ TTL-compatible inputs Ordering Code: Order Number Package Number 74ACT16240SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ACT16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Inputs (Active LOW) I0–I15 Inputs O0–O15 Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS500293 www.fairchildsemi.com 74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs August 1999 74ACT16240 Truth Tables Inputs Outputs Inputs I0–I3 O0–O3 OE2 L L H L H L H X Z OE1 Inputs Outputs I4–I7 O4–O7 L L H L H L H X Z Outputs Inputs Outputs OE3 I8–I11 O8–O11 OE4 I12–I15 O12–O15 L L H L L H L H L L H L H X Z H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Functional Description Logic Diagram The ACT16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) +140°C −65°C to +150°C 125 mV/ns VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ± 50 mA Storage Temperature −40°C to +85°C VIN from 0.8V to 2.0V DC VCC or Ground Current per Output Pin 0V to VCC Operating Temperature (TA) ± 50 mA Junction Temperature 0V to VCC Output Voltage (VO) Minimum Input Edge Rate (∆V/∆t) −0.5V to VCC + 0.5V DC Output Source/Sink Current (IO) 4.5V to 5.5V Input Voltage (VI) DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = −40°C to +85°C TA = +25°C VCC (V) Typ Units Conditions Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 2) 4.86 4.76 Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.5 ±5.0 ± 0.1 ± 1.0 µA VI = VCC, GND 1.5 mA VI = VCC − 2.1V 80.0 µA VIN = VCC or GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IOZ Maximum 3-STATE Leakage Current IIN Maximum Input Leakage Current 5.5 ICCT Maximum ICC/Input 5.5 ICC Max Quiescent Supply Current 5.5 IOLD Minimum Dynamic IOHD Output Current (Note 3) 0.6 8.0 5.5 IOL = 24 mA (Note 2) µA VI = VIL, VIH VO = VCC, GND Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. 3 www.fairchildsemi.com 74ACT16240 Absolute Maximum Ratings(Note 1) 74ACT16240 AC Electrical Characteristics Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 4) tPLH Propagation Delay tPHL Data to Output tPZH Output Enable Time 5.0 5.0 tPZL tPHZ Output Disable Time 5.0 tPLZ TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max 2.7 4.8 7.3 2.7 7.8 3.0 5.1 7.3 3.0 7.8 2.5 4.5 7.4 2.5 7.9 2.7 4.7 7.5 2.7 8.0 2.3 5.0 7.9 2.3 8.2 2.0 4.6 7.4 2.0 7.9 Note 4: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Typ Units CIN Symbol Input Pin Capacitance Parameter 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 30 pF VCC = 5.0V www.fairchildsemi.com 4 Conditions Units ns ns ns 74ACT16240 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS48A 5 www.fairchildsemi.com 74ACT16240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Think Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 www.fairchildsemi.com 6 74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com
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