74ACT843SCX

Revised September 2000 74ACT843 9-Bit Transparent Latch General Description Features The ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths. ■ TTL compatible inputs ■ 3-STATE outputs for bus interfacing Ordering Code: Order Number Package Number 74ACT843SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Description 74ACT843SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.) Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D8 Data Inputs O0–O8 Data Outputs OE Output Enable LE Latch Enable CLR Clear PRE Preset FACT is a trademark of Fairchild Semiconductor Corporation © 2000 Fairchild Semiconductor Corporation DS009800 www.fairchildsemi.com 74ACT843 9-Bit Transparent Latch July 1988 74ACT843 Functional Description The ACT843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the ACT843 has a Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR. Function Tables Inputs Internal Outputs Function CLR PRE OE LE D Q O H H H H L L Z High Z High Z H H H H H H Z H H H L X NC Z Latched H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC H L L X X H H Preset L H L X X L L Clear L L L X X H H Preset L H H L X L Z Clear/High Z H L H L X H Z Preset/High Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram www.fairchildsemi.com 2 Latched Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 0V to VCC Output Voltage (VO) −0.5V to VCC +0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC +0.5V 125 mV/ns VIN from 0.8V to 2.0V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) VCC @ 4.5V, 5.5V −0.5V to VCC +0.5V DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to +85°C Units Conditions Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 2) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.5 ±5.0 µA 1.5 mA V IOUT = 50 µA V IO = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current ICCT Maximum ICC/Input 5.5 0.6 IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 80.0 µA Supply Current 5.5 8.0 VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT843 Absolute Maximum Ratings(Note 1) 74ACT843 AC Electrical Characteristics Symbol tPLH Parameter Propagation Delay Dn to On tPHL Propagation Delay Dn to On tPLH Propagation Delay LE to On tPHL Propagation Delay LE to On tPLH Propagation Delay PRE to On tPHL Propagation Delay CLR to On tPZH Output Enable Time OE to On tPZL Output Enable Time OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On tPHL Propagation Delay PRE to On tPLH Propagation Delay CLR to On VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 4) Min Typ Max Min Max 5.0 2.5 5.5 9.5 2.0 10.0 ns 5.0 2.5 5.5 9.5 2.0 10.0 ns 5.0 2.5 5.5 9.0 2.0 10.0 ns 5.0 2.5 5.5 9.0 2.0 10.0 ns 5.0 2.5 6.5 14.0 2.0 16.0 ns 5.0 2.5 7.5 15.5 2.0 17.5 ns 5.0 2.5 5.5 9.5 2.0 10.5 ns 5.0 2.5 5.5 9.5 2.0 10.5 ns 5.0 2.5 6.0 10.5 2.0 11.0 ns 5.0 2.5 6.0 10.5 2.0 11.0 ns 5.0 2.5 6.0 10.5 2.0 11.0 ns 5.0 2.5 5.5 9.5 2.0 10.5 ns Note 4: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol tS Parameter Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW tH Dn to LE VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 5) Typ Guaranteed Minimum 5.0 −0.5 0.5 1.0 ns 5.0 0.5 2.0 2.0 ns ns tW LE Pulse Width, HIGH 5.0 2.0 3.5 3.5 tW PRE Pulse Width, LOW 5.0 5.0 8.5 10.0 ns tW CLR Pulse Width, LOW 5.0 5.5 9.5 11.0 ns trec PRE Recovery Time 5.0 0.5 2.0 2.0 ns trec CLR Recovery Time 5.0 −0.5 1.0 1.0 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 44 pF VCC = 5.0V www.fairchildsemi.com 4 Conditions 74ACT843 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74ACT843 9-Bit Transparent Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6