74AUP1T97L6X

DATA SHEET www.onsemi.com TinyLogic) Low Power Configurable Gate with Voltage-Level Translator UDFN6 CASE 517DP 74AUP1T97 SIP6 CASE 127EB MARKING DIAGRAM Description The 74AUP1T97 is a universal configurable 2−input logic gate that provides single supply voltage level translation. This device is designed for applications with inputs switching levels that accept 1.8 V low voltage CMOS signals while operating from either a single 2.5 V or 3.3 V supply voltage. The 74AUP1T97 is an ideal low power solution for mixed voltage signal applications especially for battery−powered portable applications. This product guarantees very low static and dynamic power consumption across entire voltage range. All inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. The 74AUP1T97 provides for multiple functions as determined by various configurations of the three inputs. The potential logic functions provided are MUX, AND, NAND, OR, and NOR, inverter and buffer. Refer to Figures 3 to 9. AHKK XYZ Pin 1 Identifier AH KK XY Z ORDERING INFORMATION Device Package Shipping† 74AUP1T97FHX UDFN−6 (Pb-Free/Halide Free) 5000 / Tape & Reel 74AUP1T97L6X SIP−6 (Pb-Free/Halide Free) 5000 / Tape & Reel Features • Single Supply Voltage Translator 1.8 V to 3.3 V Input at VCC = 3.3 V ♦ 1.8 V to 2.5 V Input at VCC = 2.5 V 2.3 V to 3.6 V VCC Supply Voltage Operation 3.6 V Over−Voltage Tolerant I/O's at VCC from 2.3 V to 3.6 V Power−Off High−Impedance Inputs and Outputs Low Static Power Consumption ♦ ICC = 0.9 mA Maximum Low Dynamic Power Consumption ♦ CPD = 2.7 pF Typical at 3.3 V Ultra−Small MicroPak™ Packages ♦ • • • • • • = Specific Device Code = Lot Code = Date Code = Assembly Plant Code †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Logic Diagram A B C 3 4 1 Y 6 Figure 1. Logic Diagram (Positive Logic) © Semiconductor Components Industries, LLC, 2008 June 2022 − Rev. 2 1 Publication Order Number: 74AUP1T97/D 74AUP1T97 PIN CONFIGURATIONS Table 1. PIN DESCRIPTIONS Pin Name Description 1 B 2 GND 3 A Data Input 4 Y Output 5 VCC 6 C Data Input Ground Supply Voltage B 1 6 C GND 2 5 VCC A 3 4 Y Figure 2. MicroPakE (Top View) Data Input Table 2. FUNCTION TABLE Inputs Output C B A Y L L L L L L H L L H L H L H H H H L L L H L H H H H L L H H H H 1. H = HIGH Logic Level 2. L = LOW Logic Level Table 3. FUNCTION SELECTION TABLE Logic Function Connection Configuration 2−to−1 MUX Figure 3 2−Input AND Gate Figure 4 2−Input OR Gate with One Inverted Input Figure 5 2−Input NAND Gate with One Inverted Input Figure 5 2−Input AND Gate with One Inverted Input Figure 6 2−Input NOR Gate with One Inverted Input Figure 6 2−Input OR Gate Figure 7 Inverter Figure 8 Buffer Figure 9 www.onsemi.com 2 74AUP1T97 Logic Configurations Figure 3 through Figure 9 show the logical functions that can be implemented using the 74AUP1T97. The diagrams show the DeMorgan’s equivalent logic duals for a given two−input function. The logical implementation is next to the board−level physical implementation of how the pins of the function should be connected. VCC VCC C B B 1 2 A 3 Y A 6 5 4 C C Y 1 2 Y A D 3 A GND 6 5 4 C Y GND Note: 1. When C is L, Y = B. 2. When C is H, Y = A. Figure 4. 2−Input AND Gate Figure 3. 2−to−1 MUX VCC VCC C C Y A C Y A Y B A 1 2 6 5 C 3 4 Y B C Y B GND 1 2 6 5 C 3 4 Y GND Figure 6. 2−Input AND Gate with One Inverted Input 2−Input NOR Gate with One Inverted Input Figure 5. Input OR Gate with One Inverted Input 2−Input NAND Gate with One Inverted Input VCC VCC C B Y B 1 2 6 5 C 3 4 Y C Y 1 2 6 5 C 3 4 Y GND GND Figure 8. Inverter Figure 7. 2−Input OR Gate VCC B 1 B Y 2 6 5 3 4 GND Figure 9. Buffer www.onsemi.com 3 Y 74AUP1T97 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VCC Supply Voltage VIN DC Input Voltage VOUT Min. Max. Unit −0.5 4.6 V −0.5 4.6 V −0.5 −0.5 VCC + 0.5 4.6 V DC Output Voltage HIGH or LOW State(Note 3) VCC = 0 V IIK DC Input Diode Current VIN < 0 V − −50 mA IOK DC Output Diode Current VOUT < 0 V VOUT > VCC − −50 +50 mA DC Output Source / Sink Current − ±50 mA Continuous Output Current − ±20 mA DC VCC or Ground Current per Supply Pin − ±50 mA IOH / IOL IO ICC or IGND TSTG −65 +150 °C TJ Junction Temperature Under Bias − +150 °C TL Junction Lead Temperature, Soldering 10s − +260 °C PD Power Dissipation at +85°C − 130 120 mW − 5000+ 2000 V ESD Storage Temperature Range MicroPak−6 MicroPak2−6 Human Body Model, JEDEC:JESD22−A114 Charged Device Model, JEDEC:JESD22−C101 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. IO absolute maximum rating must be observed. Table 4. RECOMMENDED OPERATING CONDITIONS (Note 4) Symbol Parameter VCC Supply Voltage VIN Input Voltage Conditions Min Max Unit 2.3 3.6 V 0 3.6 V VOUT Output Voltage VCC = 0 V HIGH or LOW State 0 0 3.6 VCC V IOH / IOL Output Current VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V − ±4.0 ±3.1 mA −40 +85 °C − 500 560 °C/W TA Operating Free−Air Temperature qJA Thermal Resistance MicroPak−6 MicroPak2−6 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Unused inputs must be held HIGH or LOW. They may not float. www.onsemi.com 4 74AUP1T97 Table 5. DC ELECTRICAL CHARACTERISTICS TA = +255C Symbol VP VN VH VOH Conditions VCC (V) Min Max Min Max Unit Positive Threshold Voltage − 2.3 V to 2.7 V 0.60 1.10 0.60 1.10 V 3.0 V to 3.6 V 0.75 1.16 0.75 1.19 V Negative Threshold Voltage − 2.3 V to 2.7 V 0.35 0.60 0.35 0.60 V 3.0 V to 3.6 V 0.50 0.85 0.50 0.85 V Hysteresis Voltage − 2.3 V to 2.7 V 0.23 0.60 0.10 0.60 V 3.0 V to 3.6 V 0.25 0.56 0.15 0.56 V IOH = −20 mA 2.3 V ≤ VCC ≤ 3.6 V VCC −0.1 − VCC −0.1 − V IOH = −2.3 mA 2.3 V 2.05 − 1.97 − V 1.90 − 1.85 − V 2.72 − 2.67 − V 2.60 − 2.55 − V Parameter HIGH Level Output Voltage IOH = −3.1 mA IOH = −2.7 mA 3.0 V IOH = −4 mA VOL LOW Level Output Voltage IOL = 20 mA 2.3 V ≤ VCC ≤ 3.6 V − 0.10 − 0.10 V IOL = 2.3 mA 2.3 V − 0.31 − 0.33 V − 0.44 − 0.45 V − 0.31 − 0.33 V − 0.44 − 0.45 V 0 V to 3.6 V − ±0.10 − ±0.50 mA IOH = 3.1 mA IOL = 2.7 mA 3.0 V IOL = 4.0 mA IIN TA = −405C to +855C Input Leakage Current 0 ≤ VIN ≤ 3.6 IOFF Power Off Leakage Current 0 ≤ (VIN,VO) ≤ 3.6 0V − 0.10 − 0.50 mA DIOFF Additional Power Off Leakage Current VIN or VO = 0 V to 3.6 V 0 V to 0.2 V − 0.20 − 0.60 mA Quiescent Supply Current VIN = VCC or GND 2.3 V to 3.6 V − 0.50 − 0.90 mA − − − ±0.90 mA Increase in ICC per Input One Input at 0.3 V or 1.1 V, other Inputs at 0 or VCC 2.3 V to 2.7 V − − − 4 mA One Input at 0.45 V or 1.2 V, other Inputs at 0 or VCC 3.0 V to 3.6 V − − − 12 mA ICC DICC VCC ≤ VIN ≤ 3.6 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5 74AUP1T97 Table 6. AC ELECTRICAL CHARACTERISTICS TA = −40 to +855C TA = +25°C Symbol tPHL, tPLH Parameter Propagation Delay Conditions VCC (V) Min Typ Max Typ Max Unit Figure CL = 5 pF, RL = 1 MW 2.30 V ≤ VCC ≤ 2.70 V, VIN = 1.65 V to 1.95 V 1.1 3.7 5.5 1.1 6.8 ns 2.30 V ≤ VCC ≤ 2.70 V VIN = 2.30 V to 2.70 V 1.1 3.8 6.5 1.1 7.0 Figure 10 & 11 2.30 V ≤ VCC ≤ 2.70 V, VIN = 3.0 V to 3.60 V 1.1 3.9 6.0 1.1 6.5 3.00 V ≤ VCC ≤ 3.60 V, VIN = 1.65 V to 1.95 V 1.0 3.3 4.9 1.0 8.0 3.00 V ≤ VCC ≤ 3.60 V, VIN = 2.30 V to 2.70 V 1.0 3.2 4.6 1.0 5.8 3.00 V ≤ VCC ≤ 3.60 V, VIN = 3.00 V to 3.60 V 1.0 3.1 4.7 1.0 5.5 2.30 V ≤ VCC ≤ 2.70 V, VIN = 1.65 V to 1.95 V 1.3 4.1 6.5 1.0 7.9 2.30 V ≤ VCC ≤ 2.70 V, VIN = 2.30 V to 2.70 V 1.3 4.0 6.2 1.0 7.1 2.30 V ≤ VCC ≤ 2.70 V, VIN = 3.0 V to 3.60 V 1.3 3.7 5.7 1.0 6.5 3.00 V ≤ VCC ≤ 3.60 V, VIN = 1.65 V to 1.95 V 1.3 3.5 5.6 1.0 8.5 3.00 V ≤ VCC ≤ 3.60 V, VIN = 2.30 V to 2.70 V 1.3 3.4 5.3 1.0 6.1 3.00 V ≤ VCC ≤ 3.60 V, VIN = 3.00 V to 3.60 V 1.3 3.3 5.2 1.0 5.9 2.30 V ≤ VCC ≤ 2.70 V, VIN = 1.65 V to 1.95 V 1.5 4.6 6.9 1.0 8.7 2.30 V ≤ VCC ≤ 2.70 V, VIN = 2.30 V to 2.70 V 1.5 4.4 6.8 1.0 7.9 2.30V ≤ VCC ≤ 2.70 V, VIN = 3.0 V to 3.60 V 1.5 4.2 6.3 1.0 7.4 3.00 V ≤ VCC ≤ 3.60 V, VIN = 1.65 V to 1.95 V 1.3 3.9 6.2 1.0 9.1 3.00 V ≤ VCC ≤ 3.60 V, VIN = 2.30 V to 2.70 V 1.3 3.8 5.6 1.0 6.8 3.00 V ≤ VCC ≤ 3.60 V, VIN = 3.00 V to 3.60 V 1.3 3.8 5.6 1.0 6.2 2.30 V ≤ VCC ≤ 2.70 V, VIN = 1.65 V to 1.95 V 1.3 4.2 7.9 1.3 8.5 2.30 V ≤ VCC ≤ 2.70 V, VIN = 2.30 V to 2.70 V 1.3 3.9 7.9 1.3 8.5 2.30V ≤ VCC ≤ 2.70 V, VIN = 3.0 V to 3.60 V 1.0 3.7 7.3 1.0 8.9 3.00 V ≤ VCC ≤ 3.60 V, VIN = 1.65 V to 1.95 V 1.3 3.5 6.1 1.3 7.9 3.00V ≤ VCC ≤ 3.60 V, VIN = 2.30 V to 2.70 V 1.1 3.0 5.9 1.1 6.8 3.00 V ≤ VCC ≤ 3.60 V, VIN = 2.30 V to 2.70 V 1.0 2.7 5.7 1.0 6.5 pF − CL = 10 pF, RL = 1 MW CL = 15 pF, RL = 1 MW CL = 30 pF, RL = 1 MW CIN COUT CPD Input Capacitance − 0 − 2.1 − − − Output Capacitance Power Dissipation Capacitance − − 0 − 3.0 − − − 2.30 V ≤ VCC ≤ 2.70 V − 2.0 − − − 3.00 V ≤ VCC ≤ 3.60 V − 2.7 − − − www.onsemi.com 6 74AUP1T97 AC LOADINGS AND WAVEFORMS Figure 11. AC Waveforms Figure 10. AC Test Circuit VCC Symbol 3.3 V +0.3 V 2.5 V +0.2 V Vmi VIN / 2 VIN / 2 Vmo VCC / 2 VCC / 2 MicroPak is trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SIP6 1.45X1.0 CASE 127EB ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13590G SIP6 1.45X1.0 DATE 31 AUG 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN6 1.0X1.0, 0.35P CASE 517DP ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13593G UDFN6 1.0X1.0, 0.35P DATE 31 AUG 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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