74AUP2G97DPJ

74AUP2G97 Low-power dual PCB configurable multiple function gate Rev. 3 — 22 July 2019 Product data sheet 1. General description The 74AUP2G97 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: • HBM JESD22-A114F exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G97DP -40 °C to +125 °C TSSOP10 plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1 74AUP2G97GU -40 °C to +125 °C XQFN10 plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.40 × 1.80 × 0.50 mm SOT1160-1 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 4. Marking Table 2. Marking Type number Marking code [1] 74AUP2G97DP aV 74AUP2G97GU aV [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram nA nY nB nC Fig. 1. aaa-015396 Logic symbol (one gate) 6. Pinning information 6.1. Pinning 9 1Y 3 8 2C 2Y 4 7 2B GND 5 6 2A Product data sheet VCC 1Y 9 8 2B aaa-015399 Pin configuration SOT552-1 (TSSOP10) 74AUP2G97 6 Transparent top view aaa-015397 Fig. 2. 2 5 2 1C 2A 1B 1C 2C 4 10 VCC 7 GND 1 1 3 1A 1B 2Y 74AUP2G97 1A terminal 1 index area 10 74AUP2G97 Fig. 3. Pin configuration SOT1160-1 (XQFN10) All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 2 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 6.2. Pin description Table 3. Pin description Symbol Pin Description SOT552-1 SOT1160-1 1A, 2A 1, 6 10, 5 data input 1B, 2B 2, 7 1, 6 data input 1C, 2C 3, 8 2, 7 data input 1Y, 2Y 9, 4 8, 3 data output GND 5 4 ground (0 V) VCC 10 9 supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Output Input nC nB nA nY L L L L L L H L L H L H L H H H H L L L H L H H H H L L H H H H 7.1. Logic configurations Table 5. Function selection table Logic function Figure 2-input MUX see Fig. 4 2-input AND see Fig. 5 2-input OR with one input inverted see Fig. 6 2-input NAND with one input inverted see Fig. 6 2-input AND with one input inverted see Fig. 7 2-input NOR with one input inverted see Fig. 7 2-input OR see Fig. 8 Inverter see Fig. 9 Buffer see Fig. 10 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 3 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate VCC VCC nB nA nB 2, 7 nY 5 nA 1, 6 3, 8 nC 9, 4 2, 7 nA nC 10 nY nY 3, 8 5 nA nC 10 1, 6 9, 4 nY nC aaa-015402 aaa-015401 Pin numbers are not valid for SOT1160-1 package Fig. 4. 2-input MUX Pin numbers are not valid for SOT1160-1 package Fig. 5. 2-input AND gate VCC nA nC nY 2, 7 5 nA nC nY nA 1, 6 3, 8 VCC nB nC nC nY nB 2, 7 3, 8 5 10 nB nC nY 9, 4 10 1, 6 nY 9, 4 2-input NAND gate with input A inverted or 2-input OR gate with input C inverted Pin numbers are not valid for SOT1160-1 package Fig. 7. 2-input NOR gate with input B inverted or 2-input AND gate with input C inverted VCC VCC nB nC nB nY 2, 7 5 1, 6 3, 8 nC 2, 7 10 9, 4 nC nY nY 3, 8 5 1, 6 nC 10 9, 4 aaa-015405 nY aaa-015406 Pin numbers are not valid for SOT1160-1 package Fig. 8. nY aaa-015404 aaa-015403 Pin numbers are not valid for SOT1160-1 package Fig. 6. nC 2-input OR gate Pin numbers are not valid for SOT1160-1 package Fig. 9. Inverter VCC nB nB nY 2, 7 5 1, 6 3, 8 10 9, 4 nY aaa-015407 Pin numbers are not valid for SOT1160-1 package Fig. 10. Buffer 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 4 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +4.6 V -50 - -0.5 +4.6 -50 - -0.5 +4.6 V - ±20 mA 50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] VI < 0 V [1] Tamb = -40 °C to +125 °C [1] [2] mA V mA The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT552-1 (TSSOP10) packages: Ptot derates linearly with 8.3 mW/K above 120 °C. For SOT1160-1 (XQFN10) packages: Ptot derates linearly with 7.1 mW/K above 115 °C. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCC V 0 3.6 V Tamb ambient temperature -40 +125 °C Unit Active mode Power-down mode; VCC = 0 V 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max VCC - 0.1 - - V IO = -1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 1.11 - - V IO = -1.9 mA; VCC = 1.65 V 1.32 - - V IO = -2.3 mA; VCC = 2.3 V 2.05 - - V IO = -3.1 mA; VCC = 2.3 V 1.9 - - V IO = -2.7 mA; VCC = 3.0 V 2.72 - - V IO = -4.0 mA; VCC = 3.0 V 2.6 - - V Tamb = 25 °C VOH HIGH-level output voltage VI = VT+ or VTIO = -20 μA; VCC = 0.8 V to 3.6 V 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 5 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate Symbol Parameter Conditions VOL VI = VT+ or VT- LOW-level output voltage Min Typ Max Unit IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V 0.3 × VCC V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF IO = -20 μA; VCC = 0.8 V to 3.6 V VCC - 0.1 - - V IO = -1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 1.03 - - V IO = -1.9 mA; VCC = 1.65 V 1.30 - - V IO = -2.3 mA; VCC = 2.3 V 1.97 - - V IO = -3.1 mA; VCC = 2.3 V 1.85 - - V IO = -2.7 mA; VCC = 3.0 V 2.67 - - V IO = -4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V [1] Tamb = -40 °C to +85 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT- VI = VT+ or VT0.3 × VCC V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.6 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 μA 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 [1] © Nexperia B.V. 2019. All rights reserved 6 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate Symbol Parameter Conditions Min Typ Max Unit IO = -20 μA; VCC = 0.8 V to 3.6 V VCC - 0.11 - - V IO = -1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 0.93 - - V IO = -1.9 mA; VCC = 1.65 V 1.17 - - V IO = -2.3 mA; VCC = 2.3 V 1.77 - - V IO = -3.1 mA; VCC = 2.3 V 1.67 - - V IO = -2.7 mA; VCC = 3.0 V 2.40 - - V IO = -4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V Tamb = -40 °C to +125 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT- VI = VT+ or VT0.33 × VCC V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 μA [1] [1] One input at VCC - 0.6 V, other input at VCC or GND. 10.1. Transfer characteristics Table 9. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 16. Symbol Parameter VT+ positive-going threshold voltage 74AUP2G97 Product data sheet Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 0.8 V 0.30 - 0.60 0.30 0.60 0.30 0.62 V VCC = 1.1 V 0.53 - 0.90 0.53 0.90 0.53 0.92 V VCC = 1.4 V 0.74 - 1.11 0.74 1.11 0.74 1.13 V VCC = 1.65 V 0.91 - 1.29 0.91 1.29 0.91 1.31 V VCC = 2.3 V 1.37 - 1.77 1.37 1.77 1.37 1.80 V VCC = 3.0 V 1.88 - 2.29 1.88 2.29 1.88 2.32 V see Fig. 11 and Fig. 12 All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 7 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate Symbol Parameter VT- Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 0.8 V 0.10 - 0.60 0.10 0.60 0.10 0.60 V VCC = 1.1 V 0.26 - 0.65 0.26 0.65 0.26 0.65 V VCC = 1.4 V 0.39 - 0.75 0.39 0.75 0.39 0.75 V VCC = 1.65 V 0.47 - 0.84 0.47 0.84 0.47 0.84 V VCC = 2.3 V 0.69 - 1.04 0.69 1.04 0.69 1.04 V VCC = 3.0 V 0.88 - 1.24 0.88 1.24 0.88 1.24 V VCC = 0.8 V 0.07 - 0.50 0.07 0.50 0.07 0.50 V VCC = 1.1 V 0.08 - 0.46 0.08 0.46 0.08 0.46 V VCC = 1.4 V 0.18 - 0.56 0.18 0.56 0.18 0.56 V VCC = 1.65 V 0.27 - 0.66 0.27 0.66 0.27 0.66 V VCC = 2.3 V 0.53 - 0.92 0.53 0.92 0.53 0.92 V VCC = 3.0 V 0.79 - 1.31 0.79 1.31 0.79 1.31 V see Fig. 11 and Fig. 12 negative-going threshold voltage VH 25 °C (VT+ - VT-); see Fig. 11, Fig. 12, Fig. 13 and Fig. 14 hysteresis voltage 10.2. Waveforms transfer characteristics VO VI VT+ mna208 VT+ and VT- limits at 70 % and 20 %. mna207 Fig. 11. Transfer characteristic Fig. 12. Definition of VT+, VT- and VH 001aad691 240 VH VT- VO VI VH VT- VT+ 001aad692 1200 ICC (µA) ICC (µA) 160 800 80 400 0 0 0.4 0.8 1.2 1.6 VI (V) 2.0 Fig. 13. Typical transfer characteristics; VCC = 1.8 V 74AUP2G97 Product data sheet 0 0 1.0 2.0 VI (V) 3.0 Fig. 14. Typical transfer characteristics; VCC = 3.0 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 8 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 11. Dynamic characteristics Table 10. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 16. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max Min Max - 23.0 - - - - - ns VCC = 1.1 V to 1.3 V 2.8 6.6 12.6 2.5 13.0 2.5 13.2 ns VCC = 1.4 V to 1.6 V 2.3 4.7 7.6 2.5 8.2 2.5 8.6 ns VCC = 1.65 V to 1.95 V 2.2 3.9 6.2 2.0 6.8 2.0 7.2 ns VCC = 2.3 V to 2.7 V 2.0 3.2 4.5 1.7 5.1 1.7 5.3 ns VCC = 3.0 V to 3.6 V 1.9 2.8 3.9 1.5 4.1 1.5 4.3 ns CL = 5 pF tpd propagation nA, nB, nC to nY; see Fig. 15 delay VCC = 0.8 V [2] CL = 10 pF tpd propagation nA, nB, nC to nY; see Fig. 15 delay VCC = 0.8 V [2] - 26.6 - - - - - ns VCC = 1.1 V to 1.3 V 3.2 7.4 14.3 2.9 14.9 2.9 15.2 ns VCC = 1.4 V to 1.6 V 2.6 5.3 8.7 2.8 9.4 2.8 9.8 ns VCC = 1.65 V to 1.95 V 2.5 4.5 7.0 2.3 7.8 2.3 8.2 ns VCC = 2.3 V to 2.7 V 2.4 3.7 5.2 2.1 5.9 2.1 6.1 ns VCC = 3.0 V to 3.6 V 2.3 3.4 4.6 1.9 4.9 1.9 5.1 ns - 30.1 - - - - - ns VCC = 1.1 V to 1.3 V 3.6 8.2 16.0 3.2 16.7 3.2 17.0 ns VCC = 1.4 V to 1.6 V 2.9 5.9 9.6 3.1 10.4 3.1 10.9 ns VCC = 1.65 V to 1.95 V 2.8 5.0 7.8 2.5 8.7 2.5 9.1 ns VCC = 2.3 V to 2.7 V 2.7 4.2 5.8 2.4 6.5 2.4 6.9 ns VCC = 3.0 V to 3.6 V 2.5 3.8 5.1 2.2 5.5 2.2 5.7 ns - 38.3 - - - - - ns VCC = 1.1 V to 1.3 V 4.6 10.5 20.9 4.0 21.8 4.0 22.2 ns VCC = 1.4 V to 1.6 V 3.7 7.4 12.2 3.8 13.3 3.8 14.0 ns VCC = 1.65 V to 1.95 V 3.5 6.3 9.9 3.2 11.1 3.2 11.8 ns VCC = 2.3 V to 2.7 V 3.4 5.3 7.4 3.1 8.3 3.1 8.8 ns VCC = 3.0 V to 3.6 V 3.2 4.9 6.6 2.8 7.0 2.8 7.4 ns CL = 15 pF tpd propagation nA, nB, nC to nY; see Fig. 15 delay VCC = 0.8 V [2] CL = 30 pF tpd propagation nA, nB, nC to nY; see Fig. 15 delay VCC = 0.8 V 74AUP2G97 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 9 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max Min Max - 2.6 - - - - - pF - 2.8 - - - - - pF VCC = 1.4 V to 1.6 V - 2.9 - - - - - pF VCC = 1.65 V to 1.95 V - 3.1 - - - - - pF VCC = 2.3 V to 2.7 V - 3.7 - - - - - pF VCC = 3.0 V to 3.6 V - 4.3 - - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF fi = 1 MHz; VI = GND to VCC power dissipation VCC = 0.8 V capacitance VCC = 1.1 V to 1.3 V CPD [1] [2] [3] [3] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 10 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 11.1. Waveforms and test circuit VI nA, nB, nC input VM VM GND tPHL tPLH VOH VM nY output VM VOL tPLH tPHL VOH nY output VM VM VOL aaa-015383 Measurement points are given in Table 11. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 15. Input nA, nB and nC to output nY propagation delay times Table 11. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns VCC G VI DUT VEXT 5 kΩ VO RT CL RL 001aac521 Test data is given in Table 12. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 16. Test circuit for measuring switching times Table 12. Test data Supply voltage Load VEXT VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ open GND 2VCC [1] For measuring enable and disable times, RL = 5 kΩ. For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 11 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 12. Package outline TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm D E SOT552-1 A X c y HE v M A Z 6 10 A2 pin 1 index (A3) A1 A θ Lp L 1 5 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.15 0.23 0.15 3.1 2.9 3.1 2.9 0.5 5.0 4.8 0.95 0.7 0.4 0.1 0.1 0.1 0.67 0.34 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-07-29 03-02-18 SOT552-1 Fig. 17. Package outline SOT552-1 (TSSOP10) 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 12 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate XQFN10: plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.40 x 1.80 x 0.50 mm SOT1160-1 X D B A terminal 1 index area E A A1 A3 detail X e1 e v w b 3 5 C C A B C y1 C y L 2 6 1 7 e2 terminal 1 index area 10 L1 8 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A A1 0.5 0.05 A3 b 0.25 0.127 0.20 0.00 0.15 D E e e1 e2 1.5 1.4 1.3 1.9 1.8 1.7 0.4 0.8 0.4 L L1 0.45 0.55 0.40 0.50 0.35 0.45 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1160-1 --- --- --- sot1160-1_po European projection Issue date 09-12-28 09-12-29 Fig. 18. Package outline SOT1160-1 (XQFN10) 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 13 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 13. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PCB Printed-Circuit Board 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2G97 v.3 20190722 Product data sheet - 74AUP2G97 v.2 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74AUP2G97GF (SOT1081-2) removed. 74AUP2G97 v.2 20151202 Modifications: • • 74AUP2G97 v.1 20141104 74AUP2G97 Product data sheet Product data sheet - 74AUP2G97 v.1 Maximum value temperature range TSSOP10 (74AUP2G97DP) changed from 85 °C to 125 °C. Removed 74AUP2G97GM (SOT1049-3). Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 - © Nexperia B.V. 2019. All rights reserved 14 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74AUP2G97 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 15 / 16 74AUP2G97 Nexperia Low-power dual PCB configurable multiple function gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 7.1. Logic configurations.....................................................3 8. Limiting values............................................................. 5 9. Recommended operating conditions..........................5 10. Static characteristics..................................................5 10.1. Transfer characteristics..............................................7 10.2. Waveforms transfer characteristics............................8 11. Dynamic characteristics.............................................9 11.1. Waveforms and test circuit.......................................11 12. Package outline........................................................ 12 13. Abbreviations............................................................ 14 14. Revision history........................................................14 15. Legal information......................................................15 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 July 2019 74AUP2G97 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 July 2019 © Nexperia B.V. 2019. All rights reserved 16 / 16 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74AUP2G97GUX 74AUP2G97GFX 74AUP2G97DPJ