74F251APC

Revised September 2000 74F251A 8-Input Multiplexer with 3-STATE Outputs General Description Features The 74F251A is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. ■ Multifunctional capability ■ On-chip select logic decoding ■ Inverting and non-inverting 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74F251ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F251ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F251APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009504 www.fairchildsemi.com 74F251A 8-Input Multiplexer with 3-STATE Outputs April 1988 74F251A Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL S0–S2 Select Inputs 1.0/1.0 20 µA/−0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA I0–I7 Multiplexer Inputs 1.0/1.0 20 µA/−0.6 mA Z 3-STATE Multiplexer Output 150/40 (33.3) −3 mA/24 mA (20 mA) Z Complementary 3-STATE Multiplexer Output 150/40 (33.3) −3 mA/24 mA (20 mA) Truth Table Functional Description This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is: Inputs Z = OE •(I0•S0•S1 •S2 + I1•S0•S 1•S2 + I2•S0•S1•S2 + I3•S0•S1•S2 + I4•S0•S1•S2 + I5•S0•S1•S2 + I6•S0•S1•S2 + I7•S0•S1•S2) When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltages. Outputs OE S2 S1 S0 Z H X X X Z Z L L L L I0 I0 L L L H I1 I1 L L H L I2 I2 L L H H I3 I3 L H L L I4 I4 L H L H I5 I5 L H H L I6 I6 L H H H I7 I7 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Z Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH 2.0 Units VIH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VOL Output LOW Voltage IIH Input HIGH IBVI Input HIGH Current ICEX Output HIGH Leakage Current Test IOD Circuit Current Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCL Power Supply Current ICCZ Power Supply Current IIN = −18 mA IOH = −3 mA V Min 0.5 V Min IOL = 24 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V 4.75 Output Leakage IIL Recognized as a LOW Signal Min IOH = −1 mA IOH = −3 mA 10% VCC Breakdown Test Input Leakage Conditions Recognized as a HIGH Signal IOH = −1 mA Current VID VCC V IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 15 22 mA Max VO = LOW 16 24 mA Max VO = HIGH Z −60 3 www.fairchildsemi.com 74F251A Absolute Maximum Ratings(Note 1) 74F251A AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = 5.0V VCC = 5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 3.5 6.0 9.0 3.5 11.5 3.5 9.5 tPHL Sn to Z 3.2 5.0 7.5 3.2 8.0 3.2 7.5 tPLH Propagation Delay 4.5 7.5 10.5 3.5 14.0 4.5 12.5 tPHL Sn to Z 4.0 6.0 8.5 3.0 10.5 4.0 9.0 tPLH Propagation Delay 3.0 5.0 6.5 2.5 8.0 3.0 7.0 tPHL In to Z 1.5 2.5 4.0 1.5 6.0 1.5 5.0 tPLH Propagation Delay 3.5 5.0 7.0 2.5 9.0 2.5 8.0 tPHL In to Z 3.5 5.5 7.0 3.5 9.0 3.5 7.5 tPZH Output Enable Time 2.5 4.3 6.0 2.0 7.0 2.5 7.0 tPZL OE to Z 2.5 4.3 6.0 2.5 7.5 2.5 6.5 tPHZ Output Disable Time 2.5 4.0 5.5 2.5 6.0 2.5 6.0 tPLZ OE to Z 1.5 3.0 4.5 1.5 5.0 1.5 4.5 tPZH Output Enable Time 3.5 5.0 7.0 3.0 8.5 3.0 7.5 tPZL OE to Z 3.5 5.5 7.5 3.5 9.0 3.5 8.0 tPHZ Output Disable Time 2.0 3.8 5.5 2.0 5.5 2.0 5.5 tPLZ OE to Z 1.5 3.0 4.5 1.5 5.5 1.5 4.5 www.fairchildsemi.com 4 Units ns ns ns ns ns ns 74F251A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com 74F251A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74F251A 8-Input Multiplexer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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