Revised January 2004
74F258A
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
Features
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a common data select input. The four outputs
present the selected data in the complement (inverted)
form. The outputs may be switched to a high impedance
state with a HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-oriented systems.
■ Multiplexer expansion by tying outputs together
■ Inverting 3-STATE outputs
Ordering Code:
Order Number
74F258ASC
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Logic Symbols
Connection Diagram
IEEE/IEC
© 2004 Fairchild Semiconductor Corporation
DS009508
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74F258A Quad 2-Input Multiplexer with 3-STATE Outputs
April 1988
74F258A
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
S
Common Data Select Input
1.0/1.0
20 µA/−0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
I0a–I0d
Data Inputs from Source 0
1.0/1.0
20 µA/−0.6 mA
I1a–I1d
Data Inputs from Source 1
1.0/1.0
20 µA/−0.6 mA
Za–Zd
3-STATE Inverting Data Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Functional Description
Truth Table
Output
Select
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a common Select input (S). When the Select
input is LOW, the I0x inputs are selected and when Select
is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in inverted form.
The 74F258A is the logic implementation of a 4-pole, 2position switch where the position of the switch is determined by the logic levels supplied to the Select input. The
logic equation for the outputs is shown below:
Data
Output
Enable
Input
Inputs
OE
S
I0
I1
H
X
X
X
Z
L
H
X
L
H
L
H
X
H
L
L
L
L
X
H
L
L
H
X
L
Z
Z n = OE • (I1n • S + I0n • S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs of
the 3-STATE devices are tied together, all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should
ensure that Output Enable signals to 3-STATE devices
whose outputs are tied together are designed so there is
no overlap.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
VOH
Output HIGH
10% VCC
2.5
Voltage
10% VCC
2.4
5% VCC
2.7
5% VCC
2.7
VOL
Output LOW Voltage
IIH
Input HIGH
2.0
Units
VIH
Input HIGH Current
Output HIGH
Leakage Current
VID
Input Leakage
Test
Recognized as a LOW Signal
Min
IIN = −18 mA
IOH = −3 mA
V
Min
0.5
V
Min
IOL = 24 mA
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
−0.6
mA
Max
VIN = 0.5V
IOH = −1 mA
IOH = −3 mA
10% VCC
Breakdown Test
ICEX
Conditions
Recognized as a HIGH Signal
IOH = −1 mA
Current
IBVI
VCC
V
4.75
IID = 1.9 µA
All Other Pins Grounded
VIOD = 150 mV
IOD
Output Leakage
IIL
Input LOW Current
IOZH
Output Leakage Current
50
µA
Max
VOUT = 2.7V
IOZL
Output Leakage Current
−50
µA
Max
VOUT = 0.5V
IOS
Output Short-Circuit Current
−150
mA
Max
VOUT = 0V
IZZ
Bus Drainage Test
500
µA
0.0V
VOUT = VCC
ICCH
Power Supply Current
6.2
9.5
mA
Max
VO = HIGH
ICCL
Power Supply Current
15.1
23
mA
Max
VO = LOW
ICCZ
Power Supply Current
11.3
17
mA
Max
VO = HIGH Z
Circuit Current
−60
3
All Other Pins Grounded
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74F258A
Absolute Maximum Ratings(Note 1)
74F258A
AC Electrical Characteristics
Symbol
Parameter
Min
TA = +25°C
TA = −5°C to +125°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = 5.0V
VCC = 5.0V
CL = 50 pF
CL = 50 pF
CL = 50 pF
Max
Min
Max
Min
tPLH
Propagation Delay
2.5
Typ
5.3
2.0
7.5
2.0
6.0
tPHL
In to Z n
1.0
4.0
1.0
6.0
1.0
5.0
Max
tPLH
Propagation Delay
3.0
7.5
3.0
9.5
3.0
8.5
tPHL
S to Z n
2.5
7.0
2.5
9.0
2.5
8.0
tPZH
Output Enable Time
2.0
6.0
2.0
8.0
2.0
7.0
2.5
7.0
2.5
9.0
2.5
8.0
tPZL
tPHZ
Output Disable Time
tPLZ
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2.0
6.0
1.5
7.0
2.0
7.0
2.0
6.0
2.0
8.5
2.0
7.0
4
Units
ns
ns
ns
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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5
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74F258A Quad 2-Input Multiplexer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
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