74F524SC

Revised August 1999 74F524 8-Bit Registered Comparator General Description Features The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. ■ 8-Bit bidirectional register with bus-oriented input-output An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing “register equal to bus”, “register greater than bus” and “register less than bus” are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words. ■ Independent serial input-output to register ■ Register bus comparator with “equal to”, “greater than” and “less than” outputs ■ Cascadable in groups of eight bits ■ Open-collector expansion comparator outputs for AND-wired ■ Twos complement or magnitude compare Ordering Code: Order Number Package Number Package Description 74F524SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F524PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009546 www.fairchildsemi.com 74F524 8-Bit Registered Comparator April 1988 74F524 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description S0 , S1 Mode Select Inputs 1.0/1.0 20 µA/−0.6 mA C/SI Status Priority or Serial Data Input 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA 20 µA/−0.6 mA SE Status Enable Input (Active LOW) 1.0/1.0 M Compare Mode Select Input 1.0/1.0 20 µA/−0.6 mA I/O0–I/O7 Parallel Data Inputs or 3.5/1.083 70 µA/−0.65 mA 150/40 (33.3) −3 mA/24 mA (20 mA) 3-STATE Parallel Data Outputs 50/33.3 −1 mA/20 mA OC (Note 1) /33.3 (Note 1) /20 mA C/SO Status Priority or Serial Data Output LT Register Less Than Bus Output EQ Register Equal Bus Output OC(Note 1) /33.3 (Note 1) /20 mA GT Register Greater Than Bus Output OC(Note 1) /33.3 (Note 1) /20 mA Note 1: OC = Open Collector Number Representation Select Table M Operation L Magnitude Compare H Twos Complement Compare Select Truth Table S0 S1 Operation L L Hold—Retains Data in Shift Register L H Read—Read Contents in Register onto Data Bus, H L Shift—Allows Serial Shifting on Next Rising Clock Edge H H Load—Load Data on Bus into Register Data Remains in Register Unaffected by Clock Status Truth Table (Hold Mode) Inputs Outputs SE C/SI Data Comparison EQ GT LT C/SO H H X H H H 1 L L L OA–OH > I/O0–I/O7 L H H X L OA–OH = I/O0–I/O7 H H H L H L OA–OH < I/O0–I/O7 L H H L H H OA–OH > I/O0–I/O7 L H L L H H OA–OH = I/O0–I/O7 H L L H L H OA–OH < I/O0–I/O7 L L H L 1 = HIGH if data are equal, otherwise LOW H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial www.fairchildsemi.com 2 icant byte to the C/SI input of the next less significant byte and also to its own SE input (see Figure 1). The C/SI input of the most significant device is held HIGH while the SE input of the least significant device is held LOW. The corresponding status outputs are AND-wired together. In the case of twos complement number compare, only the Mode input to the most significant device should be HIGH. The Mode inputs to all other cascaded devices are held LOW. The 74F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial loading. Parallel data may be read from or loaded into the registers via the data bus I/O0–I/O7. Serial data is entered from the C/SI input and may be shifted into the register and out through the C/SO output. Both parallel and serial data entry occur on the rising edge of the input clock (CP). The operation of the shift register is controlled by two signals S0 and S1 according to the Select Truth Table. The 3-STATE parallel output buffers are enabled only in the Read mode. Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, the EQ and LT outputs will be pulled LOW and the GT output will float HIGH. Also the C/SO output of the most significant device will be forced LOW, disabling the subsequent devices but enabling its own status outputs. The correct status condition is thus indicated. The same applies if the registered byte is less than the data byte, only in this case the EQ and GT outputs go LOW and LT output floats HIGH. One port of an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal register. Three active-OFF, open-collector outputs indicate whether the contents held in the shift register are “greater than”, (GT), “less than” (LT), or “equal to” (EQ) the data on the input bus. A HIGH signal on the Status Enable (SE) input disables these outputs to the OFF state. A mode control input (M) allows selection between a straightforward magnitude compare or a comparison between twos complement numbers. If an equality condition is detected in the most significant device, its C/SO output is forced HIGH. This enables the next less significant device and also disables its own status outputs. In this way, the status output priority is handed down to the next less significant device which now effectively becomes the most significant byte. The worst case propagation delay for a compare operation involving “n” cascaded 74F524s will be when an equality condition is detected in all but the least significant byte. In this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take 35 + 6(n−2) ns. For “greater than” or “less than” detection, the C/SI input must be held HIGH, as indicated in the Status Truth Table. The internal logic is arranged such that a LOW signal on the C/SI input disables the “greater than” and “less than” outputs. The C/SO output will be forced HIGH if the “equal to” status condition exists, otherwise C/SO will be held LOW. These facilities enable the 74F524 to be cascaded for word length greater than eight bits. Word length expansion (in groups of eight bits) can be achieved by connecting the C/SO output of the more signif- Function Diagram FIGURE 1. Cascading 74F524s for Comparing Longer Words 3 www.fairchildsemi.com 74F524 Functional Description 74F524 Block Diagram Notes: 1. 3-STATE Output 2. Open-Collector Output www.fairchildsemi.com 4 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Recommended Operating Conditions 0°C to +70°C Free Air Ambient Temperature +4.5V to +5.5V Supply Voltage Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VOL 2.0 Units VIH 10% VCC 2.5 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 V 0.5 Voltage 10% VCC 0.5 Input HIGH Current Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD Output Leakage Input LOW Current IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current IOHC Open Collector, Output IIN = −18 mA Min IOH = −3 mA IOH = −1 mA −60 IOL = 20 mA (I/On) V Min 5.0 µA Max 7.0 µA Max 50 µA Max V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 70 µA Max VI/O = 2.7V −650 µA Max VI/O = 0.5V −150 mA Max VOUT = 0V 4.75 Circuit Current IIL Recognized as a LOW Signal Min IOH = −3 mA 10% VCC IIH Conditions Recognized as a HIGH Signal IOH = −1 mA Output LOW IBVI VCC V IOL = 24 mA (LT, GT, EQ, C/SO) VIN = 2.7V VIN = 7.0V VOUT = VCC (I/On, C/SO) IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded 250 µA Min VOUT = VCC ICCH Power Supply Current 128 180 mA Max VO = HIGH ICCL Power Supply Current 128 180 mA Max VO = LOW ICCZ Power Supply Current 128 180 mA Max VO = HIGH Z OFF Leakage Test 5 www.fairchildsemi.com 74F524 Absolute Maximum Ratings(Note 2) 74F524 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Shift Frequency 50 75 tPLH Propagation Delay 9.0 16.5 Max Min Max 50 20.0 9.0 MHz 21.0 tPHL I/On to EQ 5.0 9.5 12.0 5.0 13.0 tPLH Propagation Delay 8.5 14.1 19.0 8.5 20.0 tPHL I/On to GT 6.5 13.0 16.5 6.5 17.5 tPLH Propagation Delay 7.0 15.5 20.0 7.0 21.0 tPHL I/On to LT 4.5 10.0 14.0 4.5 15.0 tPLH Propagation Delay 8.0 15.2 19.5 8.0 20.5 tPHL I/On to C/SO 6.0 12.5 16.0 6.0 17.0 tPLH Propagation Delay 10.0 20.0 25.0 10.0 26.0 tPHL CP to EQ 4.0 8.5 16.5 4.0 17.5 tPLH Propagation Delay 10.0 16.5 21.0 10.0 22.0 tPHL CP to GT 8.5 17.0 22.0 8.5 23.0 tPLH Propagation Delay 9.0 20.0 25.0 9.0 26.0 tPHL CP to LT 5.5 13.5 17.0 5.5 18.0 tPLH Propagation Delay CP to C/SO (Load) 8.5 16.5 21.0 8.5 22.0 5.0 10.0 13.0 5.0 14.0 tPLH Propagation Delay tPHL CP to C/SO (Serial Shift) 4.5 9.0 11.5 4.5 12.5 tPLH Propagation Delay 9.0 15.0 19.0 9.0 20.0 tPHL C/SI to GT 3.0 6.5 8.5 3.0 9.5 tPLH Propagation Delay 8.0 15.5 20.0 8.0 21.0 tPHL C/SI to LT 3.5 6.5 8.5 3.5 9.5 tPLH Propagation Delay 6.5 11.5 14.5 6.5 15.5 tPHL S0, S1 to C/SO 5.5 14.0 18.0 5.5 19.0 tPLH Propagation Delay 3.5 8.0 10.5 3.5 11.5 tPHL SE to EQ 2.5 6.0 8.0 2.5 9.0 tPLH Propagation Delay 6.5 12.5 16.0 6.5 17.0 tPHL SE to GT 3.5 6.0 8.0 3.5 9.0 tPLH Propagation Delay 5.0 10.5 13.5 5.0 14.5 tPHL SE to LT 3.5 6.0 8.0 3.5 9.0 tPLH Propagation Delay 4.0 8.5 11.0 4.0 12.0 tPHL C/SI to C/SO 4.0 8.5 11.0 4.0 12.0 tPLH Propagation Delay 8.0 15.0 19.5 8.0 20.5 tPHL M to GT 6.0 12.0 17.5 6.0 18.5 tPLH Propagation Delay 8.0 17.0 22.0 8.0 23.0 tPHL M to LT 4.5 9.5 12.0 4.5 13.0 tPLH Propagation Delay 15.0 25.0 33.0 15.0 35.0 tPHL S0, S1 to EQ 9.0 15.0 19.0 9.0 20.0 tPLH Propagation Delay 10.5 18.0 23.0 10.5 24.0 tPHL S0, S1 to GT 10.5 18.0 23.0 10.5 24.0 tPLH Propagation Delay 13.0 22.0 28.0 13.0 30.0 tPHL S0, S1 to LT 12.0 19.0 24.0 12.0 25.0 tPZH Output Enable Time 4.5 10.0 13.0 4.5 14.0 tPZL S0, S1 to I/On 5.5 11.0 15.0 5.5 16.0 tPHZ Output Disable Time 3.5 8.0 12.0 3.5 13.0 tPLZ S0, S1 to I/On 4.5 9.6 12.5 4.5 13.5 www.fairchildsemi.com 6 Units ns ns ns ns ns ns ns ns ns ns ns 74F524 AC Operating Requirements TA = +25°C Symbol TA = 0°C to +70°C VCC = +5.0V Parameter Min Max VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 6.0 6.0 tS(L) I/On to CP 6.0 6.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) I/On to CP 0 0 tS(H) Setup Time, HIGH or LOW 10.0 10.0 tS(L) S0 or S1 to CP 10.0 10.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) S0 or S1 to CP 0 0 tS(H) Setup Time, HIGH or LOW 7.0 7.0 tS(L) C/SI to CP 7.0 7.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) C/SI to CP tW(H) Clock Pulse Width, HIGH 7 0 0 5.0 5.0 Units Max ns ns ns ns www.fairchildsemi.com 74F524 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B www.fairchildsemi.com 8 74F524 8-Bit Registered Comparator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com