74F533SC

Revised October 2000 74F533 Octal Transparent Latch with 3-STATE Outputs General Description Features The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted. ■ Eight latches in a single package ■ 3-STATE outputs for bus interfacing ■ Inverted version of the 74F373 Ordering Code: Order Number Package Number Package Description 74F533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F533SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009548 www.fairchildsemi.com 74F533 Octal Transparent Latch with 3-STATE Outputs April 1988 74F533 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description D0–D7 Data Inputs 1.0/1.0 20 µA/−0.6 mA LE Latch Enable Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA OE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA O0–O7 Complementary 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Functional Description Function Table Inputs The 74F533 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Output LE OE D O H L H L H L L H L L X O0 X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V VCC Pin Potential to −0.5V to +7.0V Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 2: Either voltage limit or current limit is sufficient to protect inputs. in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current 2.0 Input HIGH Current Output HIGH Leakage Current VID Input Leakage Test IOD Recognized as a LOW Signal Min IIN = −18 mA IOH = −3 mA V Min 0.5 V Min IOL = 24 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 0.5 mA Max VIN = 5.5V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V IOH = −1 mA IOH = −3 mA 10% VCC Breakdown (I/O) ICEX Conditions Recognized as a HIGH Signal IOH = −1 mA Breakdown Test IBVIT VCC V 4.75 Output Leakage Circuit Current IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IIL Input LOW Current IOZH Output Leakage Current 50 µA Max VOUT = 2.7V IOZL Output Leakage Current −50 µA Max VOUT = 0.5V IOS Output Short-Circuit Current −150 mA Max VOUT = 0V IZZ Bus Drainage Test 500 µA 0.0V VOUT = 5.25V ICCZ Power Supply Current 61 mA Max VO = HIGH Z −60 41 3 www.fairchildsemi.com 74F533 Absolute Maximum Ratings(Note 1) 74F533 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 4.0 6.7 9.0 4.0 12.0 4.0 10.0 tPHL Dn to On 2.5 4.4 7.0 2.5 9.0 2.5 8.0 tPLH Propagation Delay 5.0 7.1 11.0 5.0 14.0 5.0 13.0 tPHL LE to On 3.0 4.7 7.0 3.0 9.0 3.0 8.0 tPZH Output Enable Time 2.0 5.9 10.0 2.0 12.5 2.0 11.0 2.0 5.6 7.5 2.0 10.5 2.0 8.5 tPZL tPHZ Output Disable Time tPLZ 1.5 3.4 6.5 1.5 8.5 1.5 7.0 1.5 2.7 5.5 1.5 7.5 1.5 6.5 Units ns ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 2.0 2.0 2.0 tS(L) Dn to LE 2.0 2.0 2.0 tH(H) Hold Time, HIGH or LOW 3.0 3.0 3.0 tH(L) Dn to LE 3.0 3.0 3.0 tW(H) LE Pulse Width, HIGH 6.0 6.0 6.0 www.fairchildsemi.com 4 Units Max ns ns ns 74F533 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74F533 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74F533 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com