74F899QC

Revised August 1999 74F899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description Features The 74F899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability of 24 mA at the A-bus and 64 mA at the B-bus. ■ Latchable transceiver with output sink of 24 mA at the A-bus and 64 mA at the B-bus The 74F899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. ■ Select pin for ODD/EVEN parity ■ ERRA and ERRB output pins for parity checking ■ Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A ■ Independent latch enables for A-to-B and B-to-A directions ■ Ability to simultaneously generate and check parity ■ May be used in systems applications in place of the 74F543 and 74F280 ■ May be used in system applications in place of the 74F657 and 74F373 (no need to change T/R to check parity) Ordering Code: Order Number Package Number Package Description 74F899SC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F899QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for SOIC Pin Assignment for PCC Logic Symbol © 1999 Fairchild Semiconductor Corporation DS010195 www.fairchildsemi.com 74F899 9-Bit Latchable Transceiver February 1989 74F899 Input Loading/Fan-Out HIGH/LOW Pin Names A0–A7 U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−0.6 mA Description Data Inputs/ 1.0/1.0 Data Outputs 150/40 −3 mA/24 mA B0–B7 Data Inputs/ 1.0/1.0 20 µA/−0.6 mA Data Outputs 600/106.6 −12 mA/64 mA APAR A Bus Parity 1.0/1.0 20 µA/−0.6 mA Input/Output 150/40 −3 mA/24 mA BPAR B Bus Parity 1.0/1.0 20 µA/−0.6 mA Input/Output 600/106.6 −12 mA/64 mA 1.0/1.0 20 µA/−0.6 mA ODD/EVEN Parity Select Input GBA, GAB Output Enable Inputs 1.0/1.0 20 µA/−0.6 mA SEL Mode Select Input 1.0/1.0 20 µA/−0.6 mA LEA, LEB Latch Enable Inputs 1.0/1.0 20 µA/−0.6 mA ERRA, ERRB Error Signal Outputs 50/33.3 −1 mA/20 mA Pin Descriptions Pin Names Description A0–A7 A Bus Data Inputs/Data Outputs B0–B7 B Bus Data Inputs/Data Outputs APAR, BPAR A and B Bus Parity Inputs ODD/EVEN ODD/EVEN Parity Select, Active LOW for EVEN Parity GBA, GAB Output Enables for A or B Bus, Active LOW SEL Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode LEA, LEB Latch Enables for A and B Latches, HIGH for Transparent Mode ERRA, ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Functional Description • Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU). The 74F899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. • Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA). www.fairchildsemi.com • Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table). 2 74F899 Function Table Inputs Operation GAB GBA SEL LEA LEB H H X X X Busses A and B are 3-STATE. H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. H L L H H Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. H L L X L Generates parity from B latch data based on O/E. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB. H L H X H BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. H L H H H BPAR/B[0:7] → APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L H L H L Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. L H L H H Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. L H L L X Generates parity from A latch data based on O/E. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA. L H H H L APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H H APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: O/E = ODD/EVEN Functional Block Diagram 3 www.fairchildsemi.com 74F899 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 3: Either voltage limit or current limit is sufficient to protect inputs. Twice the Rated IOL (mA) in LOW State (Max) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Typ Max 2.0 Units VCC Conditions V Recognized as a 0.8 V Recognized as a −1.2 V HIGH Signal LOW Signal Voltage VOL Output LOW 10% VCC 2.5 10% VCC 2.4 10% VCC 2.0 5% VCC 2.7 5% VCC 2.7 Min IIN = −18 mA IOH = −1 mA IOH = −3 mA IOH = −15 mA (Bn, BPAR) V IOH = −1 mA IOH = −3 mA 10% VCC 0.5 5% VCC 0.55 IOL = 20 mA Voltage (An, APAR, ERRA, ERRB) IOL = 24 mA V (An, APAR, ERRA, ERRB) 10% VCC VTH Input Threshold Voltage VOLV Negative Ground Bounce Voltage VOLP Positive Ground Bounce Voltage IIL Input Low Current IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown (I/O) ICEX Output HIGH Leakage Current VID Input Leakage Test IOD Output Leakage Circuit Current IIL Input Low Current IIH+ Output Leakage Current IOZH Current www.fairchildsemi.com IOL = 64 mA (Bn, BPAR) 0.55 1.45 V 1.0 V 1.0 V ±0.1V, Sweep Edge Rate must be > 1V/50 ns Observed on “quiet” output during simultaneous switching of remaining outputs Observed on “quiet” output during simultaneous switching of remaining outputs −0.6 mA Max VIN = 0.5V 5.0 µA Max VIN = 2.7V 7.0 µA Max 0.5 mA Max 50 µA Max V 0.0 3.75 µA 0.0 −0.6 mA Max 4.75 70 4 µA Max VIN = 7.0V (ODD/EVEN, GBA, GAB, SEL, LEA, LEB) VIN = 5.5V (An, Bn, APAR, BPAR) VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VI/O = 2.7V (An, Bn, APAR, BPAR) Symbol Parameter IIL+ Output Leakage IOZL Current IOS Output Short-Circuit Current Min (Continued) Typ Max Units −650 −60 µA −150 VCC Max Max mA Bus Drainage Test ICCH Power Supply Current ICCL Power Supply Current Conditions VI/O = 0.5V (An, Bn, APAR, BPAR) VOUT = 0V (An, APAR, ERRA, ERRB) Max VOUT = 0V (Bn, BPAR) 500 µA 0.0V VOUT = 5.25V 132 155 mA Max VO = HIGH 178 210 mA Max −100 IZZ 74F899 DC Electrical Characteristics −225 VO = LOW, GAB = LOW, GBA = HIGH, VIL = LOW ICCZ Power Supply Current 160 190 mA Max VO = HIGH Z AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 4.0 7.5 13.0 4.0 14.0 tPHL An, APAR to Bn, BPAR 4.0 8.5 13.0 4.0 14.0 tPLH Propagation Delay 7.5 12.0 17.0 7.5 18.0 tPHL An, Bn to BPAR, APAR 7.5 12.5 17.0 7.5 18.0 tPLH Propagation Delay 7.5 12.0 17.0 7.5 18.0 tPHL An, Bn to ERRA, ERRB 7.5 12.5 17.0 7.5 18.0 tPLH Propagation Delay 4.5 7.5 11.0 4.5 12.0 tPHL ODD/EVEN to ERRA, ERRB 4.5 8.0 11.0 4.5 12.0 tPLH Propagation Delay 4.5 7.5 11.5 4.5 12.5 tPHL ODD/EVEN to APAR, BPAR 4.5 8.5 11.5 4.5 12.5 tPLH Propagation Delay 5.5 9.0 13.0 5.5 14.0 tPHL APAR, BPAR to ERRA, ERRB 5.5 9.5 13.0 5.5 14.0 tPLH LEA/LEB to 9.5 13.0 17.5 7.5 18.0 tPHL ERRA /ERRB 9.7 17.5 7.5 18.0 tPLH Propagation Delay 3.0 6.0 10.0 3.0 11.0 tPHL SEL to APAR, BPAR 3.0 7.0 10.0 3.0 11.0 tPLH Propagation Delay 3.5 7.0 10.0 3.5 11.0 tPHL LEB to An, APAR 3.5 8.0 10.0 3.5 11.0 tPLH tPHL Propagation Delay 3.5 6.5 10.0 3.5 11.0 LEA to Bn, BPAR 3.5 7.5 10.0 3.5 11.0 tPZH Output Enable Time 1.0 4.5 10.0 1.0 11.0 tPZL GBA or GAB to An, 1.0 6.5 10.0 1.0 11.0 Units Figure Number ns Figure 1 ns Figure 2 ns Figure 3 ns Figure 4 ns Figure 5 ns Figure 6 ns Figure 7 ns Figure 10 ns Figure 11 ns Figure 11 ns Figure 8, Figure 9 ns Figure 8, Figure 9 ns Figure 12, Figure 13 ns Figure 12, Figure 13 ns Figure 14 APAR or Bn, BPAR tPHZ Output Disable Time 1.0 4.0 7.0 1.0 8.0 tPLZ GBA or GAB to An, 1.0 4.0 7.0 1.0 8.0 APAR or Bn, BPAR tS(H) Setup Time, HIGH or LOW 5.0 1.6 5.0 tS(L) An, Bn to LEA, LEB 5.0 1.8 5.0 tH(H) Hold Time, HIGH or LOW 0 −1.7 0 tH(L) An, Bn to LEA, LEB 0 −1.5 0 tW Pulse Width for LEA, LEB 6.0 2.0 6.0 5 www.fairchildsemi.com 74F899 AC Path An, APAR → Bn, BPAR (Bn, BPAR → An, APAR) FIGURE 1. An → BPAR (Bn → APAR) FIGURE 2. An → ERRA (Bn → ERRB) FIGURE 3. www.fairchildsemi.com 6 74F899 AC Path (Continued) O/E → ERRA O/E → ERRB FIGURE 4. O/E → BPAR (O/E → APAR) FIGURE 5. APAR → ERRA (BPAR → ERRB) FIGURE 6. 7 www.fairchildsemi.com 74F899 AC Path (Continued) FIGURE 7. ZH, HZ FIGURE 8. ZL, LZ FIGURE 9. www.fairchildsemi.com 8 74F899 AC Path (Continued) SEL → BPAR (SEL → APAR) FIGURE 10. LEA → BPAR, B[0:7] (LEB → APAR, A[0:7]) FIGURE 11. TS(H), TH(H) LEA → APAR, A[0:7] (LEB → BPAR, B[0:7]) FIGURE 12. 9 www.fairchildsemi.com 74F899 AC Path (Continued) TS(L), TH(L) LEA → APAR, A[0:7] (LEB → BPAR, B[0:7]) FIGURE 13. FIGURE 14. www.fairchildsemi.com 10 74F899 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B 11 www.fairchildsemi.com 74F899 9-Bit Latchable Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 12