Revised April 1999
74LCX16374
Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant
Inputs and Outputs
General Description
Features
The LCX16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V VCC specifications provided
■ 6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
■ Power down high impedance inputs and outputs
The LCX16374 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
■ Supports live insertion/withdrawal (Note 1)
The LCX16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ Latch-up performance exceeds 500 mA
■ ±24 mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package Number
74LCX16374MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Description
74LCX16374MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
I0–I15
Inputs
O0–O15
Outputs
© 1999 Fairchild Semiconductor Corporation
DS012003.prf
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74LCX16374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
February 1994
74LCX16374
Functional Description
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
Operation of the OEn input does not affect the state of the
flip-flops.
The LCX16374 consists of sixteen edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
Truth Tables
Inputs
Outputs
OE1
I0–I7
O0–O7
L
H
H
L
L
L
L
L
X
X
H
X
CP1
Inputs
Outputs
OE2
I8–I15
O8–O15
L
H
H
L
L
L
O0
L
L
X
O0
Z
X
H
X
Z
CP2
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of CP
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Symbol
Parameter
Value
Conditions
VCC
Supply Voltage
−0.5 to +7.0
VI
DC Input Voltage
−0.5 to +7.0
VO
DC Output Voltage
−0.5 to +7.0
Units
V
V
3-STATE
−0.5 to VCC + 0.5
Output in HIGH or LOW State (Note 3)
IIK
DC Input Diode Current
−50
VI < GND
IOK
DC Output Diode Current
−50
VO < GND
+50
VO > VCC
V
mA
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature
−65 to +150
°C
Recommended Operating Conditions
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH/IOL
(Note 4)
Output Current
TA
Free-Air Operating Temperature
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
0
5.5
HIGH or LOW State
0
VCC
3-STATE
0
5.5
VCC = 3.0V − 3.6V
±24
VCC = 2.7V − 3.0V
±12
VCC = 2.3V − 2.7V
±8
Units
V
V
V
mA
−40
85
°C
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Conditions
VCC
(V)
VIH
VIL
VOH
VOL
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
IOH = −100 µA
TA = −40°C to +85°C
Min
2.3 − 2.7
1.7
2.7 − 3.6
2.0
V
2.3 − 2.7
0.7
2.7 − 3.6
0.8
2.3 − 3.6
2.3
1.8
IOH = −12 mA
2.7
2.2
IOH = −18 mA
3.0
2.4
IOH = −24 mA
3.0
2.2
IOL = 100 µA
2.3 − 3.6
V
0.2
IOL = 8 mA
2.3
0.6
IOL = 12 mA
2.7
0.4
IOL = 16 mA
3.0
0.4
0.55
IOL = 24 mA
3.0
Input Leakage Current
0 ≤ VI ≤ 5.5V
2.3 − 3.6
±5.0
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 5.5V
2.3 − 3.6
±5.0
0
10
VI = V IH or VIL
Power-Off Leakage Current
VI or VO = 5.5V
3
V
VCC − 0.2
IOH = −8 mA
II
IOFF
Units
Max
V
µA
µA
µA
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74LCX16374
Absolute Maximum Ratings(Note 2)
74LCX16374
DC Electrical Characteristics
Symbol
Parameter
(Continued)
VCC
Conditions
(V)
ICC
∆ICC
Quiescent Supply Current
Increase in ICC per Input
TA = −40°C to +85°C
Min
Units
Max
VI = VCC or GND
2.3 − 3.6
20
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
2.3 − 3.6
±20
VIH = VCC −0.6V
2.3 − 3.6
500
µA
µA
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = −40° to +85°C, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Min
Max
Min
Max
Min
Max
6.2
1.5
6.5
1.5
7.4
Units
fMAX
Maximum Clock Frequency
170
tPHL
Propagation Delay
1.5
tPLH
CP to On
1.5
6.2
1.5
6.5
1.5
7.4
tPZL
Output Enable time
1.5
6.1
1.5
6.3
1.5
7.9
1.5
6.1
1.5
6.3
1.5
7.9
Output Disable Time
1.5
6.0
1.5
6.2
1.5
7.2
1.5
6.0
1.5
6.2
1.5
7.2
tS
Setup Time
2.5
2.5
3.0
ns
tH
Hold Time
1.5
1.5
2.0
ns
tW
Pulse Width
3.0
3.0
3.5
ns
tOSHL
Output to Output Skew (Note 6)
tPZH
tPLZ
tPHZ
MHz
1.0
tOSLH
ns
ns
ns
ns
1.0
Note 6: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Conditions
VCC
(V)
TA = 25°C
Units
Typical
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.6
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
−0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.6
V
V
Capacitance
Typical
Units
CIN
Symbol
Input Capacitance
Parameter
VCC = Open, VI = 0V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
20
pF
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Conditions
4
74LCX16374
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
Symbol
VCC
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH − 0.3V
VOH − 0.3V
VOH − 0.15V
5
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74LCX16374
Schematic Diagram Generic for LCX Family
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6
74LCX16374
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
7
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74LCX16374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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