74VHC595MX

Revised April 1999 74VHC595 8-Bit Shift Register with Output Latches General Description The VHC595 is an advanced high-speed CMOS Shift Register fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has eight 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: tPD = 5.4 ns (typ) at VCC = 5V ■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.9V (typ) ■ Pin and function compatible with 74HC595 Ordering Code: Order Number Package Number 74VHC595M 74VHC595SJ 74VHC595MTC 74VHC595N M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS011640.prf www.fairchildsemi.com 74VHC595 8-Bit Shift Register with Output Latches August 1993 74VHC595 Pin Descriptions Pin Names Truth Table Description Inputs Function SER Serial Data Input SCK Shift Register Clock Input (Active rising edge) RCK Storage Register Clock Input (Active rising edge) SCLR Reset Input SER RCK SCK SCLR G X X X X H QA thru QH 3-STATE X X X X L QA thru QH outputs enabled X X X L L Shift Register cleared X ↑ H L Shift Register clocked Q′H = 0 G 3-STATE Output Enable Input (Active LOW) L QA - QH Parallel Data Outputs H X ↑ H L Shift Register clocked Q’H Serial Data Output X ↑ X H L Contents of Shift QN = Qn-1, Q0 = SER = L QN = Qn-1, Q0 = SER = H Register transferred to output latches Timing Diagram www.fairchildsemi.com 2 74VHC595 Logic Diagram (positive logic) 3 www.fairchildsemi.com 74VHC595 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT ) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC/GND Current (ICC) ±75 mA VCC = 3.3V ±0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ±0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH HIGH Level Input Voltage VIL VOL IOZ TA = 25°C Min TA = −40°C to +85°C Typ Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH VCC (V) Parameter Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 V VIN = VIH V IOH = −50 µA or VIL 4.4 IOH = −4 mA V LOW Level 2.0 0.0 0.1 0.1 Output Voltage 3.0 0.0 0.1 0.1 4.5 0.0 3-STATE Conditions V 3.0 − 5.5 HIGH Level Units 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 ±0.25 ±2.5 Output VIN = VIH V IOL = 50 µA or VIL IOL = 4 mA V IOL = 8 mA VIN = VCC or GND µA Off-State IOH = −8 mA VOUT = VCC or GND VING = VIH or VIL Current IIN Input Leakage Current ICC Quiescent Supply Current 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND Noise Characteristics Symbol Parameter VOLP Quiet Output Maximum (Note 3) Dynamic VOL VOLV Quiet Output Minimum (Note 3) Dynamic VOL VIHD Minimum HIGH Level (Note 3) Dynamic Input Voltage VILD Maximum LOW Level (Note 3) Dynamic Input Voltage TA = 25°C VCC (V) Typ Limits 5.0 0.9 1.2 5.0 −0.9 −1.2 5.0 3.5 5.0 1.5 Note 3: Parameter guaranteed by design. www.fairchildsemi.com 4 Units V V V V Conditions CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Parameter VCC (V) tPLH Propagation Delay Time 3.3 ± 0.3 tPHL RCK to QA–QH Symbol TA = +25°C Min 5.0 ± 0.5 tPLH Propagation Delay Time tPHL SCK–Q'H 3.3 ± 0.3 5.0 ± 0.5 tPHL Propagation Delay Time 3.3 ± 0.3 SCLR –Q'H 5.0 ± 0.5 tPZL Output Enable Time tPZH G to QA–QH 3.3 ± 0.3 5.0 ± 0.5 TA = −40°C to +85°C Typ Max Min Max 7.7 11.9 1.0 13.5 10.2 15.4 1.0 17.0 5.4 7.4 1.0 8.5 6.9 9.4 1.0 10.5 8.8 13.0 1.0 15.0 11.3 16.5 1.0 18.5 6.2 8.2 1.0 9.4 7.7 10.2 1.0 11.4 8.4 12.8 1.0 13.7 10.9 16.3 1.0 17.2 5.9 8.0 1.0 9.1 7.4 10.0 1.0 11.1 7.5 11.5 1.0 13.5 9.0 15.0 1.0 17.0 4.8 8.6 1.0 10.0 8.3 10.6 1.0 12.0 tPLZ Output Disable Time 3.3 ± 0.3 12.1 15.7 1.0 16.2 tPHZ G to QA–QH 5.0 ± 0.5 7.6 10.3 1.0 11.0 fMAX Maximum Clock 3.3 ± 0.3 Frequency 5.0 ± 0.5 80 150 70 55 130 50 135 185 115 95 155 85 Units CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns ns CL = 50 pF RL = 1 kΩ CL = 15 pF ns ns CL = 50 pF RL = 1 kΩ 3.3 ± 0.3 1.5 1.5 tOSHL Skew 5.0 ± 0.5 1.0 1.0 CIN Input Capacitance 5.0 10 10 COUT Output Capacitance 6.0 CPD Power Dissipation 87 ns pF pF pF CL = 50 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF MHz Output to Output CL = 15 pF CL = 50 pF MHz tOSLH Capacitance Conditions CL = 50 pF (Note 4) CL = 50 pF CL = 50 pF VCC = Open VCC = 5.0V (Note 5) Note 4: Parameter guaranteed by design. tOSLH = | tPLH max − tPLH min|; tOSHL = | tPHL max − tPHL min|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC. 5 www.fairchildsemi.com 74VHC595 AC Electrical Characteristics 74VHC595 AC Operating Requirements Symbol tS tS tS tH tH tH tW(L) Parameter TA = 25°C VCC (V) Typ TA = −40°C to +85°C Guaranteed Minimum 3.3 ± 0.3 3.5 3.5 (SER–SCK) 5.0 ± 0.5 3.0 3.0 Minimum Setup Time 3.3 ± 0.3 8.0 8.5 (SCK–RCK) 5.0 ± 0.5 5.0 5.0 Minimum Setup Time 3.3 ± 0.3 8.0 9.0 (SCLR –RCK) 5.0 ± 0.5 5.0 5.0 Minimum Hold Time 3.3 ± 0.3 1.5 1.5 (SER–SCK) 5.0 ± 0.5 2.0 2.0 Minimum Hold Time 3.3 ± 0.3 0.0 0.0 (SCK–RCK) 5.0 ± 0.5 0.0 0.0 Minimum Hold Time 3.3 ± 0.3 0.0 0.0 (SCLR –RCK) 5.0 ± 0.5 0.0 0.0 Minimum Pulse Width 3.3 ± 0.3 5.0 5.0 (SCLR) 5.0 ± 0.5 5.0 5.0 Minimum Setup Time tW(L) Minimum Pulse Width 3.3 ± 0.3 5.0 5.0 tW(H) (SCK) 5.0 ± 0.5 5.0 5.0 tW(L) Minimum Pulse Width 3.3 ± 0.3 5.0 5.0 tW(H) (RCK) 5.0 ± 0.5 5.0 5.0 trem Minimum Removal Time 3.3 ± 0.3 3.0 3.0 (SCLR –SCK) 5.0 ± 0.5 2.5 2.5 www.fairchildsemi.com 6 Units ns ns ns ns ns ns ns ns ns ns 74VHC595 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74VHC595 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC595 8-Bit Shift Register with Output Latches Physical Dimensions inches (millimeters) unless otherwise noted (Continued)