CAV24C32C4CTR

CAV24C32 EEPROM Serial 32-Kb I2C -Automotive Grade 1 Description The CAV24C32 is a EEPROM Serial 32−Kb I2C devices, internally organized as 4096 words of 8 bits each. It features a 32−byte page write buffer and supports the Standard (100 kHz) and Fast (400 kHz) I2C protocol. External address pins make it possible to address up to eight CAV24C32 devices on the same bus. Features • • • • • • • • • • • • Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified Supports Standard and Fast I2C Protocol 2.5 V to 5.5 V Supply Voltage Range 32−Byte Page Write Buffer Hardware Write Protection for Entire Memory CAV Prefix for Automotive and Other Applications Requiring Site and Change Control Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention SOIC, TSSOP 8−lead, and WLCSP 4−Ball and 5−Ball Packages This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant www.onsemi.com WLCSP5 C5A SUFFIX CASE 567JQ WLCSP4 C4C SUFFIX CASE 567JY SOIC−8 W SUFFIX CASE 751BD TSSOP−8 Y SUFFIX CASE 948AL PIN CONFIGURATIONS (Top Views) 1 1 2 VCC VSS SCL 2 3 A A B SDA B SDA VSS VCC C WP WLCSP4 (C4C) SCL WLCSP5 (C5A) A0 VCC SCL 1 VCC A1 WP A2 SCL VSS SDA SOIC (W), TSSOP (Y) CAV24C32 A2, A1, A0 SDA For the location of Pin 1, please consult the corresponding package drawing. WP PIN FUNCTION Pin Name VSS A0, A1, A2 Figure 1. Functional Symbol This document contains information on some products that are still under development. ON Semiconductor reserves the right to change or discontinue these products without notice. © Semiconductor Components Industries, LLC, 2017 April, 2019 − Rev. 5 1 Function Device Address Input SDA Serial Data Input/Output SCL Serial Clock Input WP Write Protect Input VCC Power Supply VSS Ground ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Publication Order Number: CAV24C32/D CAV24C32 DEVICE MARKINGS (TSSOP−8) (SOIC−8) C32F AYMXXX G C32F A Y M XXX G 24C32F AYMXXX G = Specific Device Code = Assembly Location = Production Year (Last Digit) = Production Month (1-9, O, N, D) = Last Three Digits of Assembly Lot Number = Pb−Free Package 24C32F A Y M XXX G (WLCSP−5) = Specific Device Code = Assembly Location = Production Year (Last Digit) = Production Month (1-9, O, N, D) = Last Three Digits of Assembly Lot Number = Pb−Free Package (WLCSP−4) 2 YW 2 Y W B YW = Specific Device Code = Production Year Code = Production Workweek Code B Y W = Specific Device Code = Production Year Code = Production Workweek Code Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature –65 to +150 °C Voltage on any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute maximum ratings, irrespective of VCC. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Min Units 1,000,000 Program/Erase Cycles 100 Years Data Retention 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol ICCR ICCW Parameter Read Current Write Current Test Conditions Max Units 1 mA 2 mA 5 mA 2 mA −0.5 0.3 x VCC V A0, A1, A2 and WP 0.7 x VCC VCC + 0.5 V SCL and SDA 0.7 x VCC 5.5 Read, fSCL = 400 kHz Write, fSCL = 400 kHz ISB Standby Current All I/O Pins at GND or VCC IL I/O Pin Leakage Pin at GND or VCC VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage Min TA = −40°C to +125°C VCC > 2.5 V, IOL = 3 mA 0.4 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2 CAV24C32 Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Parameter Symbol Conditions Max Units 8 pF CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V, TA = 25°C, VCC = 5.0 V CIN (Note 4) Input Capacitance (other pins) VIN = 0 V, TA = 25°C, VCC = 5.0 V 6 pF IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA VIN < VIH, VCC = 3.3 V 120 VIN < VIH, VCC = 2.5 V 80 VIN < VIH 2 VIN < VIH, VCC = 5.5 V 50 VIN < VIH, VCC = 3.3 V 35 VIN < VIH, VCC = 2.5 V 25 VIN > VIH 2 IA (Note 5) Address Input Current (A0, A1, A2) Product Rev F mA 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. Table 5. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 6) Standard FSCL tHD:STA Clock Frequency Max Min 100 START Condition Hold Time tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock Max Units 400 kHz 4 0.6 ms 4.7 1.3 ms 4 0.6 ms 4.7 0.6 ms Data In Hold Time 0 0 ms Data In Setup Time 250 100 ns tSU:STA START Condition Setup Time tHD:DAT tSU:DAT tR SDA and SCL Rise Time 1000 300 ns tF (Note 6) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti (Note 6) 4 0.6 ms 4.7 1.3 ms 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time 0 tHD:WP WP Hold Time 2.5 tPU (Notes 7, 8) 0.9 100 100 tSU:WP tWR 6. 7. 8. Min Parameter Symbol Fast ms ns 100 0 ns ms 2.5 ms Write Cycle Time 5 5 ms Power−up to Ready Mode 1 1 ms Test conditions according to “AC Test Conditions” table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Drive Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Time ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Level 0.5 x VCC Output Test Load Current Source IOL = 3 mA; CL = 100 pF www.onsemi.com 3 CAV24C32 I2C Bus Protocol Power-On Reset (POR) Each CAV24C32 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power. The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition Pin Description SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CAV24C32, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A2, A1 and A0, must match the logic state of the similarly named input pins. The R/W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 3). Acknowledge During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. Functional Description The CAV24C32 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAV24C32 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 A2 A1 A0 DEVICE ADDRESS Figure 3. Slave Address Bits www.onsemi.com 4 R/W CAV24C32 BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 4. Acknowledge Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:SDA tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 5. Bus Timing WRITE OPERATIONS Byte Write Acknowledge Polling To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 6). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 7). As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). Delivery State The CAV24C32 is shipped erased, i.e., all bytes are FFh. www.onsemi.com 5 CAV24C32 BUS ACTIVITY: S T A MASTER R T ADDRESS BYTE SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7 − a0 d7 − d0 a15 − a8 S S T O P P * * * * A C K A C K SLAVE *a15 − a12 are don’t care bits A C K A C K Figure 6. Byte Write Sequence SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: S T A MASTER R T ADDRESS BYTE SLAVE ADDRESS DATA BYTE n ADDRESS BYTE DATA BYTE n+1 S T O P DATA BYTE n+P P S n=1 P ≤ 31 A C K A C K A C K SLAVE A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE DATA BYTE 1 8 a7 a0 9 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing www.onsemi.com 6 A C K A C K CAV24C32 READ OPERATIONS Immediate Read Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 11). To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 10). The Slave then returns to Standby mode. Sequential Read Selective Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 12). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte BUS ACTIVITY MASTER N O S T A R T S A T CO K P SLAVE ADDRESS P S A C K SLAVE SCL 8 SDA DATA BYTE 9 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: S T A MASTER R T ADDRESS BYTE SLAVE ADDRESS S T A R T ADDRESS BYTE S N O A C K SLAVE ADDRESS P S A C K SLAVE A C K A C K A C K DATA BYTE Figure 11. Selective Read Sequence N O A C K BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K A C K S T O P P SLAVE A C K DATA BYTE n DATA BYTE n+1 DATA BYTE n+2 Figure 12. Sequential Read Sequence www.onsemi.com 7 S T O P DATA BYTE n+x CAV24C32 ORDERING INFORMATION Specific Device Marking Package Type Lead Finish Shipping† CAV24C32C5ATR (Note 10) 2 WLCSP5 SnAgCu Tape & Reel, 5,000 Units / Reel CAV24C32C5CTR (Note 10) P WLCSP5 with Die Coat SnAgCu Tape & Reel, 5,000 Units / Reel CAV24C32C4CTR (Note 10) B WLCSP4 with Die Coat SnAgCu Tape & Reel, 5,000 Units / Reel 24C32F SOIC−8, JEDEC NiPdAu Tape & Reel, 3,000 Units / Reel CAV24C32YE−G (Note 10) C32F TSSOP−8 NiPdAu Tube, 100 Units / Tube CAV24C32YE−GT3 C32F TSSOP−8 NiPdAu Tape & Reel, 3,000 Units / Reel Device Order Number CAV24C32WE−GT3 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. Please contact your nearest ON Semiconductor Sales office for availability. 11. Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light the EEPROM cells lose their stored data. ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP5, 1.34x0.91 CASE 567JQ ISSUE A SCALE 4:1 E 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. DIMENSION b IS MEASURED AT THE MAXIMUM BALL DIAMETER PARALLEL TO DATUM C. A B ÈÈ PIN A1 REFERENCE D DIE COAT (OPTIONAL) 0.10 C 2X 0.10 C DATE 09 JUN 2015 A3 A2 DIM A A1 A2 A3 b D E e e1 TOP VIEW A2 DETAIL A DETAIL A 0.10 C A 0.05 C A1 SIDE VIEW NOTE 3 5X 0.03 C SEATING PLANE GENERIC MARKING DIAGRAM* XYW e b 0.05 C A B C MILLIMETERS MIN MAX 0.35 −−− 0.08 0.12 0.23 REF 0.025 REF 0.16 0.20 1.34 BSC 0.91 BSC 0.40 BSC 0.693 BSC e1 C B A 1 2 3 BOTTOM VIEW X Y W = Specific Device Code = Year = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* A1 PACKAGE OUTLINE 5X 0.69 PITCH 0.18 0.40 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON82067F WLCSP5, 1.34X0.91 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP4, 0.77x0.77 CASE 567JY ISSUE C DATE 07 MAR 2017 SCALE 4:1 A E PIN A1 REFERENCE ÈÈ D TOP VIEW NOTE 6 A3 DIE COAT (OPTIONAL) DETAIL A A2 0.05 C A DETAIL A 0.05 C A1 NOTE 4 NOTE 5 4X C SIDE VIEW NOTE 3 SEATING PLANE A2 DIM A A1 A2 A3 b D E e e X YW B 0.03 C A 1 X Y W 2 BOTTOM VIEW 0.40 PITCH 1 PACKAGE OUTLINE 4X 0.40 PITCH = Specific Device Code = Year = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* A MILLIMETERS MIN NOM MAX −−− −−− 0.35 0.04 0.06 0.08 0.23 REF 0.025 REF 0.15 0.155 0.16 0.75 0.77 0.79 0.75 0.77 0.79 0.40 BSC GENERIC MARKING DIAGRAM* e b 0.05 C A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF THE SOLDER BALLS. 5. DIMENSION b IS MEASURED AT THE MAXIMUM CONTACT BALL DIAMETER PARALLEL TO DATUM C. 6. BACKSIDE COATING IS OPTIONAL. B 0.16 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON85186F WLCSP4, 0.77X0.77 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 DATE 19 DEC 2008 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 A θ c e b SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. DOCUMENT NUMBER: DESCRIPTION: 98AON34272E SOIC 8, 150 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O DATE 19 DEC 2008 b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.90 e 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 1.05 0.75 8º e TOP VIEW D A2 A A1 SIDE VIEW c q1 L1 L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. DOCUMENT NUMBER: DESCRIPTION: 98AON34428E TSSOP8, 4.4X3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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