CAV24C64

CAV24C64 64-Kb I2C CMOS Serial EEPROM Description The CAV24C64 is a 64−Kb CMOS Serial EEPROM device, internally organized as 8192 words of 8 bits each. It features a 32−byte page write buffer and supports the Standard (100 kHz) and Fast (400 kHz) I2C protocol. External address pins make it possible to address up to eight CAV24C64 devices on the same bus. Features http://onsemi.com • • • • • • • • • • • • Automotive Temperature Grade 1 (−40°C to +125°C) Supports Standard and Fast I2C Protocol 2.5 V to 5.5 V Supply Voltage Range 32−Byte Page Write Buffer Hardware Write Protection for Entire Memory CAV Prefix for Automotive and Other Applications Requiring Site and Change Control Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention SOIC, TSSOP 8−lead Packages This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant VCC SOIC−8 W SUFFIX CASE 751BD TSSOP−8 Y SUFFIX CASE 948AL PIN CONFIGURATION A0 A1 A2 VSS SOIC (W), TSSOP (Y) For the location of Pin 1, please consult the corresponding package drawing. 1 VCC WP SCL SDA PIN FUNCTION Pin Name A0, A1, A2 SDA SCL Function Device Address Input Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground SCL CAV24C64 SDA WP VCC A2, A1, A0 WP VSS ORDERING INFORMATION VSS See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Figure 1. Functional Symbol © Semiconductor Components Industries, LLC, 2011 March, 2011 − Rev. 0 1 Publication Order Number: CAV24C64/D CAV24C64 DEVICE MARKINGS (TSSOP−8) C64F AYMXXX G C64F A Y M XXX G = Specific Device Code = Assembly Location = Production Year (Last Digit) = Production Month (1-9, O, N, D) = Last Three Digits of Assembly Lot Number = Pb−Free Package (SOIC−8) 24C64F AYMXXX G 24C64F A Y M XXX G = Specific Device Code = Assembly Location = Production Year (Last Digit) = Production Month (1-9, O, N, D) = Last Three Digits of Assembly Lot Number = Pb−Free Package Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Ratings –65 to +150 –0.5 to +6.5 Units °C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute maximum ratings, irrespective of VCC. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program/Erase Cycles Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol ICCR ICCW ISB IL VIL VIH VOL Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage A0, A1, A2 and WP SCL and SDA Output Low Voltage VCC > 2.5 V, IOL = 3 mA Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC −0.5 0.7 x VCC 0.7 x VCC TA = −40°C to +125°C Min Max 1 2 5 2 0.3 x VCC VCC + 0.5 5.5 0.4 V Units mA mA mA mA V V http://onsemi.com 2 CAV24C64 Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol CIN (Note 4) CIN (Note 4) IWP (Note 5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V, TA = 25°C VIN = 0 V, TA = 25°C VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.3 V VIN < VIH, VCC = 2.5 V VIN > VIH IA (Note 5) Address Input Current (A0, A1, A2) Product Rev F VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.3 V VIN < VIH, VCC = 2.5 V VIN > VIH Max 8 6 130 120 80 2 50 35 25 2 mA Units pF pF mA 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. Table 5. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 6) Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (Note 6) tSU:STO tBUF tAA tDH Ti (Note 6) tSU:WP tHD:WP tWR tPU (Notes 7, 8) Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power−up to Ready Mode 0 2.5 5 1 100 100 0 2.5 5 1 4 4.7 3.5 100 100 4 4.7 4 4.7 0 250 1000 300 0.6 1.3 0.9 Parameter Min Max 100 0.6 1.3 0.6 0.6 0 100 300 300 Min Fast Max 400 Units kHz ms ms ms ms ms ns ns ns ms ms ms ns ns ms ms ms ms 6. Test conditions according to “AC Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC ≤ 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA; CL = 100 pF http://onsemi.com 3 CAV24C64 Power-On Reset (POR) Each CAV24C64 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. Functional Description The CAV24C64 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAV24C64 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition I2C Bus Protocol An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CAV24C64, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A2, A1 and A0, must match the logic state of the similarly named input pins. The R/W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 3). Acknowledge During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS Figure 3. Slave Address Bits http://onsemi.com 4 CAV24C64 BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) ACK SETUP (≥ tSU:DAT) 1 8 9 BUS RELEASE DELAY (RECEIVER) Figure 4. Acknowledge Timing tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA tHIGH tLOW tR tHD:DAT tSU:DAT tSU:STO tDH tBUF Figure 5. Bus Timing WRITE OPERATIONS Byte Write Acknowledge Polling To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 6). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 7). Page Write As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAV24C64 is shipped erased, i.e., all bytes are FFh. http://onsemi.com 5 CAV24C64 BUS ACTIVITY: S T A MASTER R T S SLAVE *a15 − a13 are don’t care bits. A C K ADDRESS BYTE a15 − a8 ** * A C K A C K A C K ADDRESS BYTE a7 − a0 DATA BYTE d7 − d0 S T O P P SLAVE ADDRESS Figure 6. Byte Write Sequence SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: S T A MASTER R T S SLAVE SLAVE ADDRESS ADDRESS BYTE ADDRESS BYTE DATA BYTE n DATA BYTE n+1 DATA BYTE n+P S T O P P A C K A C K A C K A C K A C K A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE 1 SCL 8 9 1 DATA BYTE 8 SDA a7 a0 tSU:WP d7 d0 WP tHD:WP Figure 9. WP Timing http://onsemi.com 6 CAV24C64 READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 10). The Slave then returns to Standby mode. Selective Read Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 11). Sequential Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte BUS ACTIVITY: S T A MASTER R T S SLAVE If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 12). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. N O SLAVE ADDRESS S AT CO KP P A C K 9 DATA BYTE SCL 8 SDA 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: S T A MASTER R T S SLAVE A C K A C K A C K S T A R T S A C K DATA BYTE N O A C K SLAVE ADDRESS ADDRESS BYTE ADDRESS BYTE SLAVE ADDRESS S T O P P Figure 11. Selective Read Sequence BUS ACTIVITY: MASTER SLAVE ADDRESS A C K A C K A C K N O A C K S T O P P SLAVE A C K DATA BYTE n DATA BYTE n+1 DATA BYTE n+2 DATA BYTE n+x Figure 12. Sequential Read Sequence http://onsemi.com 7 CAV24C64 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 θ 0º 8º D h A1 A θ c e SIDE VIEW b L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 8 CAV24C64 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL A A1 A2 b E1 E c D E E1 e L L1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 NOM MAX 1.20 0.15 0.90 1.05 0.30 0.20 3.00 6.40 4.40 0.65 BSC 1.00 REF 3.10 6.50 4.50 0.50 0.60 0.75 θ e 0º 8º TOP VIEW D A2 A q1 c A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. L1 END VIEW L http://onsemi.com 9 CAV24C64 Example of Ordering Information CAV24C64WE−GT3 (Note 11) Prefix CAV Device # 24C64 Suffix W E −G T3 Company ID Product Number 24C64 Package W: SOIC, JEDEC Y: TSSOP Temperature Range E = Automotive (−40°C to +125°C) Lead Finish G: NiPdAu Tape & Reel (Note 13) T: Tape & Reel 3: 3,000 / Reel 9. All packages are RoHS-compliant (Lead-free, Halogen-free). 10. The standard lead finish is NiPdAu. 11. The device used in the above example is a CAV24C64WE−GT3 (SOIC, Automotive Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 12. For other package options, please contact your nearest ON Semiconductor Sales office. 13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. 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