CS8101
Micropower 5.0 V, 100 mA
Low Dropout Linear
Regulator with RESET
and ENABLE
The CS8101 is a precision 5.0 V micropower voltage regulator with
very low quiescent current (70 mA typ at 100 mA load). The 5.0 V
output is accurate within ±2.0% and supplies 100 mA of load current
with a typical dropout voltage of only 400 mV. Microprocessor control
logic includes an ENABLE input and an active RESET. This
combination of low quiescent current, outstanding regulator
performance and control logic makes the CS8101 ideal for any battery
operated, microprocessor controlled equipment.
The active RESET circuit includes hysteresis, and operates
correctly at an output voltage as low as 1.0 V. The RESET function is
activated during the power up sequence or during normal operation if
the output voltage drops outside the regulation limits by more than
200 mV typ. The logic level compatible ENABLE input allows the user
to put the regulator into a shutdown mode where it draws only 20 mA
typical of quiescent current.
The regulator is protected against reverse battery, short circuit, over
voltage, and thermal overload conditions. The device can withstand
load dump transients making it suitable for use in automotive
environments.
The CS8101 is functionally equivalent to the National
Semiconductor LP2951 series low current regulators.
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SO−20 WB
DWF SUFFIX
CASE 751D
20
1
8
1
SOIC−8
D SUFFIX
CASE 751
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
Features
•
•
•
•
•
•
•
•
•
5.0 V ±2.0% Output
Low 70 mA Quiescent Current
Active RESET
ENABLE Input for ON/OFF and Active/Sleep Mode Control
100 mA Output Current Capability
Fault Protection
− +60 V Peak Transient Voltage
− −15 V Reverse Voltage Short Circuit Thermal Overload
Low Reverse Current (Output to Input)
Internally Fused Leads Available in SO−20 WB Package
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 19
1
Publication Order Number:
CS8101/D
CS8101
PIN CONNECTIONS
VOUT
1
SOIC−8
8
VOUTSense
ENABLE
ENABLE
NC
NC
GND
GND
GND
GND
NC
NC
RESET
VIN
NC
NC
GND
RESET
1
SO−20WB
20
VOUT
VIN
NC
GND
GND
GND
GND
NC
NC
NC
VOUT
VIN
Current Source
(Circuit Bias)
Over Voltage
Shutdown
Internally
connected on
SO−20WB
ENABLE
Current Limit
Sense
+
Error
− Amplifier
VOUT
Sense
Thermal
Protection
Bandgap
Reference
RESET
+
−
Reset Comparator
GND
Figure 1. Block Diagram
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2
CS8101
MAXIMUM RATINGS*
Rating
Value
Unit
Internally Limited
−
−15, 60
V
Operating DC Voltage
30
V
ENABLE (Up to VIN with external resistor)
10
V
Internally Limited
−
ESD Susceptibility (Human Body Model)
2.0
kV
ESD Susceptibility (Machine Model)
200
V
Operating Temperature
−40 to +125
°C
Junction Temperature Range
−40 to +150
°C
Storage Temperature Range
−55 to +150
°C
260 peak
240 peak
°C
°C
Power Dissipation
Peak Transient Voltage (46 V Load Dump @ VIN = 14 V)
Output Current
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 1)
Reflow (SMD styles only) (Notes 2 & 3)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 10 second maximum.
2. 60 second maximum above 183°C.
3. −5°C / +0°C allowable conditions.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (6.0 V ≤ VIN ≤ 26 V; IOUT = 1.0 mA; −40 ≤ TA ≤ 125, −40°C ≤ TJ ≤ 150°C,
unless otherwise noted.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Voltage, VOUT
9.0 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 100 mA
6.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 100 mA
4.90
4.85
5.00
5.00
5.10
5.15
V
V
Dropout Voltage (VIN − VOUT)
IOUT = 100 mA
IOUT = 100 mA
−
−
400
100
600
150
mV
mV
Load Regulation
VIN = 14 V, 100 mA ≤ IOUT ≤ 100 mA
−
5.0
50
mV
Line Regulation
6.0 < V < 26 V, IOUT = 1.0 mA
−
5.0
50
mV
Quiescent Current, (IQ) Active Mode
IOUT = 100 mA, VIN = 6.0 V
IOUT = 50 mA
IOUT = 100 mA
−
−
−
70
4.0
12
140
6.0
20
mA
mA
mA
Quiescent Current, (IQ) Sleep Mode
VOUT = OFF, VIN = 6.0 V, VENABLE = 2.0 V
−
20
50
mA
Ripple Rejection
7.0 ≤ VIN ≤ 17 V, IOUT = 100 mA, f = 120 Hz
60
75
−
dB
−
105
200
−
mA
25
125
−
mA
150
180
−
°C
Output Stage
Current Limit
Short Circuit Output Current
VOUT = 0 V
Thermal Shutdown
−
Overvoltage Shutdown
VOUT ≤ 1.0 V
30
34
38
V
Reverse Current
VOUT = 5.0 V, VIN = 0 V
−
100
200
mA
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3
CS8101
ELECTRICAL CHARACTERISTICS (continued) (6.0 V ≤ VIN ≤ 26 V; IOUT = 1.0 mA; −40 ≤ TA ≤ 125, −40°C ≤ TJ ≤ 150°C,
unless otherwise noted.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
−
0.6
1.4
1.4
2.0
−
V
V
ENABLE Input (ENABLE)
Threshold
HIGH
LOW
(VOUT OFF)
(VOUT ON)
Input Current
VENABLE = 2.4 V
−
30
100
mA
RESET Threshold
HIGH (VRH)
LOW (VRL)
VOUT Increasing
VOUT Decreasing
4.525
4.500
4.75
4.70
VOUT − 0.05
VOUT − 0.075
V
V
RESET Hysteresis
(HIGH − LOW)
25
50
100
mV
Reset Output Leakage
RESET = HIGH
VOUT ≥ VRH
−
−
25
mA
1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k
VOUT, Power up, Power down, RRESET = 10 k
−
−
0.1
0.6
0.4
1.0
V
V
Reset Functions (RESET)
Output Voltage
Low (VRLO)
Low (VRPEAK)
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
SO−20 WB
SOIC−8
LEAD SYMBOL
FUNCTION
20
1
VOUT
−
2
VOUTSENSE
1
3
ENABLE
4, 5, 6, 7
14, 15, 16, 17
4
GND
10
5
RESET
2, 3, 8, 9, 11,
12, 13, 18
6,7
NC
No Connection. True no−connect (i.e. is floating)
19
8
VIN
Input voltage.
5.0 V, ±2.0%, 100 mA output.
Kelvin connection which allows remote sensing of output voltage for improved
regulation. If remote sensing is not required, connect to VOUT.
Logic level switches output off when toggled HIGH.
Ground. All GND leads must be connected to Ground.
Active reset (accurate to VOUT ≥ 1.0 V)
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4
CS8101
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
Dropout Voltage
0.5
125°C
0.4
25°C
0.3
−40°C
0.2
0.1
0
0
10
20
30
40
50
60
70
80
90
100
Load (mA)
Figure 2. CS8101 Dropout Voltage vs. Load Over Temperature
CIRCUIT DESCRIPTION
VOLTAGE REFERENCE AND OUTPUT CIRCUITRY
For 7.0 V < VIN < 26 V
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 3).
VIN
ENABLE
VIN(H)
> 30 V
VRH
VIN
VOUT
VOUT
VRL
(1)
VRPEAK
VRLO
RESET
IOUT
Load
Dump
Current
Limit
(2)
VRPEAK
(1) = No Reset Delay Capacitor
(2) = With Reset Delay Capacitor
Short
Circuit
Figure 4. Circuit Waveform
Figure 3. Typical Circuit Waveforms for Output
Stage Protection
ENABLE Function
The ENABLE function switches the output transistor ON
and OFF. When the voltage on the ENABLE lead exceeds
1.4 V typ, the output pass transistor turns off, leaving a high
impedance facing the load. The IC will remain in Sleep
mode, drawing only 50 mA, until the voltage on this input
drops below the ENABLE threshold.
If the input voltage rises above 30 V (e.g. load dump), the
output shuts down. This response protects the internal
circuitry and enables the IC to survive unexpected voltage
transients.
Should the junction temperature of the power device
exceed 180°C (typ) the load current capability is reduced
thereby preventing thermal overload. This thermal
management function is an effective means to prevent die
overheating since the load current is the principle heat
source in the IC.
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until VOUT is within 250 mV of the regulated
output voltage, or when VOUT drops out of regulation, and
is lower than 300 mV below the regulated output voltage. A
hysteresis of 50 mV is included in the function to minimize
oscillations.
REGULATOR CONTROL FUNCTIONS
The CS8101 contains two microprocessor compatible
control functions: ENABLE and RESET (Figure 4).
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5
CS8101
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for VOUT as low
as 1.0 V.
VOUT
CS8101
COUT
RRST
VT = RESET threshold.
The circuit depicted in Figure 6 lets the microprocessor
control its power source, the CS8101 regulator. An I/O port
on the mP and the SWITCH port are used to drive the base
of Q1. When Q1 is driven into saturation, the voltage on the
ENABLE lead falls below its lower threshold. The
regulator’s output is enabled. When the drive current is
removed, the voltage on the ENABLE lead rises, the output
is switched off and the IC moves into Sleep mode where it
draws 50 mA (max).
By coupling these two controls with the ENABLE lead,
the system has added flexibility. Once the system is running,
the state of the SWITCH is irrelevant as long as the I/O port
continues to drive Q1. The microprocessor can turn off its
own power by withdrawing drive current, once the
SWITCH is open. This software control at the I/O port
allows the microprocessor to finish key housekeeping
functions before power is removed.
The logic options are summarized in Table 1.
5.0 V to mP
and System
Power
to mP
RESET
Port
RESET
CRST
Figure 5. RC Network for RESET Delay
An external RC network on the lead (Figure 5) provides
a sufficiently long delay for most microprocessor based
applications. RC values can be chosen using the following
formula:
RTOTCRST +
ƪ
−tDelay
lnǒV
Ǔ
VT*VOUT
RST*VOUT
Table 1. Logic Control of CS8101 Output
ƫ
where:
RRST = RESET Delay resistor
RIN = mP port impedance
RTOT = RRST in parallel with RIN
CRST = RESET Delay capacitor
tDelay = desired delay time
VRST = VSAT of RESET lead (0.7 V @ turn − ON)
Microprocessor
I/O Drive
Switch
ENABLE
Output
ON
Closed
LOW
ON
Open
LOW
ON
OFF
Closed
LOW
ON
Open
HIGH
OFF
The I/O port of the microprocessor typically provides
50 mA to Q1. In automotive applications the SWITCH is
connected to the ignition switch.
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6
CS8101
APPLICATION NOTES
VIN
VBAT
VOUT
VCC
0.1 mF
CS8101
500 kW
ENABLE
GND
COUT
RRST
RESET
mP
RESET
I/O Port
CRST
Q1
100 kW
500 kW
100 kW
SWITCH
Figure 6. Microprocessor Control of CS8101 Using External Switching Transistor Q1
The ENABLE pin of the CS8101 can be tied to the battery
voltage provided a series resistor is used as shown in Figure 7.
The maximum allowed voltage on the ENABLE pin without
the resistor is 10 V. Direct voltages greater than 10 V applied
to the pin without the series resistor may damage the device.
The system designer should note the turn−on threshold (typ
1.4 V) is on the ENABLE pin. The threshold will be higher
on the other side of RENABLE.
VIN
VOUT
CIN*
0.1 mF
CS8101
ENABLE
RRST
RESET
COUT**
10 mF
*CIN required if regulator is located far from the power supply filter.
RENABLE
10 k
VBAT
*COUT required for stability. Capacitor must operate at
minimum temperature expected.
ENABLE
Figure 8. Test and Application Circuit Showing
Output Compensation
60 k
0.64 V
ON/OFF
Control
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor COUT shown in Figure 8
should work for most applications, however it is not
necessarily the optimized solution.
50 k
Figure 7. Using the ENABLE pin with VBAT
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
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7
CS8101
To determine an acceptable value for COUT for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the
application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RQJA +
(2)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
IIN
VIN
IOUT
REGULATOR®
VOUT
Control
Features
IQ
Figure 9. Single Output Regulator With Key
Performance Parameters Labeled
HEAT SINKS
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
RQJA + RQJC ) RQCS ) RQSA
(3)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 9) is:
PD(max) + NJVIN(max) * VOUT(min)NjIOUT(max) ) VIN(max)IQ
150C * TA
PD
(1)
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8
CS8101
DEVICE ORDERING INFORMATION*
Package
Shipping†
CS8101YD8G
SOIC−8
(Pb−Free)
98 Units/Rail
CS8101YDR8G
SOIC−8
(Pb−Free)
2500/Tape & Reel
CS8101YDWF20G
SO−20 WB
(Pb−Free)
38 Units/Tube
CS8101YDWFR20G
SO−20 WB
(Pb−Free)
1000/Tape & Reel
Device
*Contact your local sales representative for D2PAK package option.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
SOIC−8
D SUFFIX
CASE 751
SO−20 WB
DWF SUFFIX
CASE 751D
20
8
CS810
ALYW1
G
CS8101
AWLYYWWG
1
1
CS8101 = Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= Pb−Free Package
G
= Pb−Free Package
SMART REGULATOR is a trademark of Semiconductor Components Industries, LLC.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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