Features
Description
The FA N3223-25 family of dual 4 A gate dr ivers is
designed to drive N-channel enhancement- mode
MOSFETs in low -side sw itching applications by
providing high peak current pulses dur ing the short
sw itching intervals. The driver is available w ith either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output LOW until the supply voltage is w ithin the
operating range. In addition, the drivers feature matched
internal propagation delays betw een A and B channels
for applications requiring dual gate drives w ith critical
timing, such as synchronous rectifiers. This also
enables connecting tw o drivers in parallel to effectively
double the current capability driving a single MOSFET.
Industry-Standard Pinouts
4.5-V to 18-V Operating Range
5-A Peak Sink/Source at V DD = 12 V
4.3-A Sink / 2.8-A Source at V OUT = 6 V
Choice of TTL or CMOS Input Thresholds
Three Versions of Dual Independent Drivers:
Dual Inverting + Enable (FAN3223)
Dual Non-Inverting + Enable (FAN3224)
Dual-Inputs (FAN3225)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
The FA N322X drivers incorporate Miller Drive™
architecture for the final output stage. This bipolarMOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize sw itching loss, w hile providing railto-rail voltage sw ing and reverse current capability.
12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load)
Under 20-ns Typical Propagation Delay Matched
w ithin 1 ns to the Other Channel
Double Current Capability by Paralleling Channels
8-Lead 3x3 mm MLP or 8-Lead SOIC Package
The FAN3223 offers two inverting drivers and the
FA N3224 offers tw o non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FA N3225, each channel has dual
inputs of opposite polar ity, w hich allow s configuration as
non-inverting or inverting w ith an optional enable
function using the second input. If one or both inputs are
left unconnected, internal resistors bias the inputs such
that the output is pulled LOW to hold the pow er
MOSFET OFF.
Rated from –40°C to +125°C Ambient
Automotive Qualified to AEC-Q100 (F085 Version)
Applications
Sw itch-Mode Pow er Supplies
High-Efficiency MOSFET Sw itching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
Automotive-Qualified Systems (F085 version)
ENA
1
INA
2
GND
3
INB
4
8
A
B
ENB
7
OUTA
6
VDD
5
OUTB
ENA
INA
2
GND
3
INB
4
FAN3223
A
B
ENB
INA- 1
7
OUTA
INB+
2
6
VDD
GND
3
5
OUTB
FAN3224
Figure 1.
© 2016 Semiconductor Components Industries, LLC
December-2017, Rev. 2
8
1
INB-
4
+
A
+
B
-
8
INA+
7
OUTA
6
VDD
5
OUTB
FAN3225
Pin Configurations
Publication Order Number
FAN3224/D
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
FAN3223 / FAN3224 / FAN3225
Dual 4-A High-Speed, Low-Side Gate Drivers
Packing
Method
Quantity
per Reel
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
FAN3223TMX- F085
SOIC-8
Tape & Reel
2,500
FAN3224CMPX
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
FAN3224TUMX- F085
SOIC-8
Tape & Reel
2,500
FAN3225CMPX
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
Part Number
Input
Threshold
Logic
FAN3223CMPX
FAN3223CMX
CMOS
(1)
FAN3223CMX-F085
FAN3223TMPX
Dual Inverting
Channels + Dual
Enable
FAN3223TMX
TTL
(1)
FAN3224CMX
CMOS
(1)
FAN3224CMX-F085
Dual Non-Inverting
Channels + Dual
Enable
FAN3224TMPX
FAN3224TMX
TTL
(1)
FAN3224TMX- F085
(2)
FAN3225CMX
CMOS
(1)
FAN3225CMX-F085
FAN3225TMPX
Dual Channels of Tw oInput / One-Output
Drivers
TTL
FAN3225TMX
(1)
FAN3225TMX- F085
Notes:
1. Qualified to AEC-Q100.
2. Modified UVLO thresholds.
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2
Package
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Ordering Information
Figure 2.
1
8
2
7
3
6
4
5
3x3 m m MLP-8 (Top View )
1
8
2
7
3
6
4
5
Figure 3.
SOIC-8 (Top View )
Thermal Characteristics(3)
ΘJL(4)
ΘJT(5)
ΘJA(6)
Ψ JB(7)
Ψ JT(8)
Unit
8-Lead 3x3 mm Molded Leadless Package (MLP)
1.2
64
42
2.8
0.7
°C/W
8-Pin Small Outline Integrated Circuit (SOIC)
38
29
87
41
2.3
°C/W
Package
Notes:
3.
4.
5.
6.
7.
8.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
Theta_JT (ΘJT ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 6. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (ΨJT ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 6.
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3
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Package Outlines
1
INA
2
GND
3
INB
8
A
B
4
ENA
ENB
7
OUTA
6
VDD
5
OUTB
1
INA
2
GND
3
INB
8
A
B
4
FAN3223
ENB
INA- 1
7
OUTA
INB+
2
6
VDD
GND
3
5
OUTB
INB-
4
FAN3224
Figure 4.
+
A
+
B
-
8
INA+
7
OUTA
6
VDD
5
OUTB
FAN3225
Pin Assignm ents (Repeated)
Pin Definitions
Name
Pin Description
ENA
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENB
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
GND
Ground. Common ground reference for input and output circuits.
INA
Input to Channel A.
INA+
Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA-
Inverting Input to Channel A. Connect to GND to enable output.
INB
Input to Channel B.
INB+
Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB-
Inverting Input to Channel B. Connect to GND to enable output.
OUTA
Gate Drive Output A: Held LOW unless required input(s) are present and V DD is above UVLO threshold.
OUTB
Gate Drive Output B: Held LOW unless required input(s) are present and V DD is above UVLO threshold.
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V DD is
above UVLO threshold.
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V DD is
above UVLO threshold.
Therm al Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
P1
VDD
Supply Voltage. Provides pow er to the IC.
Output Logic
FAN3223 (x=A or B)
ENx
0
0
INx
ENx
INx
(9)
INx+
INx−
OUTx
0
0
(9)
0
1
0
1
1
(9)
0
(9)
0
0
0
0
0
0
1
0
0
1
(9)
(9)
0
0
(9)
1
0
0
OUTx
(9)
(9)
1
OUTx
FAN3225 (x=A or B)
0
1
(9)
1
FAN3224 (x=A or B)
1
(9)
1
0
1
Note:
9. Default input signal if no external connection is made.
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4
1
(9)
1
1
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
ENA
VDD
VDD
100kΩ
100kΩ
ENA 1
8
ENB
VDD
100kΩ
INA
2
7
OUTA
100kΩ
GND 3
UVLO
6
VDD
VDD_OK
VDD
100kΩ
INB
5
4
OUTB
100kΩ
Figure 5.
FAN3223 Block Diagram
VDD
VDD
100kΩ
100kΩ
ENA 1
8
ENB
INA 2
7
OUTA
100kΩ
100kΩ
UVLO
GND 3
6
VDD
VDD_OK
INB 4
5
OUTB
100kΩ
100kΩ
Figure 6.
FAN3224 Block Diagram
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5
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Block Diagrams
VDD
INA+ 8
100kΩ
INA-
1
100kΩ
7
OUTA
6
VDD
5
OUTB
100kΩ
VDD_OK
GND 3
UVLO
VDD
INB+ 2
100kΩ
INB- 4
100kΩ
100kΩ
Figure 7.
FAN3225 Block Diagram
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6
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Block Diagrams
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
20.0
V
V DD
VDD to PGND
V EN
ENA and ENB to GND
GND - 0.3 V DD + 0.3
V
V IN
INA, INA+, INA–, INB, INB+ and INB– to GND
GND - 0.3 V DD + 0.3
V
OUTA and OUTB to GND
GND - 0.3 V DD + 0.3
V
V OUT
DC
TL
Lead Soldering Temperature (10 Seconds)
TJ
Junction Temperature
TSTG
Storage Temperature
+260
ºC
-55
+150
ºC
-65
+150
ºC
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
V DD
Supply Voltage Range
4.5
18.0
V
V DD
Supply Voltage Range (FAN3224TU only)
9.5
18.0
V
V EN
Enable Voltage ENA and ENB
0
V DD
V
V IN
Input Voltage INA, INA+, INA–, INB, INB+ and INB–
0
V DD
V
-2.0
V DD + 0.3
V
-40
+125
ºC
V OUT
TA
OUTA and OUTB to GND
Repetitive Pulse < 200 ns
Operating Ambient Temperature
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FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Absolute Maximum Ratings
Unless otherw ise noted, V DD=12 V, TJ =-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
18.0
V
0.70
0.95
mA
0.21
0.35
mA
Supply
V DD
Operating Range
4.5
IDD
Supply Current, Inputs / EN Not
Connected
FAN3225C
V ON
Turn-On Voltage
INA=ENA=V DD, INB=ENB=0 V
3.5
3.9
4.3
V
V OFF
Turn-Off Voltage
INA=ENA=V DD, INB=ENB=0 V
3.3
3.7
4.1
V
18.0
V
0.70
1.20
mA
0.21
0.35
mA
All except FAN3225C
(10)
FAN322xTMX-F085, FAN322xCMX-F085 (Autom otive-Qualified Versions)
V DD
Operating Range
IDD
Supply Current, Inputs / EN Not
(15)
Connected
V ON
V OFF
4.5
(15)
Turn-On Voltage
(15)
Turn-Off Voltage
All Except FAN3225C
(10)
FAN3225C
INA=ENA=V DD, INB=ENB=0 V
3.4
3.9
4.5
V
INA=ENA=V DD, INB=ENB=0 V
3.2
3.7
4.3
V
18.0
V
0.70
1.20
mA
FAN3224TUMX-F085 (Modified UVLO Version)
V DD
Operating Range
IDD
Supply Current, Inputs / EN Not
(15)
Connected
V ON
Turn-On Voltage
V OFF
9.5
(15)
INA=ENA=V DD, INB=ENB=0 V
8.0
9.1
10.2
V
(15)
INA=ENA=V DD, INB=ENB=0 V
7.0
8.2
9.3
V
0.8
1.2
Turn-Off Voltage
Inputs (FAN322xT)(11)
V INL_T
INx Logic LOW Threshold
V INH_T
INx Logic HIGH Threshold
V HYS_T
1.6
TTL Logic Hysteresis Voltage
0.2
0.4
V
2.0
V
0.8
V
IIN+
Non-Inverting Input Current
IN from 0 to V DD
-1
175
µA
IIN-
Inverting Input Current
IN from 0 to V DD
-175
1
µA
FAN322xTMX-F085, FAN3224TUMX-F085 (Autom otive-Qualified Versions)
V INL_T
INx Logic LOW Threshold
V INH_T
INx Logic HIGH Threshold
0.8
V HYS_T
TTL Logic Hysteresis Voltage
2.0
V
0.4
0.9
V
IN=0 V
-1.5
1.5
µA
(15)
IN=V DD
80
120
175
µA
(15)
IN=0 V
-175
-120
-90
µA
(15)
IN=V DD
-1.5
1.5
µA
Non-inverting Input Current
IINx_T
Non-inverting Input Current
IINx_T
V
1.6
(15)
IINx_T
IINx_T
0.1
1.2
Inverting Input Current
Inverting Input Current
(11)
Inputs (FAN322xC)
V INL_C
INx Logic Low Threshold
V INH_C
INx Logic High Threshold
55
V HYS_C
CMOS Logic Hysteresis Voltage
17
IIN+
Non-Inverting Input Current
30
IN from 0 to V DD
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8
-1
38
%V DD
70
%V DD
%V DD
175
µA
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherw ise noted, V DD=12 V, TJ =-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
IIN-
Parameter
Conditions
Inverting Input Current
IN from 0 to V DD
Min.
Typ.
-175
Max.
Unit
1
µA
FAN322xCMX-F085 (Autom otive-Qualified Versions)
V INL_C
INx Logic Low Threshold
V INH_C
INx Logic High Threshold
55
V HYS_C
CMOS Logic Hysteresis Voltage
17
IINx_T
30
(15)
IN=0 V
(15)
Non-Inverting Input Current
IINx_T
Non-Inverting Input Current
IINx_T
Inverting Input Current
IINx_T
38
-1.5
%V DD
70
%V DD
%V DD
1.5
µA
IN=V DD
90
120
175
µA
(15)
IN=0 V
-175
-120
-90
µA
(15)
IN=V DD
-1.5
1.5
µA
Inverting Input Current
ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)
V ENL
Enable Logic Low Threshold
EN from 5 V to 0 V
V ENH
Enable Logic High Threshold
EN from 0 V to 5 V
V HYS_T
RPU
0.8
1.2
1.6
(12)
V
2.0
V
TTL Logic Hysteresis Voltage
0.4
V
(12)
100
kΩ
Enable Pull-Up Resistance
tD3
EN to Output Propagation Delay
(13)
tD4
0 V to 5 V EN, 1 V/ns Slew
Rate
9
17
26
ns
5 V to 0 V EN, 1 V/ns Slew
Rate
11
18
28
ns
FAN3223C-TMX-F085, FAN3224C-TMX-F085, FAN3224TUMX-F085 (Autom otive-Qualified Versions)
V ENL
Enable Logic Low Threshold
EN from 5 V to 0 V
V ENH
Enable Logic High Threshold
EN from 0 V to 5 V
V HYS_T
RPU
0.8
1.2
1.6
(12)
V
2.0
V
TTL Logic Hysteresis Voltage
0.4
V
(12)
100
kΩ
Enable Pull-Up Resistance
tD3
EN to Output Propagation Delay
(13,15)
tD4
0 V to 5V EN, 1 V/ns Slew
Rate
6
17
34
ns
5 V to 0V EN, 1 V/ns Slew
Rate
6
19
31
ns
Outputs
OUT Current, Mid-Voltage, Sinking
OUT at V DD/2, CLOAD=0.22 µF,
f=1 kHz
4.3
A
ISOURCE
OUT Current, Mid-Voltage,
(12)
Sourcing
OUT at V DD/2, CLOAD=0.22 µF,
f=1 kHz
-2.8
A
IPK_SINK
OUT Current, Peak, Sinking
5
A
ISINK
(12)
(12)
CLOAD=0.22 µF, f=1 kHz
(12)
IPK_SOURCE OUT Current, Peak, Sourcing
CLOAD=0.22 µF, f=1 kHz
-5
CLOAD=2200 pF
12
20
ns
Output Fall Time
CLOAD=2200 pF
9
17
ns
Propagation Matching Betw een
Channels
INA=INB, OUTA and OUTB at
50% Point
2
4
ns
(14)
tRISE
Output Rise Time
tFALL
tDEL.MATCH
(14)
(12)
A
IRVS
Output Reverse Current Withstand
500
tD1, tD2
Output Propagation Delay, CMOS
(14)
Inputs
0 – 12 V IN, 1 V/ns Slew Rate
10
18
29
ns
tD1, tD2
Output Propagation Delay, TTL
(14)
Inputs
0 – 5 V IN, 1 V/ns Slew Rate
9
17
29
ns
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9
mA
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherw ise noted, V DD=12 V, TJ =-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
CLOAD=2200 pF
12
20
ns
Output Fall Time
CLOAD=2200 pF
9
17
ns
Propagation Matching Betw een
Channels
INA=INB, OUTA and OUTB at
50% Point
2
4
ns
All Except for FAN3225C-TMX-F085 (Autom otive-Qualified Versions)
tRISE
tFALL
tDEL.MATCH
(14)
Output Rise Time
(14)
(12)
IRVS
Output Reverse Current Withstand
tD1, tD2
Output Propagation Delay, CMOS
(14,15)
Inputs
0 – 12 V IN, 1 V/ns Slew Rate
9
18
34
ns
tD1, tD2
Output Propagation Delay, TTL
(14,15)
Inputs
0 – 5 V IN, 1 V/ns Slew Rate
6
16
30
ns
V OH
V OL
500
mA
(15)
V OH =V DD–V OUT, IOUT=–1 mA
15
35
mV
(15)
IOUT = 1 mA
10
25
mV
CLOAD=2200 pF
12
28
ns
CLOAD=2200 pF
9
26
ns
(15)
V OH =V DD–V OUT, IOUT=–1 mA
15
37
mV
(15)
IOUT = 1 mA
10
25
mV
High Level Output Voltage
Low Level Output Voltage
FAN3225C_TMX_F085 (Autom otive-Qualificed Versions)
(14)
tRISE
Output Rise Time
tFALL
Output Fall Time
V OH
High Level Output Voltage
V OL
(14)
Low Level Output Voltage
Notes:
10. Low er supply current due to inactive TTL circuitry.
11. EN inputs have TTL thresholds; refer to the ENABLE section.
12. Not tested in production.
13. See Timing Diagrams of Figure 10 and Figure 11.
14. See Timing Diagrams of Figure 8 and Figure 9.
15. Applies only to _F085 versions.
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FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
VINH
Input
VINH
Input
VINL
tD1
VINL
tD2
t RISE
tD1
t FALL
tRISE
tFALL
90%
90%
Output
Output
10%
Figure 8.
10%
Non-Inverting (EN HIGH or Floating)
Figure 9.
HIGH
Inverting (EN HIGH or Floating)
HIGH
Input
Input
LOW
LOW
Enable
tD2
Enable
VENH
VENH
VENL
VENL
tD3
tD4
tD3
tD4
t RISE
t RISE
t FALL
90%
t FALL
90%
Output
Output
10%
10%
Figure 10.
Non-Inverting (IN HIGH)
Figure 11.
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11
Inverting (IN LOW)
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Timing Diagrams
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 12.
IDD (Static) vs. Supply Voltage
Figure 14.
Figure 15.
(16)
Figure 13.
IDD (Static) vs. Supply Voltage
IDD (Static) vs. Supply Voltage
IDD (No-Load) vs. Frequency
Figure 16.
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12
(16)
(16)
IDD (No-Load) vs. Frequency
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 17.
IDD (2.2 nF Load) vs. Frequency
Figure 18.
IDD (2.2 nF Load) vs. Frequency
Figure 19.
IDD (Static) vs. Tem perature
(16)
Figure 20.
IDD (Static) vs. Tem perature
Figure 21.
IDD (Static) vs. Tem perature
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13
(16)
(16)
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 22.
Input Thresholds vs. Supply Voltage
Figure 24.
Figure 25.
Figure 23.
Input Thresholds vs. Supply Voltage
Input Threshold % vs. Supply Voltage
Input Thresholds vs. Tem perature
Figure 26.
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14
Input Thresholds vs. Tem perature
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 27.
UVLO Thresholds vs. Tem perature
Figure 29.
Figure 30.
Figure 28. UVLO Threshold vs. Tem perature
UVLO Thresholds vs. Tem perature
Propagation Delay vs. Supply
Voltage
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15
Figure 31.
Propagation Delay vs. Supply
Voltage
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 32.
Figure 34.
Propagation Delay vs. Supply
Voltage
Propagation Delays vs. Tem perature
Figure 33.
Figure 35.
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16
Propagation Delay vs. Supply
Voltage
Propagation Delays vs. Tem perature
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 36.
Propagation Delays vs. Tem perature
Figure 37.
Propagation Delays vs. Tem perature
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 38.
Fall Tim e vs. Supply Voltage
Figure 40.
Figure 39. Rise Tim e vs. Supply Voltage
Rise and Fall Tim es vs. Tem perature
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17
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 41.
Rise/Fall Waveform s w ith 2.2 nF
Load
Figure 42.
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18
Rise/Fall Waveform s w ith 10 nF
Load
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 43.
Quasi-Static Source Current
(17)
w ith V DD=12 V
Figure 44.
Quasi-Static Sink Current w ith
(17)
V DD=12 V
Figure 45.
Quasi-Static Source Current
(17)
w ith V DD=8 V
Figure 46.
Quasi-Static Sink Current w ith
(17)
V DD=8 V
Notes:
16. For any inverting inputs pulled low , non-inverting inputs pulled high, or outputs driven high, static IDD increases by
the current flow ing through the corresponding pull-up/dow n resistor show n in the block diagram.
17. The initial spike in each current w aveform is a measurement artifact caused by the stray inductance of the
current-measurement loop.
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19
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
VDD
470 µF
Al. El.
4.7 µF
ceramic
Current Probe
LECROY AP015
IOUT
IN
1 kHz
Figure 47.
1 µF
ceramic
VOUT
CLOAD
0.22 µF
Quasi-Static IOUT / V OUT Test Circuit
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20
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Test Circuit
Input Thresholds
MillerDrive™ Gate Drive Technology
Each member of the FA N322x driver family consists of
tw o identical channels that may be used independently
at rated current or connected in parallel to double the
individual current capacity. In the FA N3223 and
FA N3224, channels A and B can be enabled or disabled
independently using ENA or ENB, respectively. The EN
pin has TTL thresholds for parts w ith either CMOS or
TTL input thresholds. If ENA and ENB are not
connected, an internal pull-up resistor enables the dr iver
channels by default. ENA and ENB have TTL thresholds
in parts w ith either TTL or CMOS INx threshold. If the
channel A and channel B inputs and outputs are
connected in parallel to increase the driver current
capacity, ENA and ENB should be connected and
driven together.
FA N322x gate drivers incorporate the Miller Drive™
architecture show n in Figure 48. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a w ide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT sw ings betw een 1/3 to 2/3
V DD and the MOS dev ices pull the output to the HIGH or
LOW rail.
The FA N322x family offers versions in either TTL or
CMOS input thresholds. In the FA N322x T, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the V DD voltage, and there is a
hysteresis voltage of approximately 0.4 V. These levels
per mit the inputs to be driven from a range of input logic
signal levels for w hich a voltage over 2 V is considered
logic HIGH. The driving signal for the TTL inputs should
have fast rising and falling edges w ith a slew rate of
6 V/µs or faster, so a r ise time from 0 to 3.3 V should be
550 ns or less. With reduced slew rate, circuit noise
could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the dr iver input, causing
erratic operation.
In the FA N322x C, the logic input thresholds are
dependent on the V DD level and, w ith V DD of 12V, the
logic rising edge threshold is approximately 55% of V DD
and the input falling edge threshold is approximately
38% of V DD. The CMOS input configuration offers a
hysteresis voltage of approximately 17% of V DD. The
CMOS inputs can be used w ith relatively s low edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
w indow . This allow s setting precise timing intervals by
fitting an R- C c ircuit betw een the controlling signal and
the IN pin of the dr iver. The s low rising edge at the IN
pin of the driver introduces a delay betw een the
controlling signal and the OUT pin of the driver.
Static Supply Current
In the IDD (static) typical performance characteristics
(Figure 12 - Figure 14 and Figure 19 - Figure 21), the
curve is produced w ith all inputs/enables floating (OUT
is low ) and indicates the low est static IDD current for the
tested configuration. For other states, additional current
flow s through the 100 kΩ resistors on the inputs and
outputs show n in the block diagram of each part (see
Figure 5 - Figure 7). In these cases, the actual static IDD
current is the value obtained from the curves plus this
additional current.
The purpose of the Miller Drive™ architecture is to
speed up sw itching by providing high current during the
Miller plateau region w hen the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications that have zero voltage sw itching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast sw itching even
though the Miller plateau is not present. This situation
often occurs in synchronous rectif ier applications
because the body diode is generally conducting before
the MOSFET is sw itched ON.
The output pin slew rate is determined by V DD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slow er rise or fall time
at the MOSFET gate is needed.
VDD
Input
stage
Figure 48.
VOUT
MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN322x startup logic is optimized to drive groundreferenced N-channel MOSFETs w ith an under-voltage
lockout ( UVLO) function to ensure that the IC starts up
in an orderly fashion. When V DD is rising, yet below the
UVLO level, this circuit holds the output LOW,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.2 V before the
part shuts dow n. This hysteresis helps prevent chatter
when low V DD supply voltages have noise from the
pow er sw itching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver w ould turn the P-channel
MOSFET ON w ith V DD below the UVLO level.
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21
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Applications Information
To enable this IC to turn a dev ice ON quic kly, a loc al
high-frequency bypass capacitor, CBYP , w ith low ESR
and ESL should be connected betw een the V DD and
GND pins w ith minimal trace length. This c apac itor is
in addition to the bulk electrolytic capacitanc e of 10 µF
to 47 µF c ommonly found on the driv er and contr oller
bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the r ipple voltage on the V DD supply to ≤5%. This
is often achieved w ith a value ≥20 times the equivalent
load capacitance CEQV, defined here as QGATE/V DD.
Ceramic capacitors of 0.1 µF to 1 µF or larger are
common choices, as are dielectrics, such as X5R and
X7R w ith good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into tw o capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a s maller value, such as 1-10 nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
sw itching simultaneously, the combined peak current
sourced from the CBYP w ould be tw ice as large as w hen
a single channel is sw itching.
The FAN322x is compatible w ith many other
industry-standard drivers. In single input parts w ith
enable pins, there is an internal 100 kΩ res istor tied
to VDD to enable the driver by default; this should
be considered in the PCB layout.
The turn-on and turn-off current paths should be
minimized, as discussed in the follow ing section.
Figure 49 show s the pulsed gate drive current path
when the gate dr iver is supplying gate charge to turn the
MOSFET ON. The current is supplied from the local
bypass capacitor, CBYP, and flow s through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized CBYP acts
to contain the high peak current pulses w ithin this driverMOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
VDD
CBYP
FAN322x
Layout and Connection Guidelines
The FA N3223-25 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays,
and pow erful output stages capable of delivering current
peaks over 4 A to facilitate voltage transition times from
under 10 ns to over 150 ns. The follow ing layout and
connection guidelines are strongly recommended:
Keep high-current output and pow er ground paths
separate logic and enable input signals and signal
ground paths. This is espec ially critical w hen
dealing w ith TTL-level logic thresholds at driver
inputs and enable pins.
VDS
PWM
Figure 49.
Current Path for MOSFET Turn-On
Figure 50 show s the current path w hen the gate dr iver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a s mall
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the ser ies inductance to improve highspeed sw itching, w hile reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
If the inputs to a channel are not externally
connected, the internal 100 kΩ resistors indicated
on bloc k diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to V DD or GND using short
traces to prevent noise from causing spur ious
output sw itching.
Many high-speed pow er circuits can be susceptible
to noise injected from their ow n output or other
external sources, possibly caus ing output retriggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts w ith long input, enable, or output leads.
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22
VDD
VDS
CBYP
FAN322x
PWM
Figure 50.
Current Path for MOSFET Turn-Off
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
For best results, make connections to all pins as
short and direct as possible.
VDD Bypass Capacitor Guidelines
Operational Waveforms
The FAN3225 truth table indicates the operational states
using the dual-input configuration. In a non-inverting
driver configuration, the IN- pin should be a logic LOW
signal. If the IN- pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN+ pin.
At pow er-up, the driver output remains LOW until the
V DD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises w ith V DD until
steady-state V DD is reached. The non-inverting
operation illustrated in Figure 53 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase w ith the input.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
VDD
In the non- inverting dr iver configuration in Figure 51, the
IN- pin is tied to ground and the input signal ( PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
HIGH to disable the dr iver and the output remains LOW,
regardless of the state of the IN+ pin.
Turn-on threshold
IN-
IN+
VDD
PWM
IN+
IN-
FAN3225
OUT
OUT
GND
Figure 53.
Figure 51. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application in Figure 52, the IN+
pin is tied HIGH. Pulling the IN+ pin to GND forces the
output LOW, regardless of the state of the IN- pin.
For the inverting configuration of Figure 52, startup
waveforms are show n in Figure 54. With IN+ tied to
VDD and the input signal applied to IN–, the OUT
pulses are inverted w ith respect to the input. At pow erup, the inverted output remains LOW until the V DD
voltage reaches the turn-on threshold, then it follows the
input w ith inverted phase.
VDD
VDD
Non-Inverting Startup Waveform s
Turn-on threshold
IN+
PWM
IN-
FAN3225
OUT
GND
IN-
IN+
(VDD)
Figure 52. Dual-Input Driver Enabled,
Inverting Configuration
OUT
Figure 54.
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23
Inverting Startup Waveform s
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Truth Table of Logic Operation
Gate dr ivers used to sw itch MOSFETs and IGBTs at
high frequencies can dissipate s ignificant amounts of
pow er. It is important to deter mine the driver pow er
dissipation and the resulting junction temperature in the
application to ensure that the part is operating w ithin
acceptable temperature limits.
The total pow er dissipation in a gate dr iver is the sum of
tw o components, PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC
(1)
PGATE ( Gate Driving Loss): The most significant pow er
loss results from supplying gate current (charge per
unit time) to sw itch the load MOSFET on and off at
the sw itching frequency. The pow er dissipation that
results from dr iving a MOSFET at a specified gatesource voltage, V GS, w ith gate charge, QG, at
sw itching frequency, f SW, is determined by:
PGATE = QG • V GS • f SW • n
(2)
w here n is the number of driver channels in use (1 or 2).
PDYNAMIC (Dynamic Pre- Drive / Shoot-through
Current): A pow er loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-dow n resistors. The internal
current consumption ( IDYNAMIC) can be estimated using
the graphs in Figure 15 and Figure 16 of the Typical
Performance Character istics to deter mine the current
IDYNAMIC draw n from V DD under actual operating
conditions:
PDYNAMIC = IDYNAMIC • V DD • n
To give a numerical example, assume for a 12 V V DD
(V BIAS) system, the synchronous rectifier sw itches of
Figure 55 have a total gate charge of 60 nC at
V GS = 7 V. Therefore, tw o devices in parallel w ould have
120 nC gate charge. At a sw itching frequency of
300 kHz, the total pow er dissipation is:
PGATE = 120 nC • 7 V • 300 kHz • 2 = 0.504 W
(5)
PDYNAMIC = 3.0 mA • 12 V • 1 = 0.036 W
(6)
PTOTAL = 0.540 W
(7)
The SOIC-8 has a junction-to-board ther mal
characterization parameter of ψJB = 42°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along w ith airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; w ith 80%
derating, TJ w ould be limited to 120°C. Rearranging
Equation 4 deter mines the board temperature required
to maintain the junction temperature below 120°C:
TB,MAX = TJ - PTOTAL • ψ JB
(8)
TB,MAX = 120°C – 0.54 W • 42°C/W = 97°C
(9)
(3)
where n is the number of driver ICs in use. Note that n is
usually be one IC even if the IC has tw o channels,
unless tw o or more.driver ICs are in parallel to driv e a
large load.
Once the pow er dissipated in the driver is deter mined,
the driver junction rise w ith respect to circuit board can
be evaluated using the follow ing ther mal equation,
assuming ψ JB w as determined for a similar ther mal
design (heat sinking and air flow ):
TJ = PTOTAL • ψ JB + TB
(4)
w here:
TJ
= driver junction temperature;
ψ JB
= (psi) thermal characterization parameter
relating temperature rise to total pow er
dissipation; and
TB
= board temperature in location as defined in
the Thermal Characteristics table.
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24
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Thermal Guidelines
VIN
VOUT
PWM
1
8
2
7
3
6
4
5
FAN3224
ENB 8
1 ENA
Timing/
Isolation
Vbias
3 GND
4
FAN3224
Figure 55. High Current Forw ard Converter
w ith Synchronous Rectification
Vin
A
2
Figure 56.
QC
QA
QD
QB
7
VDD 6
B
5
Center-Tapped Bridge Output w ith
Synchronous Rectifiers
FAN3224
PWM-A
FAN3225
SR-1
PWM-B
Secondary
Phase Shift
Controller
SR-2
PWM-C
FAN3225
PWM-D
Figure 57.
Secondary Controlled Full Bridge w ith Current Doubler Output, Synchronous
Rectifiers (Sim plified)
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25
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Application Diagrams
Type
Related Products
Part
Number
Gate
Input
Drive (18)
Threshold
(Sink/Src)
Single 1 A FAN3111C +1.1 A / -0.9 A
Single 1 A FAN3111E
CMOS
(19)
Logic
Single Channel of Dual-Input/Single-Output
Package
SOT23-5, MLP6
+1.1 A / -0.9 A
External
Single Non-Inverting Channel with External Reference SOT23-5, MLP6
Single 2 A FAN3100C +2.5 A / -1.8 A
CMOS
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
SOT23-5, MLP6
Single 2 A FAN3100T
+2.5 A / -1.8 A
TTL
Single Channel of Two-Input/One-Output
Single 2 A
FAN3180
+2.4 A / -1.6 A
TTL
Single Non-Inverting Channel + 3.3-V LDO
Dual 2 A
FAN3216T
+2.4 A / -1.6 A
TTL
Dual Inverting Channels
SOIC8
Dual 2 A
FAN3217T
+2.4 A / -1.6 A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 2 A
FAN3226C +2.4 A / -1.6 A
Dual 2 A
FAN3226T
Dual 2 A
FAN3227C +2.4 A / -1.6 A
Dual 2 A
FAN3227T
Dual 2 A
FAN3228C +2.4 A / -1.6 A
Dual 2 A
FAN3228T
Dual 2 A
FAN3229C +2.4 A / -1.6 A
Dual 2 A
FAN3229T
Dual 2 A
SOT23-5
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
+2.4 A / -1.6 A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3268T
+2.4 A / -1.6 A
TTL
20 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 2 A
FAN3278T
+2.4 A / -1.6 A
TTL
30 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 4 A
FAN3213T
+4.3 A / -2.8 A
TTL
Dual Inverting Channels
SOIC8
Dual 4 A
FAN3214T
+4.3 A / -2.8 A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 4 A
FAN3223C +4.3 A / -2.8 A
CMOS
Dual Inv erting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3223T +4.3 A / -2.8 A
TTL
Dual Inv erting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3224C +4.3 A / -2.8 A
CMOS
Dual Non-Inv erting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3224T +4.3 A / -2.8 A
TTL
Dual Non-Inv erting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3225C +4.3 A / -2.8 A
CMOS
Dual Channels of Tw o-Input/One-Output
SOIC8, MLP8
Dual 4 A
FAN3225T +4.3 A / -2.8 A
TTL
Dual Channels of Tw o-Input/One-Output
SOIC8, MLP8
CMOS
Single Inverting Channel + Enable
SOIC8, MLP8
Single Inverting Channel + Enable
SOIC8, MLP8
+2.4 A / -1.6 A
+2.4 A / -1.6 A
+2.4 A / -1.6 A
Single 9 A FAN3121C +9.7 A / -7.1 A
Single 9 A FAN3121T
+9.7 A / -7.1 A
TTL
Single 9 A FAN3122T
+9.7 A / -7.1 A
CMOS
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Single 9 A FAN3122C +9.7 A / -7.1 A
TTL
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Dual 12 A
FAN3240
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 0
SOIC8
Dual 12 A
FAN3241
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 1
SOIC8
Notes:
18. Typical currents w ith OUTx at 6 V and V DD=12 V.
19. Thresholds proportional to an externally supplied reference voltage.
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26
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Table 1.
3.00
0.10 C
A
B
2X
8
2.37
5
1.99
1.42
3.00
3.30
(0.65)
PIN #1 IDENT
0.10 C
TOP VIEW
2X
1
0.65 TYP
4
0.42 TYP
RECOMMENDED LAND PATTERN
0.10 C
0.80 MAX
(0.20)
0.08 C
0.05
0.00
FRONT VIEW C
NOTES:
SEATING
PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION VEEC, DATED 11/2001.
1
2.25MAX
0.45
0.20
4
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
PIN #1 IDENT
1.30MAX
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP08Drev3
5 0.25
0.35
8
0.65
0.10
0.05
1.95
C A B
C
BOTTOM VIEW
Figure 58.
3x3 m m , 8-Lead Molded Leadless Package (MLP)
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27
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Physical Dimensions
(Continued)
4.90±0.10
0.65
A
(0.635)
5
8
B
1.75
6.00±0.20
PIN ONE
INDICATOR
5.60
3.90±0.10
1
4
1.27
1.27
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.175±0.075
0.22±0.03
C
1.75 MAX
0.10
0.42±0.09
OPTION A - BEVEL EDGE
(0.86) x 45°
R0.10
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES:
8°
0°
SEATING PLANE
0.65±0.25
(1.04)
DETAIL A
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M
E) DRAWING FILENAME: M08Arev16
SCALE: 2:1
Figure 59. 8-Lead Sm all Outline Integrated Circuit (SOIC)
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FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
Physical Dimensions
FAN3223 / FAN3224 / FAN3225 — Dual 4-A High-Speed, Low-Side Gate Drivers
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