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FAN4800AU / FAN4800CU
PFC/ PWM Controller Combination
Features
Pin-to-Pin Compatible with ML4800, FAN4800,
CM6800, and CM6800A
PWM Configurable for Current-Mode or
Feed-Forward Voltage-Mode Operation
Internally Synchronized Leading-Edge PFC and
Trailing-Edge PWM in One IC
Low Operating Current
Innovative Switching-Charge Multiplier Divider
Description
The highly integrated FAN4800AU/CU parts are
specially designed for power supplies that consist of
boost PFC and PWM. They require very few external
components to achieve versatile protections and
compensation. They are available in 16-pin DIP and
SOP packages.
The PWM can be used in current or Voltage Mode. In
Voltage Mode, feed-forward from the PFC output bus
can reduce secondary output ripple.
PFC Feedback Open-Loop Protection
To evaluate FAN4800AU/CU for replacing existing
FAN4800A/C, FAN4800AS/CS, old version FAN4800
and ML4800 boards, six things must be completed
before the fine-tuning procedure:
Cycle-by-Cycle Current Limiting for PFC/PWM
1.
Change RAC resistor from the old value to a higher
resistor value: 6 M to 8 M.
2.
Change RT/CT pin from the existing values to
RT=6.8 k and CT=1000 pF to have fPFC=64 kHz
and fPWM=64 kHz.
3.
The VRMS pin needs to be 1.224 V at VIN=85 VAC
for universal input application with line input from
85 VAC to 270 VAC.
4.
Change ISENSE pin filter from the exiting values to
RFilter=51 and CFilter=0.01 µF for higher bandwidth.
5.
At full load, the average VVEA must be ~4.5 V and
ripple on VVEA needs to be less than 400 mV.
6.
For the SS pin, the soft-start current has been
reduced to half the FAN4800 capacitor.
Average-Current-Mode for Input-Current Shaping
PFC Over-Voltage and Under-Voltage Protections
Power-on Sequence Control and Soft-Start
Line Sagging Protection
fRTCT=4•fPFC=4•fPWM for FAN4800AU
fRTCT=4•fPFC=2•fPWM for FAN4800CU
Applications
Desktop PC Power Supply
Internet Server Power Supply
LCD TV/ Monitor Power Supply
UPS
Battery Charger
DC Motor Power Supply
Monitor Power Supply
Telecom System Power Supply
Distributed Power
There are two differences from FAN4800AS/CS to
FAN4800AU/CU:
Add Line Sagging Protection
Fix Inductance Current Instability during AC Cycle
Drop Test
Related Resources
AN-8027 — FAN480X PFC+PWM Combination
Controller Application
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
FAN4800AU/CU — PFC/ PWM Controller Combination
September 2015
PFC:PWM
Frequency
Ratio
Operating
Temperature Range
Part Number
FAN4800AUN
1:1
FAN4800CUN
1:2
-40°C to +105°C
FAN4800AUM
16-Pin Dual Inline Package (DIP)
1:1
FAN4800CUM
Packing
Method
Package
Tube
16-Pin Small Outline Package (SOP)
1:2
Tape & Reel
Block Diagram
VDD
13
VDD OVP
1.9V
AC UVLO
BI
27V/28V
VDD
Q S
PFC OVP
BOP
VIN OFF
Q R
Debounce 30ms
2
VRMS
4
PFC ILIMIT
-1.3V
ISENSE
GMi
GMv
FBPFC 15
10µA
3
IEA
1
RT/CT
7
S
PFC SAW
10 GND
VDD
Dead-Time
300µA
VIN UVLO
PFC SAW
PWM Max. Duty
2.4V
BI
S
VIN OFF
1.3V
PWM Max. Duty
8
VDD
PWM Max. Duty
S
10V Level Shift 1.5V
10µA
5
VIN OK
Q
R Q
6
300Ω
SS
12 OPFC
Q
33µA
FBPFC
RAMP
VDD
1mA
Dead-Time
FBPWM
Q
R Q
R Q
5.7KΩ
VEA 16
ISENSE
S
ZERO POWER
0.3V
VEA
BOP
14 VREF
PFC UVP
k
x2
2.5V
7.5V
REFERENCE
0.5V
VRMS
1.05V
Debounce 1ms
IAC
FBPFC
0.85V
Gain Modulator
UVLO
11V/9V
VRMS 2.5V/2.75V
1V
Q
11 OPWM
R Q
Blanking
300Ω
PWM ILIMIT
VIN OFF
9
UVLO
ILIMIT
Figure 1. Function Block Diagram
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
FAN4800AU/CU — PFC/ PWM Controller Combination
Ordering Information
FAN4800AU/CU — PFC/ PWM Controller Combination
Application Diagrams
LBoost
DBoost
AC
CVIN
1MΩ
3MΩ
1MΩ
3MΩ
10Ω
Q1
CBulk
RFBPFC1
10KΩ
RFBPFC2
IAC OPFC
200KΩ
47nF
220nF
VRMS
FBPFC
36KΩ
CFBPFC
ISENSE
RSENSE
RFBPFC3
VEA
RFilter
CFilter
CVEA1
CVEA2
10Ω
RVEA
IEA
GND
CIEA1
Q2
DF1
10KΩ
CIEA2
12V
RIEA
CVDD
VREF
VDD
DF2
VDD
Lm
5V
RFBPWM
FBPWM
FBPWM
RT
OPWM
RT/CT
CT
Q3
10Ω
SS
10KΩ
CSS
RAMP
12V
FBPWM
RFilter
RD
ILIMIT
RILIMIT
CFilter
1nF
RFB1
RRAMP
CFB RFB4
RFB2
5V
CRAMP
RFB3
Figure 2.
Current Mode
LBoost
DBoost
AC
CVin
1MΩ
3MΩ
1MΩ
3MΩ
10Ω
Q1
CBulk
RFBPFC1
10KΩ
RFBPFC2
IAC OPFC
200KΩ
47nF
220nF
VRMS
FBPFC
36KΩ
CFBPFC
ISENSE
RFilter
RSENSE
RFBPFC3
VEA
CFilter
CVEA1
CVEA2
RVEA
IEA
CIEA1
10Ω
GND
Q2
DF1
10KΩ
CIEA2
12V
RIEA
CVDD
VREF
VDD
DF2
VDD
Lm
5V
RFBPWM
RRAMP
RT
FBPWM
FBPWM
OPWM
RT/CT
CRAMP
10KΩ
CT
12V
FBPWM
RFilter
SS
CSS
Q3
10Ω
RAMP
RD
ILIMIT
CFilter
RILIMIT
1nF
RFB1
CFB RFB4
RFB2
5V
RFB3
Figure 3.
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
Voltage Mode
www.fairchildsemi.com
3
16
16
ZXYYTT
ZXYYTT
FAN4800C
UTM
1
FAN4800A
UTM
1
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
YY – 2-Digit Week Code
TT – 2-Digit Die-Run Code
T – Package Type (N:DIP)
M – Manufacture Flow Code
Figure 4. DIP Top Mark
16
16
ZXYTT
ZXYTT
FAN4800A
UTM
1
FAN4800C
UTM
1
Figure 5. SOP Top Mark
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die-Run Code
T – Package Type (M:SOP)
M – Manufacture Flow Code
FAN4800AU/CU — PFC/ PWM Controller Combination
Marking Information
www.fairchildsemi.com
4
1
IEA
VEA 16
2
IAC
3
ISENSE
4
VRMS
5
SS
6
FBPWM
7
RT/CT
GND
10
8
RAMP
ILIMIT
9
FBPFC
15
VREF
14
VDD
13
OPFC 12
OPWM 11
Figure 6. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
IEA
Output of PFC Current Amplifier. The signal from this pin is compared with an internal
sawtooth to determine the pulse width for the PFC gate drive.
2
IAC
Input AC Current. For normal operation, this input provides a current reference for the
multiplier. The suggested maximum IAC is 65 µA.
3
ISENSE
PFC Current Sense. The inverting input of the PFC current amplifier and the output of
multiplier and PFC ILIMIT comparator.
4
VRMS
5
SS
6
FBPWM
7
RT/CT
Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.
8
RAMP
PWM RAMP Input. In Current Mode, this pin functions as the current-sense input. In Voltage
Mode, it is the feed-forward sense input from PFC output 380 V (feed-forward ramp).
Peak Current Limit Setting for PWM. The peak current limit setting for PWM.
FAN4800AU/CU — PFC/ PWM Controller Combination
Pin Configuration
Line-Voltage Detection. The pin is used for the PFC multiplier.
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10 µA
constant current source. The voltage on FBPWM is clamped by SS during startup. If a
protection condition occurs and/or PWM is disabled, the SS pin is quickly discharged.
PWM Feedback Input. The control input for voltage-loop feedback of PWM stage.
9
ILIMIT
10
GND
11
OPWM
PWM Gate Drive. The totem-pole output drive for the PWM MOSFET. This pin is internally
clamped under 19 V to protect the MOSFET.
12
OPFC
PFC Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped
under 15 V to protect the MOSFET.
13
VDD
Supply. The power supply pin. The threshold voltages for startup and turn-off are 11 V and
9.3 V, respectively. The operating current is lower than 10 mA.
14
VREF
Reference Voltage. Buffered output for the internal 7.5 V reference.
15
FBPFC
16
VEA
Ground
Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input
of PFC error amplifier. This pin is connected to the PFC output through a divider network.
Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop.
A compensation network is connected between this pin and ground.
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VDD
DC Supply Voltage
VH
Voltage on SS, FBPWM, RAMP, VREF Pins
Min.
-0.3
Max.
Unit
30
V
30.0
V
V
VPFC-OUT
Voltage on OPFC Pin
VDD
+0.3V
VPWM-OUT
Voltage on OPWM Pin
VDD
+0.3V
V
-0.3
7.0
V
0
VVREF+0.3
V
-5.0
0.7
V
VL
Voltage on IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA Pins
VIEA
Voltage on IEA Pin
VN
Voltage on ISENSE Pin
IAC
Input AC Current
1
mA
IREF
VREF Output Current
5
mA
IPFC-OUT
Peak PFC OUT Current, Source or Sink
0.5
A
IPWM-OUT
Peak PWM OUT Current, Source or Sink
0.5
A
PD
Power Dissipation TA < 50°C
800
mW
ΘJA
Thermal Resistance (Junction to Air)
ΘJC
Thermal Resistance (Junction to Case)
TJ
DIP
80.80
SOP
104.10
DIP
35.38
SOP
40.41
°C/W
°C/W
Operating Junction Temperature
-40
+125
°C
TSTG
Storage Temperature Range
-55
+150
°C
TL
Lead Temperature(Soldering)
+260
°C
ESD
Electrostatic Discharge Capability
Human Body Model,
JESD22-A114
6.0
Charged Device Model,
JESD22-C101
2.0
FAN4800AU/CU — PFC/ PWM Controller Combination
Absolute Maximum Ratings
kV
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
Min.
Max.
Unit
-40
+105
°C
www.fairchildsemi.com
6
Unless otherwise noted, VDD=15 V, TA= 25°C, TA=TJ, RT=6.8 kΩ, and CT=1000 pF.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
30
80
µA
2.0
2.6
5.0
mA
11
12
V
1.9
V
29
V
VDD Section
IDD-ST
Startup Current
VDD=VTH-ON-0.1V, OPFC OPWM
Open
IDD-OP
Operating Current
VDD=13 V, OPFC OPWM Open
VTH-ON
Turn-on Threshold Voltage
10
△VTH
Hysteresis
1.3
VDD OVP
27
VDD-OVP
△VDD-OVP
VDD OVP Hysteresis
28
1
V
Oscillator
fOSC-RT/CT
RT/CT Frequency
RT=6.8 kΩ, CT=1000 pF
PFC & PWM Frequency
fOSC
FAN4800CU PWM Frequency
fDV
fDT
Voltage Stability
(3)
Temperature Stability
(3)
(3)
240
256
268
60
64
67
120
128
134
kHz
kHz
11 V ≦ VDD ≦ 22 V
2
%
-40°C ~ +105°C
2
%
70
kHz
fTV
Total Variation (PFC & PWM)
Line, Temperature
fRV
Ramp Voltage
Valley to Peak
IOSC-DIS
Discharge Current
VRAMP=0 V, VRT/CT=2.5 V
fRANGE
Frequency Range
58
2.8
V
6.5
15.0
mA
50
75
kHz
PFC Dead Time
RT=6.8 kΩ, CT=1000 pF
400
600
800
ns
Reference Voltage
IVREF=0 mA, CVREF=0.1 µF
7.4
7.5
7.6
V
△VVREF1
Load Regulation of Reference
Voltage
CVREF=0.1 µF, IVREF=0 mA to
3.5 mA VDD=14 V, Rise/Fall Time
> 20 µs
30
50
mV
△VVREF2
Line Regulation of Reference
Voltage
CVREF=0.1 µF, VDD=11V to 22 V
25
mV
0.5
%
7.35
7.65
V
TJ=125°C, 0 ~ 1000 Hours
5
25
mV
VVREF > 7.35 V
5
tPFC-DEAD
FAN4800AU/CU — PFC/ PWM Controller Combination
Electrical Characteristics
VVREF
VVREF
△VVREF-DT
△VVREF-TV
Temperature Stability
(3)
(3)
Total Variation
△VVREF-LS
Long-Term Stability
IVREF-MAX.
Maximum Current
-40°C ~ +105°C
Line, Load, Temperature
(3)
0.4
mA
PFC OVP Comparator
VPFC-OVP
△VPFC-OVP
Over-Voltage Protection
2.70
2.75
2.80
V
PFC OVP Hysteresis
200
250
300
mV
0.2
0.3
0.4
V
Voltage Level on FBPFC to
Enable OPWM During Startup
2.3
2.4
2.5
V
Hysteresis
1.0
1.1
1.2
V
Low-Power Detect Comparator
VVEAOFF
VEA Voltage OFF OPFC
VIN OK Comparator
VRD-FBPFC
△VRD-FBPFC
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
7
Unless otherwise noted, VDD=15 V, TA= 25°C, TA=TJ, RT=6.8 kΩ, and CT=1000 pF.
Symbol
Parameter
Condition
Min.
Typ.
Max.
2.45
2.50
2.55
35
42
Unit
Voltage Error Amplifier
VREF
AV
Gmv
Reference Voltage
(3)
Open-Loop Gain
Transconductance
VNONINV=VINV, VVEA=3.75 V
50
70
IFBPFC-L
Maximum Source Current
VFBPFC=2 V, VVEA=1.5 V
40
50
IFBPFC-H
Maximum Sink Current
VFBPFC=3 V, VVEA=6 V
IBS
-50
Input Bias Current
-1
VVEA-H
Output High Voltage on VVEA
5.8
VVEA-L
Output Low Voltage on VVEA
V
dB
90
µmho
µA
-40
µA
1
µA
6.0
V
0.1
0.4
V
88
105
µmho
10
mV
7.4
7.8
V
0.1
0.4
V
Current Error Amplifier
GmI
Transconductance
VNONINV=VINV, VIEA=3.75 V
70
VOFFSET
Input Offset Voltage
VVEA=0 V, IAC Open
-10
VIEA-H
Output High Voltage
VIEA-L
Output Low Voltage
IL
Source Current
IH
Sink Current
AI
Open-Loop Gain
6.8
VISENSE= -0.6 V, VIEA=1.5 V
35
VISENSE= +0.6 V, VIEA=4.0 V
(3)
50
-50
40
µA
-35
50
FAN4800AU/CU — PFC/ PWM Controller Combination
Electrical Characteristics (Continued)
µA
dB
TriFault Detect™
tFBPFC-OPEN
VPFC-UVP
Time to FBPFC Open
VFBPFC=VPFC-UVP to FBPFC OPEN,
470 pF from FBPFC to GND
PFC Feedback Under-Voltage
Protection
0.4
2
4
ms
0.5
0.6
V
65
µA
2
kHz
Gain Modulator
IAC
GAIN
BW
VO(gm)
Input for AC Current
(3)
(4)
Gain Modulator
Bandwidth
(3)
Output Voltage=5.7 kΩ ×
(ISENSE-IOFFSET)
Multiplier Linear Range
0
IAC=17.67 µA, VRMS=1.080 V
VFBPFC=2.25 V
7.94
IAC=20 µA, VRMS=1.224 V
VFBPFC=2.25 V
7.02
IAC=25.69 µA, VRMS=1.585 V
VFBPFC=2.25 V
4.18
IAC=51.62 µA, VRMS=3.169 V
VFBPFC=2.25 V
1.05
IAC=62.23 µA, VRMS=3.803 V
VFBPFC=2.25 V
0.73
IAC=40 µA
IAC=50 µA, VRMS=1.224 V
VFBPFC=2.25 V
0.76
0.80
0.84
V
-1.2
-1.3
-1.4
V
PFC ILIMIT Comparator
VPFC-ILIMIT
△VPK
Peak Current Limit Threshold
Voltage, Cycle-by-Cycle Limit
PFC ILIMIT-Gain Modulator
Output
IAC=17.67 µA, VRMS=1.08 V
VFBPFC=2.25 V
400
mV
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
8
Unless otherwise noted, VDD=15 V, TA= 25°C, TA=TJ, RT=6.8 kΩ, and CT=1000 pF.
Symbol
Parameter
Condition
Min.
Typ.
13
15
Max.
Unit
17
V
1.5
V
PFC Output Driver
VGATE-CLAMP
Gate Output Clamping Voltage
VDD=22 V
VGATE-L
Gate Low Voltage
VDD=15 V, IO=100 mA
VGATE-H
Gate High Voltage
VDD=13 V, IO=100 mA
8
tR
Gate Rising Time
VDD=15 V, CL=4.7 nF,
O/P= 2 V to 9 V
40
70
120
ns
tF
Gate Falling Time
VDD=15 V, CL=4.7 nF,
O/P=9 V to 2 V
40
60
110
ns
DPFC-MAX
Maximum Duty Cycle
VIEA4.5 V
V
%
0
%
PWM ILIMIT Comparator
VPWM-ILIMIT
Threshold Voltage
tPD
Propagation Delay to Output
tPWM-BNK
Leading-Edge Blanking Time
0.95
1.00
1.05
250
V
ns
170
250
350
ns
18
19
20
V
1.5
V
PWM Output Driver
VGATE-CLAMP
Gate Output Clamping Voltage
VDD=22 V
VGATE-L
Gate Low Voltage
VDD=15 V, IO=100 mA
VGATE-H
Gate High Voltage
VDD=13 V, IO=100 mA
8
tR
Gate Rising Time
VDD=15 V, CL=4.7 nF,
O/P=2 V to 9 V
30
60
120
ns
tF
Gate Falling Time
VDD=15 V, CL=4.7 nF,
O/P=9 V to 2 V
30
50
110
ns
Maximum Duty Cycle
49.0
49.5
50.0
%
PWM Comparator Level Shift
1.3
1.5
1.8
V
9.5
10.0
10.5
V
DPWM-MAX
VPWM-LS
FAN4800AU/CU — PFC/ PWM Controller Combination
Electrical Characteristics (Continued)
V
Soft-Start
VSS-MAX
Maximum Voltage
ISS
Soft-Start Current
VDD=15 V
10
µA
Brownout
VRMS-UVL
VRMS Threshold LOW
1.00
1.05
1.10
V
VRMS-UVH
VRMS Threshold HIGH
1.85
1.90
1.95
V
Hysteresis
750
850
950
mV
Under- Voltage Protection Delay
750
1000
1250
ms
0.80
0.85
0.90
V
28
33
38
ms
△VRMS-UVP
tUVP
Sagging Protection
VRMS-SAG
tSAG
VRMS Threshold SAG LOW
SAG Protection Delay
Notes:
3. This parameter, although guaranteed by design, is not 100% production tested.
4. This gain is the maximum gain of modulation with a given VRMS voltage when VVEA is saturated to HIGH.
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
9
Figure 7.
IDD-ST vs. Temperature
Figure 9.
fOSC vs. Temperature
Figure 10.
VVREF vs. Temperature
VPFC-OVP vs. Temperature
Figure 12.
VREF vs. Temperature
Figure 11.
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
Figure 8.
VDD-OVP vs. Temperature
FAN4800AU/CU — PFC/ PWM Controller Combination
Typical Characteristics
www.fairchildsemi.com
10
Figure 13.
GmV vs. Temperature
Figure 14.
GmI vs. Temperature
Figure 15.
VPFC-ILIMIT vs. Temperature
Figure 16.
VPWM-ILIMIT vs. Temperature
Figure 17.
VRMS-UVP vs. Temperature
Figure 18.
ΔVRMS-UVP vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
FAN4800AU/CU — PFC/ PWM Controller Combination
Typical Characteristics
www.fairchildsemi.com
11
Figure 19.
VGATE-CLAMP-PFC vs. Temperature
Figure 21.
Figure 20.
DPFC-MAX vs. Temperature
Figure 23.
ISS vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
VGATE-CLAMP-PWM vs. Temperature
Figure 22.
DPWM-MAX vs. Temperature
Figure 24.
VRMS-SAG vs. Temperature
FAN4800AU/CU — PFC/ PWM Controller Combination
Typical Characteristics
www.fairchildsemi.com
12
Oscillator
The internal oscillator frequency is determined by the
timing resistor and capacitor on the RT/CT pins as
shown in Figure 25. The frequency of the internal
oscillator is given:
f OSC
(1)
Because the PWM stage generally uses a forward
converter, it is necessary to limit the maximum duty
cycle at 50%. To have a small tolerance of the
maximum duty cycle, a frequency divider with toggle
flip-flops is used, as illustrated in Figure 25. The
operation frequency of PFC and PWM stage is 1/4 of
oscillator frequency. (For FAN4800CU, the operation
frequencies for PFC and PWM stages are 1/4 and 1/2
of oscillator frequency, respectively).
The dead time for the PFC gate drive signal is
determined by:
t DEAD 360CT
(2)
The dead time should be smaller than 2% of the
switching period to minimize line current distortion
around the line zero crossing.
RT/CT
T-FF
T-FF
T Q
T
Q
OPFC, OPWM
OSC
VG.PFC
VG.PWM
1
0.56 RT CT 360CT
VREF
IDS
ID
OPWM (FAN4800CU)
Figure 25. Oscillator Configuration
RT/CT
VG.PFC
VG.PWM
ID
IDS
Figure 27. Interleaved Leading / Trailing
Edge Modulation
Figure 27 shows the interleaved leading / trailing edge
modulation, where the turn-off of the PFC drive signal is
synchronized to the turn-on of the PWM drive signal.
This technique allows the PFC output diode current to
flow directly into the downstream DC/DC converter,
minimizing the current ripple of PFC output capacitor.
Gain Modulator
Gain modulator is the key block for the PFC stage
because it provides the reference to the current control
error amplifier for the input current shaping, as shown in
Figure 28. The output current of the gain modulator is a
function of VEA, IAC, and VRMS. The gain of the gain
modulator is given as a ratio between I MO and IAC with a
given VRMS when VEA is saturated to HIGH. The gain is
2
inversely proportional to VRMS , as shown in Figure 29,
to implement line feed-forward. This automatically
adjusts the reference of current control error amplifier
according to the line voltage, such that the input power
of PFC converter is not changed with line voltage (as
shown in Figure 30).
VIN
PFC Dead-Time
IL
OPFC
IEA
OPWM
RM
ISENSE
RM
RRMS1
IMO G I AC
I AC
RIAC
OPWM (FAN4800CU)
IAC
CRMS1
RRMS2
IAC
VRMS
CRMS2
k
x
2
RRMS3
Figure 26. Timing Diagram
K (VEA 0.6)
VRMS 2 (VEAMAX 0.6)
VEA
Gain
Modulator
Figure 28. Gain Modulator Block
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
FAN4800AU/CU — PFC/ PWM Controller Combination
Functional Description
The rectified sinusoidal signal is obtained by the current
flowing into the IAC pin. The resistor RIAC should be
large enough to prevent saturation of the gain
modulator, calculating as:
1
VRMS 2
7.94
2VLINE
RIAC
MIN
G MAX 140A
(3)
where VLINEMIN is the line voltage that trips brownout
protection, GMAX is the maximum modulator gain
when VRMS is 1.08 V (which can be found in the
datasheet), and 140 µA is the maximum output
current of the gain modulator.
Current Control of Boost Stage
VRMS
The FAN4800AU/CU employs two control loops for
power factor correction, as shown in Figure 32: a
current-control loop and a voltage-control loop. The
current-control loop shapes inductor current as shown
in Figure 33 based on the reference signal obtained at
the IAC pin calculated as:
VRMS-UVP
Figure 29. Modulation Gain Characteristics
VIN
I L RCS1 I MO RM I AC G RM
(4)
VIN
VO
IL
VEA
IL
FAN4800AU/CU — PFC/ PWM Controller Combination
G
RCS1
RF1
RM
IEA
ISENSE
RRMS1
RIC
CF1
IMO
RIAC
CIC2
IAC
Figure 30. Line Feed-Forward Operation
CRMS1
RRMS2
To sense the RMS value of the line voltage, averaging
circuit with two poles is typically employed, as shown in
Figure 28. Notice that the input voltage of the PFC is
clamped at the peak of the line voltage once the PFC
stops switching because the junction capacitance of the
bridge diode is not discharged, as shown in Figure 31.
Therefore, the voltage divider for VRMS should be
designed considering the brownout protection trip-point
and minimum operation line voltage.
PFC Runs
RM
IAC
VRMS
+
VEA
-
CRMS2
RRMS3
CIC1
VREF
Drive
logic
OPFC
RFB1
RVC
FBPFC
RVC2
RVC1
RFB2
2.5V
Figure 32. Gain Modulation Block
IAC
PFC Stops
VIN
I MO
RM
RCS1
IL
VRMS
Figure 33. Inductor Current Shaping
The current-control feedback loop also has a pulse-bypulse current limit comparator that forces the PFC
switch to turn off until the next switching cycle if the
ISENSE pin voltage drops below -1.3 V.
Figure 31. VRMS According to the PFC Operation
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
14
The voltage-control loop regulates PFC output voltage
using an internal error amplifier such that the FB
voltage is the same as the internal reference of 2.5 V.
Brownout Protection
No voltage error amplifier is included in the PWM stage,
as this function is generally performed by KA431, in the
secondary side. To facilitate the design of opto-coupler
feedback circuitry, an offset voltage is built into the
inverting input of PWM comparator. This allows
FBPWM to command a zero percent duty cycle when
its pin voltage is below 1.5 V.
The built-in internal brownout protection comparator
monitors the voltage of the VRMS pin. Once VRMS pin
voltage is lower than 1.05 V, the PFC stage is shut
down to protect the system from over current.
FAN4800AU/CU starts up the boost stage once VRMS
voltage increases above 1.9 V.
TriFault Detect™
VBOUT
To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the FAN4800AU/CU includes
Fairchild’s TriFault Detect technology.
REF
RRAMP
1.5V
-
In a feedback path failure, the output voltage of the PFC
can exceed safe operating limits. TriFault Detect
protects the power supply from a failure related to the
output feedback by monitoring the FBPFC voltage.
CRAMP
RAMP
TriFault Detect is an entirely internal circuit. It requires
no external components to serve its protective function.
VBOUT
PWM
+
FBPWM
Disable OPFC
0.5V
VDD
RFB1
FAN4800AU/CU — PFC/ PWM Controller Combination
For Voltage-Mode operation, RAMP can be connected to
a separate RC timing network to generate a voltage ramp
against which the FBPWM voltage is compared. Under
these conditions, the voltage feed-forward from the PFC
bus can be used for better line transient response.
Voltage Control of Boost Stage
+
-
Figure 35. PWM Ramp Generation Circuit
300nA
PWM Current Limit
+
FBPFC
2.75V
RFB2
The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. If the input voltage
at this pin exceeds 1 V, the output of the PWM is
disabled for until the start of the next PWM clock cycle.
-
TriFaultDetect
VIN OK Comparator
Figure 34. TriFault Detect™
The VIN OK comparator monitors the output of the PFC
stage and inhibits the PWM stage if this voltage is less
than 2.4 V (96% of its nominal value). Once this voltage
goes above 2.4 V, the PWM stage begins soft-start.
The PWM stage is shut down when FBPFC voltage
drops below 1.3 V.
PWM Stage
The PWM stage is capable of Current Mode or Voltage
Mode operation. In Current-Mode, the PWM ramp
(RAMP) is usually derived directly from a currentsensing resistor or current transformer in the primary
side of the output stage, and is thereby representative
of the current flowing in the converter’s output stage.
ILIMIT, which provides cycle-by-cycle current limiting, is
typically connected to RAMP in such applications.
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
PWM Soft-Start (SS)
PWM startup is controlled by the soft-start capacitor. A
current source of 10 µA supplies the charging current
for the soft-start capacitor. PWM startup is prohibited
until the soft-start capacitor voltage reaches 1.5 V.
www.fairchildsemi.com
15
VFBPFC
FAN4800AU/CU is designed such that the operation of
PFC part is not perturbed by AC line dropout. Once line
voltage disappears, the error amplifier can be saturated,
resulting in abnormal current waveforms when the line
voltage is recovered if proper preventive measures are
not employed.
With a limited gain modulator operation, FAN4800AU
/CU guarantees stable PFC operation even when AC
line is recovered from dropout, as shown in Figure 36.
VIN
VIN
PFC ILIMIT
Vo(gm)
IL
VRMS
33ms
VEA
0.85V
VEA Saturation
Figure 37. The First Condition of Sag Protection
VRMS
VFBPFC
Figure 36. AC Cycle Drop
Line Sag Protection
When the line sags below its normal operational
range, the PFC part keeps operating until the
brownout protection is triggered, which has 1 s
debounce time. Due to the low line voltage, the gain
modulator for current loop is saturated and input
current of PFC is limited, resulting in a drop of the
PFC output voltage at heavy-load condition. Since the
PWM part has a VIN OK comparator that shuts down
PWM operation when the FBPFC voltage drops below
1.3 V, the downstream DC-DC converter can stop
operation while the PFC output voltage drops during
line sag. Once the downstream converter stops
operation, even the limited PFC input current can
charge up the PFC output since the PFC part has no
load current. Because this can cause repeated startup
and shutdown of downstream converter during line
sag, FAN4800AU/CU has line sag protection.
FAN4800AU/CU — PFC/ PWM Controller Combination
AC Line Drops Out
1.3V
VIN
VRMS
25ms
0.85V
Figure 38. The Second condition of Sag Protection
There are two conditions that trigger line sag
protection, as shown in Figure 37 and Figure 38. The
first condition is when V RMS is lower than VRMS-SAG
(0.85 V) for longer than t SAG (33 ms), as shown in
Figure 37. The second condition is when V RMS is lower
than VRMS-SAG (0.85 V) and VFBPFC is lower than VIN-OFF
(1.3 V), as shown in Figure 38. Once line sag
protection is triggered, the PWM and the PFC stop
operation until VRMS increases above 1.9 V.
© 2011 Fairchild Semiconductor Corporation
FAN4800AU/CU • Rev. 1.4
www.fairchildsemi.com
16
19.69
18.67
A
16
9
7.11
6.10
1
8
(0.40)
B
TOP VIEW
8.25
7.62
1.78
1.14
0.28
0.20
4.95
2.92
5.33 MAX
3.81
2.92
C
0.38 MIN
2.54
0.56
0.36
0.25 M C
FRONT VIEW
NOTES:
A. CONFORMS TO JEDEC MS-001, VARIATION BB
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M-2009
E. DRAWING FILENAME: MKT-N16Erev3
10.92
SIDE VIEW
10.00
9.80
8.89
16
A
8.89
9
1.75
B
6.00
4.00
3.80
1
PIN #1
(0.30)
0.51
1.27 0.31
3.85
7.35
8
0.25
1.27
0.65
LAND PATTERN RECOMMENDATION
C B A
TOP VIEW
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.05
C
FRONT VIEW
0.50
0.25
R0.10
GAGE PLANE
R0.10
0.90
0.50
0.36
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
0.10 C
0.25
0.19
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AC, ISSUE C.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-2009
E) LANDPATTERN STANDARD:
SOIC127P600X175-16AM
F) DRAWING FILE NAME: M16AREV13.
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