FAN5904UC00X

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN5904 Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Features  2.7 V to 5.5 V Input Voltage Range  VOUT Range from 0.40 V to 3.50 V (or VIN)  Single 470 nH Small Form Factor Inductor  35 mΩ Integrated Bypass FET  100% Duty Cycle for Low Dropout Operation  Input Under-Voltage Lockout / Thermal Shutdown  1.71 mm x 1.71 mm, 16-Bump, 0.4 mm Pitch WLCSP  High Power PWM Mode o o o o  Up to 95% Efficient Synchronous Operation in High POUT Conditions Output current up to 2.3 A 10 µs Output Voltage Step Response for Early GSM Tx Power-Loop Settling 3MHz PWM Mode Low Power Auto Mode Up to 95% Efficient Synchronous Operation at Higher POUT Conditions o Output Current up to 1.2 A o 10 µs Output Voltage Step Response for Early Tx Power-Loop Settling o 6 MHz PWM Operation at High Power and PFM Operation at Low Power o  o Bypass Mode Up to 3 A Load Current Applications  Dynamic Supply Bias for Polar or Linear GSM/EDGE PAs and 3G/3.5G and 4G PAs  Description The FAN5904 is a high-efficiency, low-noise, synchronous, step-down, DC-DC converter optimized for powering Radio Frequency (RF) Power Amplifiers (PAs) in handsets and other mobile applications. In High-Power Mode, GSM Tx power is enabled. In Low-Power Mode, up to 3.0 W is supported, enabling up to 29 dBm output power for 3G/3.5G and 4G platforms. The output voltage may be dynamically adjusted from 0.40 V to 3.50 V, proportional to an analog input voltage VCON ranging from 0.16 V to 1.40 V, optimizing poweradded efficiency. Fast transition times of less than 10 µs are achieved, allowing excellent inter-slot settling. An integrated bypass FET is automatically enabled when the battery voltage and voltage drop across the DC-DC PMOS device are within a set voltage range of the desired output voltage (VOUT = VBAT - VPMOS - VBP_TH). This dynamic bypass feature enables the FAN5904 to support heavy load currents under the most stringent VSWR conditions while maintaining high efficiency and superior spectral performance. The bypass FET may also be enabled by providing a VCON voltage nominally greater than or equal to 1.5 V or by driving BPEN high. The FAN5904 operates in PWM Mode with a 6 MHz switching frequency in Low-Power Mode and at 3 MHz in High-Power Mode, which limits high-frequency spur levels. It uses a single, small form factor inductor of 470 nH. In addition, PFM operation is allowed in Low-Power Mode to improve efficiency at low load currents. The FAN5904UC00X option allows PFM Mode only when VOUT is less than 1 V, while the FAN5904UC01X permits PFM Mode at higher voltages for applications that can tolerate larger output ripple and that demand optimal low-tomoderate load current efficiency. Dynamic Supply Bias for GSM/EDGE Quad Band Amplifiers for Mobile Handsets and Data Cards Ordering Information Part Number LPM Mode PFM FAN5904UC00X VOUT < 1 V FAN5904UC01X All VOUT © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 Output Voltage 0.4 V to PVIN Temperature Range Package Packing 1.71 mm x 1.71 mm, 16-Bump -40°C to +85°C 0.4 mm Pitch, Wafer-Level Tape and Reel Chip-Scale Package (WLCSP) www.fairchildsemi.com FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs October 2013 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Block Diagrams Figure 1. Typical Application Figure 2. Simplified Block Diagram © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 2 Figure 3. Bumps Face Down – Top-Through View Figure 4. Bumps Face Up Pin Definitions Pin # Name Description C1 AGND A4, B4 FB D4 FB_SNS C2 EN D2 VCON Analog control pin. Shield signal routing against noise. D1 AVIN Analog supply voltage input. Connect to PVIN. C3 BPEN Force bypass when HIGH; Auto bypass when LOW. This pin should not be left floating. C4 SYNC External clock synchronization input. When SYNC is HIGH, the DC-DC does not allow PFM Mode. Tie SYNC to AGND if not used or in Auto-PFM Mode. This pin should not be left floating. D3 MODE Low-Power Auto Mode / High-Power PWM Mode select. When MODE = 1, the DC-DC is configured for 6MHz Low-Power Auto Mode. When MODE = 0, the DC-DC is configured for 3MHz High-Power PWM Mode. This pin should not be left floating. A3, B3 PVIN A2, B2 SW A1, B1 PGND Analog ground, reference ground for the IC. Follow PCB routing notes for connecting this pin. Output voltage sense pin. Connect to VOUT to establish feedback path for regulation point. Connect together on PCB. Feedback Sense pin. Connect to FB pins on PCB. Enables switcher when HIGH; Shutdown Mode when LOW. This pin should not be left floating. Supply voltage input to the internal MOSFET switches. Connect to input power source. Switching node of the internal MOSFET switches. Connect to output inductor. Power ground of the internal MOSFET switches. Follow routing notes for connections between PGND and AGND. © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 3 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Pin Configuration Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Min. Max. Voltage on AVIN, PVIN -0.3 6.0 Voltage on Any Other Pin -0.3 AVIN + 0.3 TJ Junction Temperature -40 +125 TSTG Storage Temperature -65 VIN TL ESD Parameter Lead Soldering Temperature (10 Seconds) Electrostatic Discharge Protection Level Human Body Model, JESD22-A114 2.0 Charged Device Model, JESD22-C101 1.0 Unit V °C +150 °C +260 °C kV Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VIN Supply Voltage Range 2.7 5.5 V VOUT Output Voltage Range 0.35 3 V, VCON Stepped Above 1.5 V Figure 43. VOUT Transient and Bypass Response ∆VOUT > 3 V, VCON Stepped Above 1.5 V Figure 44. Soft-Start Transient Response from 0 mA to 100 mA in High-Power Mode Figure 45. Soft-Start Transient Response from 0 mA to 100 mA in Low-Power Mode © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 14 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Typical Characteristics Unless otherwise noted, VIN = EN = 3.7 V, L = 1.0 µH, COUT = 2 x 4.7 µF, and TA = +25°C. High VOUT Low VOUT Figure 46. Soft-Start Transient Response from 0 mA to 800 mA in High-Power Mode Figure 47. Soft-Start Transient Response from 0 mA to 800 mA in Low-Power Mode Figure 48. Soft-Start Transient Response from 0 mA to 2000 mA in High-Power Mode Figure 49. Shutdown Transient Response, No Load Figure 50. Cold-Start Transient Response from 0 mA to 100 mA in High-Power Mode Figure 51. Cold-Start Transient Response from 0 mA to 100 mA in Low-Power Mode © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 15 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Typical Characteristics Unless otherwise noted, VIN = EN = 3.7 V, L = 1.0 µH, COUT = 2 x 4.7 µF, and TA = +25°C. Figure 52. Cold-Start Transient Response from 0 mA to 500 mA in High-Power Mode © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 Figure 53. Cold-Start Transient Response from 0 mA to 500 mA in Low-Power Mode www.fairchildsemi.com 16 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Typical Characteristics The FAN5904 is a high-efficiency, synchronous, stepdown converter operating with current-mode control. A wide range of load currents is supported. High-current applications, up to a DC output of 2.3 A demanded by GSM/EDGE applications, are allowed. Performance degradation due to spurs is mitigated by selection of a 3 MHz or 6 MHz switching rate. Moreover, the FAN5904 offers Bypass Mode, where the output is shorted to the battery input via a low on-state resistance bypass FET. The output voltage VOUT is regulated to 2.5 times the input control voltage, VCON, set by an external DAC. The FAN5904 operates in either PWM or PFM Mode, depending on the output voltage and load current. In Pulse Width Modulation (PWM) Mode, regulation begins with an on-state where a P-channel transistor is turned on and the inductor current is ramped up until the off-state begins. In off-state, the P-channel is switched off and an N-channel transistor is turned on. The inductor current decreases to maintain an average value equal to the DC load current. The inductor current is continuously monitored. A current sense detects when the P-channel transistor current exceeds the current limit and the switcher is turned back to off-state to decrease the inductor current and prevent magnetic saturation. Similarly, the current sense detects when the N-channel transistor current exceeds the current limit and redirects discharging current through the inductor back to the battery. In Pulse Frequency Modulation (PFM) Mode, at low load currents, the FAN5904 operates in a constant on-time mode. During the on-state, the P-channel is turned on for a specified on-time before switching to off-state, during which the N-channel switch is enabled until the inductor current decreases to 0 A. The switcher output is then put in high-impedance state until a new regulation cycle starts. PFM operation is allowed only in Low-Power Mode. At low load currents, PFM achieves higher efficiencies than PWM. To allow optimization of system performance, two versions of the FAN5904 are available. The FAN5904UC00X enables PFM only when VOUT is less than approximately 1 V. The FAN5904UC01X allows PFM to be entered at higher output voltages. PFM Mode is only enabled for output load currents nominally less than 100 mA. This realizes high efficiency down to 10mA load current. This is not supported in HighPower Mode (MODE = 0) and may be disabled in LowPower Mode by tying the SYNC input HIGH. Low-Power Auto Mode (MODE = 1) Low-Power Auto Mode is ideal for 3G/3.5G and 4G applications. Current sense limits are nominally 1.65 Apk and power levels up to 29 dBm are supported. High-Power PWM Mode (MODE = 0) Due to the large current requirements in GSM/EDGE applications, only PWM Mode is supported when the FAN5904 is configured for High-Power Mode. Currentsense limits are increased to allow for large load currents up to a maximum of approximately 3.3 A. Bypass Mode In Bypass Mode, the DC-DC turns into 100% duty cycle and the bypass FET is turned on, which allows a very low voltage dropout and up to 3.0 A load current. Table 1. Mode Definitions Mode Mode Description Conditions MODE SYNC BPEN EN X X X 0 1 0 0 1 3 Forced PWM Mode Low Power DC-DC in PWM Mode only 1 1 0 1 4 PWM Mode High Power DC-DC in PWM High-Power Mode 0 0 0 1 5 Bypass Mode Bypass FET and PFET forced to 100% duty-cycle X X 1 1 1 Standby Mode 2 Auto Mode Low Power Whole IC disabled (10) DC-DC in Auto Mode Note: 10. When VOUT exceeds the bypass threshold, the bypass FET is enabled and the DC-DC goes to 100% duty cycle. When VOUT is less than the exit threshold, the bypass FET is disabled and the DC-DC re-enters Auto Mode. © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 17 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Operating Description The output voltage of the FAN5904 is determined by VCON provided by an external DAC or voltage reference: VOUT = 2.5 ×VCON (1) Figure 55. Enabling Bypass Transistor Circuit The bypass FET is turned on progressively using a slew rate controller to limit the inrush current since Bypass Mode effectively shorts the input supply bus to a capacitive load. The resulting inrush current is expressed as a function of the specified slew rate as follows: IINRUSH ≈ COUT Figure 54. Output Voltage vs. Control Voltage ΔVOUT = COUT • VBP_SLEW Δt (2) PFM Lockout Mode and Synchronization The FAN5904 is able to provide a regulated VOUT only if VCON falls within the typical range from 0.16 V to 1.40 V. This allows VOUT to be adjusted between 0.4 V and 3.5 V. If VCON is less than 0.16 V, VOUT is clamped to 0.40 V.The part enters Bypass Mode for VCON > 1.50 V. In Low-Power Mode (MODE = 1), the FAN5904 automatically switches between PFM, PWM, and Bypass Modes. In High-Power Mode (MODE = 0), the FAN5904 automatically switches between PWM and Bypass Modes and PFM operation is not available. It may be desirable to prevent the DC-DC converter from operating in PFM Mode. For example, the low PFM switching frequency may interfere with audio circuitry and using PWM may eliminate the interference. When configured for Low-Power Mode (MODE = 1) a logic 1 on the SYNC pin forces the IC to avoid PFM Mode. Logic 0 allows the IC to automatically switch to PFM Mode during light loads. When VOUT approaches the battery voltage, the DC-DC operates in a constant off-time mode and the frequency is adjusted to achieve high duty cycle. The system operates in this regulated mode until the bypass condition is satisfied. In Low-Power or High-Power Modes, toggling the SYNC pin forces the converter to synchronize its switching frequency to the frequency on the SYNC pin (fSYNC). The signal must be within the oscillator synchronization frequency range and meet the threshold voltage requirements. Bypass Mode Dynamic Output Voltage Transitions As VOUT and the battery voltage converge, the DC-DC begins to operate in constant off-time mode until eventually the DC-DC transitions to 100% duty cycle and the low RDSON bypass FET is turned on. The battery voltage that results in 100% duty cycle operation depends on the output voltage, the voltage drop across the DC-DC converter, and the DC voltage drop across the inductor. In other words, the duty cycle is set by the ratio of the voltages across the inductor. FAN5904 has a complex voltage transition controller that realizes 10µs transition times with a large output capacitor and output voltage ranges. The transition controller manages five transitions:      In many RF applications, it is undesirable for the DC-DC to reach 100% duty cycle since this would result in excessive output ripple. To minimize ripple, the FAN5904 implements a dynamic bypass threshold based on the voltage difference between the battery voltage (sensed through the AVIN pin), the voltage drop across the DC-DC PMOS device, and the internally generated reference voltage VREF, as described in Figure 55. The Bypass Mode enter and exit thresholds are higher in High-Power Mode due to the higher load current capability. Bypass Mode is also entered when VCON exceeds 1.5 V and exited when VCON is less than 1.4 V. © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 ΔVOUT positive step ΔVOUT negative step ΔVOUT transition from or to Bypass Mode ΔVOUT transition at startup ΔVOUT transition after BPEN In all cases, it is recommended that sharp VCON transitions be applied, letting the transition controller optimize the output voltage slew rate. www.fairchildsemi.com 18 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs DC Output Voltage VOUT Transition after BPEN When BPEN goes HIGH, the controller dismisses the internal bypass flags and sensors and enables Bypass Mode. However, the transition is managed with the same current limits and slew rate used during regular transitions. ΔVOUT Negative Step After a VCON negative step, the FAN5904 enters a current limit mode where VOUT is reduced with a constant slew rate dictated by the output capacitor and the current limit ILIMn. Thermal Protection VOUT Transition to or from Bypass Mode The transition to or from Bypass Mode requires that the bypass conditions be met. The FAN5904 performs detection of the bypass conditions 2 µs after VCON transition and enables the required charging / discharging circuit to realize a transition time of 20 µs. When the junction temperature exceeds the maximum specified junction temperature, the FAN5904 enters PowerDown Mode (except the thermal detection circuit). VOUT Transition at Startup Application Information Figure 56 illustrates an application of the FAN5904 in a GSM/EDGE/WCDMA transmitter configuration. The FAN5904 is ideal for driving multiple GSM/EDGE and 3G/3.5G and 4G PAs. Figure 57 presents a timing diagram designed to meet GSM specifications. The FAN5904 is designed to support voltage transients of 10 µs when configured for GSM/EDGE applications (MODE = 0) and driving a load capacitance of approximately 10 µF. Figure 58 shows a timing diagram for WCDMA applications. Figure 56. Typical Application Diagram with GSM/EDGE/WCDMA Transmitters © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 19 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs At startup, after EN rising edge is detected, the system requires 25 µs to allow all internal voltage references and amplifiers to start before enabling the DC-DC function. ΔVOUT Positive Step After a VCON positive step, the FAN5904 goes into a current limit mode, where VOUT ramps with a constant slew rate dictated by the output capacitor and the current limit ILIMp Figure 58. Timing Diagram for WCDMA Transmitters Application Information Inductor Selection Capacitor Selection The FAN5904 operates at 6 MHz switching frequency in Low-Power Mode and 3 MHz in High-Power Mode and, as such, 470 nH or 1.0 µH inductors can be used, respectively. For applications requiring the smallest possible PCB area, use a 470 nH 2016 inductor; or a 1.0 µH 3030 inductor for optimum efficiency performance. The minimum required output capacitor COUT should be two (2) 4.7 µF, 10 V, X5R with an ESR of 10 mΩ or lower, and an ESL of 0.3 nH or lower placed in parallel after inductor L1. Larger case sizes result in increased loop parasitic inductance and higher noise. One of the 4.7 µF capacitors should be used as a decoupling capacitor at the GSM/EDGE PA VCC pin. Table 2. Recommended Inductors Inductor A 0.1 µF capacitor may be added in parallel with COUT to reduce the capacitor’s parasitic inductance. Description 470 nH, ±30%, 2.3 A, 2016 (metric) TDK: VLS201610MT-R47N L Table 3. Recommended Capacitor Values 470 nH, ±30%, 2.8 A, 2520 (metric) TDK: VLS252010T-R47N Capacitor 470 nH, ±20%, 2.3 A, 2520 (metric) Samsung: CIG22HR47MNE COUT CIN C for VCON 470 nH, ±20%, 1.8 A, 2520 (metric) Taiyo-Yuden: CKP2520R47M Description 10 µF, ±20%, X5R, 10 V (2) 4.7 µF, ±20%, X5R, 6.3 V 470 pF, ±20%, X5R, 25 V 1.0 µH, ±20%, 2.4 A, 3030 (metric) Coilcraft: XFL3010-102ME © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 20 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Figure 57. Timing Diagram for GSM/EDGE Transmitters Assembly VCON is the analog control pin of the DC-DC and should be connected to an external Digital-to-Analog Converter (DAC). It is recommended to add up to 470 pF decoupling capacitance between VCON and AGND to filter DAC noise. This capacitor also helps protect the DAC from the DC-DC high-frequency switching noise inherently coupled through the VCON pin. The value of the capacitor must be selected according to the DAC performance since it could limit the DAC output voltage slew rate. 470 pF is typically used.  Use lead-free solder reflow temperature profile.  Use metal-filled or solder-filled vias, if available.  Poor soldering can cause low DC-DC conversion efficiency. If the efficiency is low, X-ray the solder connections to verify their integrity.  PVIN and PGND must be routed with the widest and shortest traces possible. It is acceptable for the traces connecting the inductor to be long rather than having long PVIN or PGND traces.  Ensure that the routing loop, PVIN – PGND – VOUT is as short as possible.  Place PGND on the top layer and connect it to the AGND ground plane next to Cout using several vias.  The SW node is a source of electrical switching noise. Do not route it near the VCON pin.  Two small vias are used to connect the SW node to the inductor L1. Use solder-filled vias, if available.  The connection from COUT to FB should be wide to minimize the Bypass Mode voltage drop and the series inductance. Even if the current in Bypass Mode is small, keep this trace short and at least 5 mm wide.  The AGND ground plane should not be broken into pieces. Ground currents must have a direct, wide path from input to output.  Each capacitor should have at least two dedicated ground vias. Place vias within 0.1 mm of the capacitors. Any noise on the VCON input is transferred to VOUT with a gain of two and a half (2.5). If the DAC output is noisy, a series resistor may be inserted between the DAC output and the capacitor to form an RC filter. Follow these guidelines:  Use a low noise source or a driver with good PSRR to generate VCON.  The VCON driver must be referenced to AGND.  VCON routing must be protected against PVIN, SW, and PGND signals, as well as other noisy signals. Use AGND shielding for better isolation.  Be sure the DAC output can drive the capacitor on VCON. It may be necessary to insert a low-value resistor to ensure DAC stability while not slowing VCON fast transition times. No Floating Inputs The FAN5904 does not have internal pull-down resistors on its inputs. Therefore, unused inputs should not be left floating and should be pulled HIGH or LOW. PCB Layout and Component Placement  The key point in the placement is the power ground PGND connection shared between the FAN5904, C1, and C2. This minimizes the parasitic inductance of the switching loop paths.  Place the inductor away from the feedback pins to prevent unpredictable loop behavior.  Ensure the traces are wide enough to handle the maximum current value, especially in Bypass mode.  Ensure the vias are able to handle the current density. Use filled vias if available.  Refer to Fairchild’s application note: AN9726 — The Importance of PCB Design for FAN5903 and FAN5904. Figure 59. Example PCB Layout of FAN5904 © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 21 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Filter VCON 0.03 C 2X E F A B 0.40 (Ø0.20) Cu Pad A1 BALL A1 INDEX AREA D 0.40 (Ø0.30) Solder Mask Opening 0.03 C 2X RECOMMENDED LAND PATTERN (NSMD PAD TYPE) TOP VIEW 0.06 C 0.625 0.547 0.05 C C SEATING PLANE 0.378±0.018 0.208±0.021 E SIDE VIEWS D NOTES: A. NO JEDEC REGISTRATION APPLIES. 0.005 B. DIMENSIONS ARE IN MILLIMETERS. C A B Ø0.260±0.02 16X 0.40 D C B 0.40 C. DIMENSIONS AND TOLERANCE PER ASME Y14.5M, 1994. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. (Y) ±0.018 A E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS ±39 MICRONS (547-625 MICRONS). F 1 2 3 4 (X) ±0.018 F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. BOTTOM VIEW G. DRAWING FILNAME: MKT-UC016AArev2. Product D E X Y Unit FAN5904UC00X 1.710 ±0.030 1.710 ±0.030 0.255 0.255 mm FAN5904UC01X 1.710 ±0.030 1.710 ±0.030 0.255 0.255 mm Figure 60. 1.71x1.71 mm Square, 16 Bumps, 0.4 mm Pitch, WLCSP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 22 FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs Physical Dimensions FAN5904 — Multi-Mode Buck Converter for GSM/EDGE, 3G/3.5G and 4G PAs © 2011 Fairchild Semiconductor Corporation FAN5904 • Rev. 3.0.7 www.fairchildsemi.com 23 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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