High-Current, Half-Bridge,
Gate-Driver IC
FAN73912
Description
The FAN73912 is a monolithic half bridge gate−drive IC designed
for high−voltage and high−speed driving for MOSFETs and IGBTs
that operate up to +1200 V.
The advanced input filter of HIN provides protection against
short−pulsed input signals caused by noise.
An advanced level−shift circuit offers high−side gate driver
operation up to VS = −9.8 V (typical) for VBS = 15 V. The UVLO
circuit prevents malfunction when VCC and VBS are lower than
the specified threshold voltage.
Output drivers typically source and sink 2 A and 3 A, respectively.
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SOIC−16W
CASE 751BH
Features
• Floating Channel for Bootstrap Operation to +1200 V
• Typically 2 A/ 3 A Sourcing/Sinking Current Driving Capability for
•
•
•
•
•
•
•
•
•
•
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Both Channels
Gate Driver Supply (VCC) Range from 12 V to 20 V
Separate Logic Supply (VDD) Range from 3 V to 20 V
Extended Allowable Negative VS Swing to −9.8 V for Signal
Propagation at VCC = VBS = 15 V
Built−in Cycle−by−Cycle Edge−Triggered Shutdown Logic
Built−in Shoot−Through Protection Logic
Common−Mode dv/dt Noise Canceling Circuit
UVLO Functions for Both Channels
Built−in Advanced Input Filter
Matched Propagation Delay Below 50 ns
Outputs in−Phase with Input Signal
Logic and Power Ground +/− 10 V Offset
This Device is Pb−Free and Halogen Free
February, 2021 − Rev. 2
$Y
&Z
&2
&K
FAN73912MX
= ON Semiconductor Logo
= Assembly Plant Code
= 2−Digit Date Code
= Lot Code
= Specific Device Code
ORDERING INFORMATION
FAN73912MX
(Note 1)
Electrical Contactor
UPS
Solar Inverter
Ballast
General−Purpose Half−Bridge Topology
© Semiconductor Components Industries, LLC, 2016
$Y&Z&2&K
FAN73912
MX
Device
Typical Application
•
•
•
•
•
MARKING DIAGRAM
Package
Shipping†
Wide−16
SOIC
1,000/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1. This device passed wave−soldering test by
JESD22A−111
1
Publication Order Number:
FAN73912/D
FAN73912
Up to 1200 V
Q1
Typically
3.3~15 V
Controller
R1
9 NC
HO 8
10 NC
VB
7
11 VDD
VS
6
HIN
12 HIN
NC
5
DBOOT
SD
13 SD
NC
4
RBOOT
LIN
14 LIN
VCC
3
15 VSS
COM
2
CBOOT
Load
15 V
C1
Q2
R2
16 NC
1
LO
Figure 1. Application Schematic − Adjustable Option
7 VB
UVLO
LIN 14
VSS 15
VSS/COM
LEVEL
SHIFT
R R
S
Q
8 HO
6 VS
3 VCC
UVLO
CYCLE−By −
CYCLE EDGE
TRIGGERED
SHUTDOWN
DELAY
LS(ON/OFF)
DRIVER
SD 13
SCHMITT
TRIGGER
INPUT
SHOOTTHROUGH
PREVENTION
NOISE
CANCELLER
DRIVER
HIN 12
PULSE
GENERATOR
HS(ON/OFF)
VDD 11
1 LO
2 COM
Pin 4,5,9,10 and 16 are no connection
Figure 2. Simplified Block Diagram
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2
FAN73912
LO
1
16 NC
COM
2
15 VSS
FAN73912A
VCC 3
14 LIN
NC
4
13 SD
NC
5
12 HIN
VS
6
11 V
DD
VB
7
10 NC
HO
8
9
NC
Figure 3. Pin Connections − Wide 16−SOIC
(Top View)
Table 1. PIN FUNCTION DESCRIPTION
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin No.
Symbol
Description
1
LO
Low−Side Driver Output
2
COM
Low−Side Driver Return
3
VCC
Low−Side Supply Voltage
4
NC
No Connection
5
NC
No Connection
6
VS
High−Voltage Floating Supply Return
7
VB
High−Side Floating Supply
8
HO
High−Side Driver Output
9
NC
No Connection
10
NC
No Connection
11
VDD
Logic Supply Voltage
12
HIN
Logic Input for High−Side Gate Driver Output
13
SD
Logic Input for Shutdown
14
LIN
Logic Input for Low−Side Gate Driver Output
15
VSS
Logic Ground
16
NC
No Connection
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3
FAN73912
Table 2. MAXIMUM RATINGS (TJ = 25°C, unless otherwise specified. All voltage parameters are referenced to COM unless
otherwise stated in the table.)
Parameter
Symbol
Min
Max
Unit
VB
High−Side Floating Supply Voltage
−0.3
1225.0
V
VS
High−Side Floating Offset Voltage
VB −25
VB +0.3
V
VHO
High−Side Floating Output Voltage
VS −0.3
VB +0.3
V
VCC
Low−Side Supply Voltage
−0.3
25
V
VLO
Low−Side Floating Output Voltage
VDD
Logic Supply Voltage
VSS
Logic GND
VIN
Logic Input Voltage (HIN, LIN and SD)
−0.3
VCC +.0.3
V
VSS −0.3
−0.3
VSS +25
25
V
VDD −25
VDD +0.3
V
VSS + VDD −25.3
−0.3
VDD +0.3
25
V
Allowable Offset Voltage Slew Rate
−
±50
V/ns
Power Dissipation
−
1.3
W
qJA
Thermal Resistance
−
95
°C/W
TJ
Junction Temperature
−
150
°C
TSTG
Storage Temperature
−55
150
°C
dVS/dt
PD
(Note 2, 3, 4)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material).
3. Refer to the following standards:
JESD51−2: Integral circuit’s thermal test method environmental conditions, natural convection;
JESD51−3: Low effective thermal conductivity test board for leaded surface−mount packages.
4. Do not exceed maximum power dissipation (PD) under any circumstances.
Table 3. RECOMMENDED OPERATING CONDITIONS (All voltage parameters are referenced to COM unless otherwise stated in
the table)
Parameter
Symbol
Min
Max
Unit
VB
High−Side Floating Supply Voltage
VS + 12
VS + 20
V
VS
High−Side Floating Supply Offset Voltage (Note 6)
8 − VCC
1200
V
VHO
High−Side (HO) Output Voltage
VS
VB
V
VCC
Low−Side Supply Voltage
12
20
V
VLO
Low−Side (LO) Output Voltage
0
VCC
V
VDD
Logic Supply Voltage
VSS + 3
0
VSS + 20
20
V
VSS
Logic Ground (Note 5)
−10
10
V
VIN
Logic Input Voltage (HIN, LIN, SD)
VSS + VDD − 20
0
VDD
20
V
TJ
Junction Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. When VDD < 10 V, the minimum VSS offset is limited to −VDD.
6. Referenced to TJ = 25°C.
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FAN73912
Table 4. STATIC ELECTRICAL CHARACTERISTICS (VBIAS (VCC, VBS, VDD) = 15.0 V, TJ = 25°C, unless otherwise specified.
The VIH, VIL and IIN parameters are referenced to VSS and are applicable to respective input leads: HIN, LIN and SD. The VO and IO
parameters are referenced to VS and COM and are applicable to the respective output leads: HO and LO. The VDDUV parameters are
referenced to COM. The VBSUV parameters are referenced to VS1, 2, 3.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LOW−SIDE POWER SUPPLY SECTION
IQCC
Quiescent VCC Supply Current
VIN = 0 V or VDD
−
170
300
mA
IQDD
Quiescent VDD Supply Current
VIN = 0 V or VDD
−
−
10
mA
IPCC
Operating VCC Supply Current
fIN = 20 kHz, rms VIN = 15 VPP
−
650
950
mA
IPDD
Operating VDD Supply Current
fIN = 20 kHz, rms VIN = 15 VPP
−
2
−
ISD
Shutdown Supply Current
SD = VDD
−
30
50
mA
VCCUV+
VCC Supply Under−Voltage
Positive−Going Threshold Voltage
VCC = Sweep
9.7
11.0
12
V
VCCUV−
VCC Supply Under−Voltage
Negative−Going Threshold Voltage
VCC = Sweep
9.2
10.5
11.4
V
VCCUVH
VCC Supply Under−Voltage Lockout
Hysteresis Voltage
VCC = Sweep
−
0.5
−
V
BOOTSTRAPPED SUPPLY SECTION
IQBS
Quiescent VBS Supply Current
VIN = 0 V or VDD
−
50
100
mA
IPBS
Operating VBS Supply Current
fIN = 20 kHz, rms value
−
550
850
mA
VBSUV+
VBS Supply Under−Voltage
Positive−Going Threshold Voltage
VBS = Sweep
9.7
11.0
12.0
V
VBSUV−
VBS Supply Under−Voltage
Negative−Going Threshold Voltage
VBS = Sweep
9.2
10.5
11.4
V
VBSUVH
VBS Supply Under−Voltage Lockout
Hysteresis Voltage
VBS = Sweep
−
0.5
−
V
Offset Supply Leakage Current
VB = VS = 1200 V (TJ = 25°C)
−
−
50
mA
VB = VS = 1200 V (TJ = 125°C) (Note 7)
−
−
100
VB = VS = 1100 V (TJ = −40°C) (Note 7)
−
−
100
VDD = 3 V
2.4
−
−
VDD = 15 V
9.5
−
−
VDD = 3 V
−
−
0.8
VDD = 15 V
−
−
6.0
30
50
ILK
INPUT LOGIC SECTION (HIN.LIN AND AD)
VIH
VIL
Logic “1” Input Voltage
Logic “0” Input Voltage
V
V
IIN+
Logic “1” Input bias Current
VIN = 15 V
−
IIN−
Logic “0” Input bias Current
VIN = 0 V
−
−
1
mA
RIN
Logic Input Pull−down Resistance
−
500
−
kW
mA
GATE DRIVER OUTPUT SECTION
VOH
High−Level Output Voltage,
VBIAS−VO
IO = 0 A
−
−
1.2
V
VOL
Low−Level Output Voltage, VO
IO = 0 A
−
−
0.1
V
IO+
Output HIGH Short−Circuit Pulse
Current
VO = 0 V, VIN = 5 V with PW ≤ 10 ms
−
2.0
−
A
IO−
Output LOW Short−Circuit Pulsed
Current
VO = 15 V, VIN = 0 V with PW ≤ 10 ms
−
3.0
−
A
VS
Allowable Negative VS Pin Voltage
for HIN Signal Propagation to HO
−
−9.8
−7.0
V
7. These parameters are guaranteed by design.
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FAN73912
Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS (VBIAS(VCC, VBS, VDD) = 15.0 V, VS = VSS = COM, CL = 1000 pF and
TJ = 25°C, unless otherwise specified.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
LOW−SIDE POWER SUPPLY SECTION
tON
Turn−On Propagation Delay
VS = 0 V
−
500
−
ns
tOFF
Turn−Off Propagation Delay
VS = 0 V
−
550
−
ns
tFLTIN
Input Filtering Time (HIN, LIN)
(Note 8)
80
150
220
ns
tFLTSD
Input Filtering Time (SD)
−
30
−
ns
260
330
400
ns
ns
tSD
Shutdown Propagation Delay Time
tR
Turn−On Rise Time
−
25
−
tF
Turn−Off Fall Time
−
15
−
DT
Dead Time
−
−
50
ns
−
50
100
ns
MDT
Dead Time Matching (Note 9)
MT
Delay Matching ,
HO & LO Turn−On/OFF (Note 10)
PM
Output Pulse−Width Matching
(Note 11)
PWIN > 1 ms
8. The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded.
9. MDT is defined as | DTHO−LO−DTLO−HO | referenced to Figure 40.
10. MT is defined as an absolute value of matching delay time between High−side and Low−Side.
11. PM is defined as an absolute value of matching pulse−width between Input and Output.
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FAN73912
580
620
560
600
540
580
tOFF [ns]
tON [ns]
TYPICAL CHARACTERISTICS
520
500
560
540
480
520
460
500
440
−40
−20
0
20
40
60
80
100
480
−40
120
−20
0
Temperature [°C]
100
120
30
40
25
35
20
tF [ns]
30
tR [ns]
80
Figure 5. Turn−Off Propagation Delay
vs. Temperature
Figure 4. Turn−On Propagation Delay
vs. Temperature
25
15
20
10
15
5
10
−40
−20
0
20
40
60
80
100
0
−40
120
−20
0
Temperature [°C]
50
40
40
MTOFF [ns]
50
30
20
10
0
−40
80
60
20
40
Temperature [°C]
100
120
Figure 7. Turn−Off Fall Time vs. Temperature
Figure 6. Turn−On Rise Time vs Temperature
MTON [ns]
20
40
60
Temperature [°C]
30
20
10
−20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
80
100
Temperature [°C]
Temperature [°C]
Figure 9. Turn−Off Delay Matching
vs. Temperature
Figure 8. Turn−On Delay Matching
vs. Temperature
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7
120
FAN73912
TYPICAL CHARACTERISTICS (continued)
400
40
380
IIN+ [mA]
tSD [ns]
30
360
340
20
320
10
300
280
−40
−20
0
20
40
60
Temperature [°C]
80
100
0
−40
120
40
60
80
100
120
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
−20
0
20
40
60
80
100
0.0
−40
120
−20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 13. Quiescent VDD Supply Current
vs. Temperature
Figure 12. Quiescent VCC Supply Current
vs. Temperature
80
800
70
700
60
600
50
IPCC [mA]
IQBS [mA]
20
Figure 11. Logic Input High Bias Current
vs. Temperature
IQDD [mA]
IQCC [mA]
0
Temperature [°C]
Figure 10. Shutdown Propagation Delay
vs. Temperature
220
210
200
190
180
170
160
150
140
130
120
110
100
−40
−20
40
30
500
400
20
300
10
0
−40
−20
0
20
40
60
80
100
200
−40
120
−20
0
20
40
60
80
100
Temperature [°C]
Temperature [°C]
Figure 15. Operating VCC Supply Current
vs. Temperature
Figure 14. Quiescent VBS Supply Current
vs. Temperature
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120
FAN73912
TYPICAL CHARACTERISTICS (continued)
5.0
1000
4.5
800
3.5
IPBS [mA]
IPDD [mA]
4.0
3.0
2.5
2.0
600
400
1.5
200
1.0
0.5
0.0
−40
−20
0
20
40
60
80
100
0
−40
120
60
80
100
120
Figure 17. Operating VBS Supply Current
vs. Temperature
11.0
10.8
VCCUV− [V]
10.8
10.6
10.6
10.4
10.2
10.0
10.4
9.8
10.2
9.6
−20
0
20
40
60
80
100
−40
120
−20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 19. VCC UVLO− vs. Temperature
Figure 18. VCC UVLO+ vs. Temperature
11.0
11.4
10.8
11.2
10.6
VBSUV− [V]
11.0
VBSUV+ [V]
40
Figure 16. Operating VDD Supply Current
vs. Temperature
11.0
10.8
10.6
10.4
10.4
10.2
10.0
9.8
10.2
10.0
−40
20
Temperature [°C]
11.2
VCCUV+ [V]
0
Temperature [°C]
11.4
10.0
−40
−20
9.6
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
Temperature [°C]
Temperature [°C]
Figure 20. VBS UVLO+ vs. Temperature
Figure 21. VBS UVLO− vs. Temperature
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120
FAN73912
TYPICAL CHARACTERISTICS (continued)
0.010
0.008
1.4
0.006
0.004
1.0
VOL [V]
VOH [V]
1.2
0.8
0.002
0.000
−0.002
0.6
−0.004
0.4
−0.006
0.2
0.0
−40
−20
0
20
40
60
80
100
−0.008
−0.010
−40
120
−20
0
20
10
10
9
9
8
8
VIL− [V]
VIH [V]
100
120
7
7
6
5
6
5
4
4
3
3
2
2
−20
0
20
40
60
80
100
1
−40
120
−20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 25. Logic Low Input Voltage
vs. Temperature
Figure 24. Logic High Input Voltage
vs. Temperature
12
Logic Threshold Voltage [V]
−7
−8
VS [V]
80
Figure 23. Low−Level Output Voltage
vs. Temperature
Figure 22. High−Level Output Voltage
vs. Temperature
−9
−10
−11
−12
−40
60
Temperature [°C]
Temperature [°C]
1
−40
40
−20
0
20
40
60
80
100
10
8
6
4
2
0
120
0
Temperature [°C]
2
4
6
8
10
12
14
16
18
VDD Logic Supply Voltage [V]
Figure 27. Input Logic (HIN&LIN) Threshold
Voltage vs. VDD Supply Voltage
Figure 26. Allowable Negative VS
vs. Temperature
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10
20
FAN73912
−4
600
580
−6
560
tON [ns]
VS [V]
TYPICAL CHARACTERISTICS (continued)
−8
−10
540
520
500
480
−12
460
−14
440
−16
420
400
10
11
12
13
14
15
16
17
18
19
20
3 4
5 6
VDD Supply Voltage [V]
VCC Supply Voltage [V]
Figure 29. Turn−On Propagation Delay
vs. VDD Supply Voltage
Figure 28. Allowable Negative VS Voltage
for HIN Signal Propagation to High Side
vs. VCC Supply Voltage
600
350
580
300
540
tFLTIN [ns]
tOFF [ns]
560
520
500
480
460
250
200
150
100
440
420
400
50
3 4
0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VDD Supply Voltage [V]
7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 31. Logic Input Filtering Time
vs. VDD Supply Voltage
160
440
140
420
120
400
100
380
tSD [V]
tFLTSD [ns]
3 4 5 6
VDD Supply Voltage [V]
Figure 30. Turn−Off Propagation Delay
vs. VDD Supply Voltage
80
60
360
340
320
40
300
20
280
260
0
7 8 9 10 11 12 13 14 15 16 17 18 19 20
3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VDD Supply Voltage [V]
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VDD Supply Voltage [V]
Figure 33. Shutdown Propagation Delay
vs. VDD Supply Voltage
Figure 32. Shutdown Input Filtering Time
vs. VDD Supply Voltage
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11
FAN73912
TYPICAL CHARACTERISTICS (continued)
400
380
26
24
360
22
MDT [ns]
DT [ns]
340
320
300
280
18
260
240
220
200
20
16
3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
14
VDD Supply Voltage [V]
VDD Supply Voltage [V]
Figure 35. Dead−Time Matching
vs. VDD Supply Voltage
Figure 34. Dead Time vs. VDD Supply Voltage
100
PM [ns]
80
60
40
20
0
3 4
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VDD Supply Voltage [V]
Figure 36. Output Pulse−Width Matching
vs. VDD Supply Voltage
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12
FAN73912
SWITCHING TIME DEFINITIONS
9 NC
HO 8
10 NC
VB 7
11 VDD
VS 6
HIN
12 HIN
NC 5
SD
13 SD
NC 4
14 LIN
VCC 3
15 VSS
COM 2
16 NC
LO 1
15 V
LIN
HO
100 nF
1 nF
15 V
(0 to 1200 V)
15 V
100 nF
LO
1 nF
Figure 37. Switching Time Test Circuit
A
B
C
D
HIN
LIN
SD
Shutdown
Shutdown
SKIP
SKIP
Shoot−Through
Protection
HO
Shoot−Through
Protection
LO
Figure 38. Input/Output Timing Diagram
HIN
50%
50%
More than
dead−time
More than
dead−time
LIN
50%
50%
tOFF
tOFF
90%
HO
tF
tON
10%
10%
tOFF
tR
LO
50%
tON
90%
90%
10%
Figure 39. Switching Time Definition
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13
90%
FAN73912
SWITCHING TIME DEFINITIONS (continued)
HIN
50%
LIN
50%
tOFF
DTLO−HO
90%
HO
10%
DTHO−LO
tR
90%
90%
LO
tOFF
10%
tF
MDT = ⎪DTHO−LO − DTLO−HO⎟
Figure 40. Internal Dead Time Definition
HIN
50%
50%
(LIN)
ton
tr
toff
90%
tf
90%
HO
(LO)
10%
10%
Figure 41. Switching Time Waveform Definitions
50%
SD
tSD
90%
HO
(LO)
Figure 42. Switching Time Definitions
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14
10%
FAN73912
APPLICATIONS INFORMATION
Dead Time
Shutdown Input
Dead time is automatically inserted whenever the dead
time of the external two input signals (between HIN and LIN
signals) is shorter than internal fixed dead times (DT1 and
DT2). Otherwise, external dead times larger than internal
dead times are not modified by the gate driver and internal
dead−time waveform definition is shown in Figure 43.
When the SD pin is in LOW state, the gate driver operates
normally. When a condition occurs that should shut down
the gate driver, the SD pin should be HIGH. The Shutdown
circuitry has an input filter; the minimum input duration is
specified by tFLTIN (typically 250 ns).
HIN
50%
SD
50%
LIN
tSD
50%
90%
50%
HO
(LO)
LO
DT1
HO
DT2
50%
50%
Figure 45. Output Shutdown Timing Waveform
Figure 43. Internal Dead−Time Definitions
Noise Filter
Input Noise Filter
Figure 46 shows the input noise filter method, which has
symmetry duration between the input signal (tINPUT) and the
output signal (tOUTPUT) and helps to reject noise spikes and
short pulses. This input filter is applied to the HIN, LIN, and
EN inputs. The upper pair of waveforms (Example A) shows
an input signal duration (tINPUT) much longer than input
filter time (tFLTIN); it is approximately the same duration
between the input signal time (tINPUT) and the output signal
time (tOUTPUT). The lower pair of waveforms (Example B)
shows an input signal time (tINPUT) slightly longer than
input filter time (tFLTIN); it is approximately the same
duration between input signal time (tINPUT) and the output
signal time (tOUTPUT).
Protection Function
Shoot−Through Protection
The shoot−through protection circuitry prevents both
high− and low−side switches from conducting at the same
time, as shown in Figure 44.
HIN
LIN
Shoot−Through
Protection
HO
LO
After DT
IN
Example A
After DT
Example A
HIN
tFLTIN
tINPUT
tOUTPUT
OUT
LIN
Shoot−Through
Protection
IN
tINPUT
Example B
HO
LO
tOUTPUT
OUT
Example B
tFLTIN
Output duration is
same as input duration
Figure 46. Input Noise Filter Definition
Figure 44. Shoot−Through Protection
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15
FAN73912
Short−Pulsed Input Noise Rejection Method
DC+ Bus
The input filter circuitry provides protection against
short−pulsed input signals (HIN, LIN, and SD) on the input
signal lines by applied noise signal. If the input signal
duration is less than input filter time (tFLTIN), the output does
not change states. Example A and B of the Figure 47 show
the input and output waveforms with short−pulsed noise
spikes with a duration less than input filter time; the output
does not change states.
Q1
D1
iLOAD
iFREEWHEELING
VS
Load
Q2
D2
Example A
IN
tFLTIN
tFLTIN
tFLTIN
OUT
(LOW)
Figure 48. Half−Bridge Application Circuits
Example B
tFLTIN
OUT
(HIGH)
tFLTIN
This negative voltage can be trouble for the gate driver’s
output stage, there is the possibility to develop an
overvoltage condition of the bootstrap capacitor, input
signal missing and latch−up problems because it directly
affects the source VS pin of the gate driver, shown in
Figure 49. This undershoot voltage is called “negative VS
transient”.
tFLTIN
Figure 47. Noise Rejecting Input Filter Definition
Negative VS Transient
The bootstrap circuit has the advantage of being simple
and low cost, but has some limitations. The biggest difficulty
with this circuit is the negative voltage present at the emitter
of the high−side switching device when high−side switch is
turned−off in half−bridge application. If the high−side
switch, Q1, turns−off while the load current is flowing to an
inductive load, a current commutation occurs from
high−side switch, Q1, to the diode, D2, in parallel with the
low−side switch of the same inverter leg. Then the negative
voltage present at the emitter of the high−side switching
device, just before the freewheeling diode, D2, starts
clamping, causes load current to suddenly flow to the
low−side freewheeling diode, D2, as shown in Figure 48.
Q1
VS
GND
Freewheeling
Figure 49. VS Waveforms during Q1 Turn−Off
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16
FAN73912
Figure 50 and Figure 51 show the commutation of the load
current between high−side switch, Q1, and low−side
freewheeling diode, D3, in same inverter leg. The parasitic
inductances in the inverter circuit from the die wire bonding
to the PCB tracks are jumped together in LC and LE for each
IGBT. When the high−side switch, Q1, and low−side switch,
Q4, are turned on, the VS1 node is below DC+ voltage by the
voltage drops associated with the power switch and the
parasitic inductances of the circuit due to load current is
flows from Q1 and Q4, as shown in Figure 50. When the
high−side switch, Q1, is turned off and Q4, remained turned
on, the load current to flows the low−side freewheeling
diode, D3, due to the inductive load connected to VS1 as
shown in Figure 51. Q1 Turn−Off and D3 Conducting. The
current flows from ground (which is connected to the COM
pin of the gate driver) to the load and the negative voltage
present at the emitter of the high−side switching device. In
this case, the COM pin of the gate driver is at a higher
potential than the VS pin due to the voltage drops associated
with freewheeling diode, D3, and parasitic elements, LC3
and LE3.
The FAN73912 has a typical negative VS transient
characteristics, as shown in Figure 52.
0
−5
VS [V]
−10
VLC1
−30
−35
50
D1
LE1
VLE1
VS1
ifreewheeling
Q4
D3
D4
LE3
VLE4
LE4
Figure 50. Q1 and Q4 Turn−On
DC+ Bus
LC1
LC2
Q2
Q1
D1
D2
ifreewheeling
LE1
VS1
LC3
iLOAD
LE2
Load
VLC3
VS2
VLC4
LE3
LC4
Placement of Components
The recommended placement and selection of component
as follows:
• Place a bypass capacitor between the VCC and VSS
pins. A ceramic 1 mF capacitor is suitable for most
applications. This component should be placed as close
as possible to the pins to reduce parasitic elements.
Q4
Q3
D3
D4
VLE3
VLE4
300
Printed Circuit Board Layout
The layout recommended for minimized parasitic
elements is as follows:
• Direct tracks between switches with no loops or
deviation.
• Avoid interconnect links. These can add significant
inductance.
• Reduce the effect of lead−inductance by lowering
package height above the PCB.
• Consider co−locating both power switches to reduce
track length.
• To minimize noise coupling, the ground plane should
not be placed under or near the high−voltage floating
side.
• To reduce the EM coupling and improve the power
switch turn−on/off performance, the gate drive loops
must be reduced as much as possible.
LC4
Q3
250
General Guidelines
VS2
LC3
200
Even though the FAN73912 has been shown able to
handle these negative VS transient conditions, it is strongly
recommended that the circuit designer limit the negative VS
transient as much as possible by careful PCB layout to
minimize the value of parasitic elements and component
use. The amplitude of negative VS voltage is proportional to
the parasitic inductances and the turn−off speed, di/dt, of the
switching device.
LE2
Load
150
Figure 52. Negative VS Transient Characteristic
D2
iLOAD
100
Pulse Width [ns]
LC2
Q2
Q1
−20
−25
DC+ Bus
LC1
−15
LE4
Figure 51. Q1 Turn−Off and D3 Conducting
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17
FAN73912
• The bypass capacitor from VCC to VSS supports both
•
•
the low−side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
capacitor is recommended.
The bootstrap resistor, RBOOT, must be considered in
sizing the bootstrap resistance and the current
developed during initial bootstrap charge. If the resistor
is needed in series with the bootstrap diode, verify that
VB does not fall below COM (ground). Recommended
use is typically 5 ~ 10 W that increase the VBS time
constant. If the voltage drop of bootstrap resistor
and diode is too high or the circuit topology does not
allow a sufficient charging time, a fast recovery or
ultra−fast recovery diode can be used.
The bootstrap capacitor, CBOOT, uses a low−ESR
capacitor, such as ceramic capacitor. It is strongly
•
•
•
•
recommended that the placement of components is as
follows:
Place components tied to the floating voltage pins (VB
and VS) near the respective high−voltage portions of
the device and the FAN73912. Not Connected (NC)
pins in this package maximize the distance between
the high−voltage and low−voltage pins (see Figure 3).
Place and route for bypass capacitors and gate resistors
as close as possible to gate drive IC.
Locate the bootstrap diode, DBOOT, as close as possible
to bootstrap capacitor, CBOOT.
The bootstrap diode must use a lower forward voltage
drop and minimal switching time as soon as possible
for fast recovery or ultra−fast diode.
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18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16, 300 mils
CASE 751BH−01
ISSUE A
DATE 18 MAR 2009
D
SYMBOL
E1 E
MIN
NOM
MAX
2.49
2.64
A
2.36
A1
0.10
b
0.33
0.41
0.51
c
0.18
0.23
0.28
D
10.08
10.31
10.49
E
10.01
10.31
10.64
E1
7.39
7.49
7.59
0.30
1.27 BSC
e
h
0.25
L
0.38
θ
0º
0.75
0.81
1.27
8º
PIN #1 IDENTIFICATION
TOP VIEW
h
A
b
e
A1
SIDE VIEW
c
q
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34279E
SOIC−16, 300 MILS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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